1c7bb4fc1SJonas JensenDevice Tree Clock bindings for arch-moxart
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3c7bb4fc1SJonas JensenThis binding uses the common clock binding[1].
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5c7bb4fc1SJonas Jensen[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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7c7bb4fc1SJonas JensenMOXA ART SoCs allow to determine PLL output and APB frequencies
8c7bb4fc1SJonas Jensenby reading registers holding multiplier and divisor information.
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11c7bb4fc1SJonas JensenPLL:
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13c7bb4fc1SJonas JensenRequired properties:
14c7bb4fc1SJonas Jensen- compatible : Must be "moxa,moxart-pll-clock"
15c7bb4fc1SJonas Jensen- #clock-cells : Should be 0
16c7bb4fc1SJonas Jensen- reg : Should contain registers location and length
17c7bb4fc1SJonas Jensen- clocks : Should contain phandle + clock-specifier for the parent clock
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19c7bb4fc1SJonas JensenOptional properties:
20c7bb4fc1SJonas Jensen- clock-output-names : Should contain clock name
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23c7bb4fc1SJonas JensenAPB:
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25c7bb4fc1SJonas JensenRequired properties:
26c7bb4fc1SJonas Jensen- compatible : Must be "moxa,moxart-apb-clock"
27c7bb4fc1SJonas Jensen- #clock-cells : Should be 0
28c7bb4fc1SJonas Jensen- reg : Should contain registers location and length
29c7bb4fc1SJonas Jensen- clocks : Should contain phandle + clock-specifier for the parent clock
30c7bb4fc1SJonas Jensen
31c7bb4fc1SJonas JensenOptional properties:
32c7bb4fc1SJonas Jensen- clock-output-names : Should contain clock name
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35c7bb4fc1SJonas JensenFor example:
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37c7bb4fc1SJonas Jensen	clk_pll: clk_pll@98100000 {
38c7bb4fc1SJonas Jensen		compatible = "moxa,moxart-pll-clock";
39c7bb4fc1SJonas Jensen		#clock-cells = <0>;
40c7bb4fc1SJonas Jensen		reg = <0x98100000 0x34>;
41c7bb4fc1SJonas Jensen	};
42c7bb4fc1SJonas Jensen
43c7bb4fc1SJonas Jensen	clk_apb: clk_apb@98100000 {
44c7bb4fc1SJonas Jensen		compatible = "moxa,moxart-apb-clock";
45c7bb4fc1SJonas Jensen		#clock-cells = <0>;
46c7bb4fc1SJonas Jensen		reg = <0x98100000 0x34>;
47c7bb4fc1SJonas Jensen		clocks = <&clk_pll>;
48c7bb4fc1SJonas Jensen	};
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