1cfcefe36SJohnson Wang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2cfcefe36SJohnson Wang%YAML 1.2
3cfcefe36SJohnson Wang---
4cfcefe36SJohnson Wang$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
5cfcefe36SJohnson Wang$schema: http://devicetree.org/meta-schemas/core.yaml#
6cfcefe36SJohnson Wang
7cfcefe36SJohnson Wangtitle: MediaTek frequency hopping and spread spectrum clocking control
8cfcefe36SJohnson Wang
9cfcefe36SJohnson Wangmaintainers:
10cfcefe36SJohnson Wang  - Edward-JW Yang <edward-jw.yang@mediatek.com>
11cfcefe36SJohnson Wang
12cfcefe36SJohnson Wangdescription: |
13cfcefe36SJohnson Wang  Frequency hopping control (FHCTL) is a piece of hardware that control
14cfcefe36SJohnson Wang  some PLLs to adopt "hopping" mechanism to adjust their frequency.
15cfcefe36SJohnson Wang  Spread spectrum clocking (SSC) is another function provided by this hardware.
16cfcefe36SJohnson Wang
17cfcefe36SJohnson Wangproperties:
18cfcefe36SJohnson Wang  compatible:
19*4ba8590fSAngeloGioacchino Del Regno    enum:
20*4ba8590fSAngeloGioacchino Del Regno      - mediatek,mt6795-fhctl
21*4ba8590fSAngeloGioacchino Del Regno      - mediatek,mt8173-fhctl
22*4ba8590fSAngeloGioacchino Del Regno      - mediatek,mt8186-fhctl
23*4ba8590fSAngeloGioacchino Del Regno      - mediatek,mt8192-fhctl
24*4ba8590fSAngeloGioacchino Del Regno      - mediatek,mt8195-fhctl
25cfcefe36SJohnson Wang
26cfcefe36SJohnson Wang  reg:
27cfcefe36SJohnson Wang    maxItems: 1
28cfcefe36SJohnson Wang
29cfcefe36SJohnson Wang  clocks:
30cfcefe36SJohnson Wang    description: Phandles of the PLL with FHCTL hardware capability.
31cfcefe36SJohnson Wang    minItems: 1
32cfcefe36SJohnson Wang    maxItems: 30
33cfcefe36SJohnson Wang
34cfcefe36SJohnson Wang  mediatek,hopping-ssc-percent:
35cfcefe36SJohnson Wang    description: The percentage of spread spectrum clocking for one PLL.
36cfcefe36SJohnson Wang    minItems: 1
37cfcefe36SJohnson Wang    maxItems: 30
38cfcefe36SJohnson Wang    items:
39cfcefe36SJohnson Wang      default: 0
40cfcefe36SJohnson Wang      minimum: 0
41cfcefe36SJohnson Wang      maximum: 8
42cfcefe36SJohnson Wang
43cfcefe36SJohnson Wangrequired:
44cfcefe36SJohnson Wang  - compatible
45cfcefe36SJohnson Wang  - reg
46cfcefe36SJohnson Wang  - clocks
47cfcefe36SJohnson Wang
48cfcefe36SJohnson WangadditionalProperties: false
49cfcefe36SJohnson Wang
50cfcefe36SJohnson Wangexamples:
51cfcefe36SJohnson Wang  - |
52cfcefe36SJohnson Wang    #include <dt-bindings/clock/mt8186-clk.h>
53cfcefe36SJohnson Wang    fhctl: fhctl@1000ce00 {
54cfcefe36SJohnson Wang        compatible = "mediatek,mt8186-fhctl";
55cfcefe36SJohnson Wang        reg = <0x1000ce00 0x200>;
56cfcefe36SJohnson Wang        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
57cfcefe36SJohnson Wang        mediatek,hopping-ssc-percent = <3>;
58cfcefe36SJohnson Wang    };
59