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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
[all …]
H A Dxlnx,clocking-wizard.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
28 "#clock-cells":
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/openbmc/qemu/docs/system/arm/
H A Dxlnx-versal-virt.rst1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
12 The family of Versal SoCs share a single architecture but come in
16 The Xilinx Versal Virt board in QEMU is a model of a virtual board
17 (does not exist in reality) with a virtual Versal SoC without I/O
22 - 2 ACPUs (ARM Cortex-A72)
26 - Interrupt controller (ARM GICv3)
27 - 2 UARTs (ARM PL011)
28 - An RTC (Versal built-in)
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/openbmc/qemu/include/hw/arm/
H A Dxlnx-versal.h2 * Model of the Xilinx Versal
17 #include "hw/or-irq.h"
21 #include "hw/dma/xlnx-zdma.h"
23 #include "hw/rtc/xlnx-zynqmp-rtc.h"
25 #include "hw/usb/xlnx-usb-subsystem.h"
26 #include "hw/misc/xlnx-versal-xramc.h"
27 #include "hw/nvram/xlnx-bbram.h"
28 #include "hw/nvram/xlnx-versal-efuse.h"
29 #include "hw/ssi/xlnx-versal-ospi.h"
31 #include "hw/misc/xlnx-versal-crl.h"
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/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-cfu.h8 * SPDX-License-Identifier: GPL-2.0-or-later
11 * [1] Versal ACAP Technical Reference Manual,
12 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
14 * [2] Versal ACAP Register Reference,
15 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFU_CSR-Module
22 #include "hw/misc/xlnx-cfi-if.h"
25 #define TYPE_XLNX_VERSAL_CFU_APB "xlnx-versal-cfu-apb"
28 #define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx-versal-cfu-fdro"
31 #define TYPE_XLNX_VERSAL_CFU_SFR "xlnx-versal-cfu-sfr"
36 FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
[all …]
H A Dxlnx-versal-cframe-reg.h8 * SPDX-License-Identifier: GPL-2.0-or-later
11 * [1] Versal ACAP Technical Reference Manual,
12 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
14 * [2] Versal ACAP Register Reference,
15 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFRAME_REG-Module
22 #include "hw/misc/xlnx-cfi-if.h"
23 #include "hw/misc/xlnx-versal-cfu.h"
26 #define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx-cframe-reg"
29 #define TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "xlnx.cframe-bcast-reg"
92 FIELD(CFRM_ISR0, PER_FRAME_SEQ_ERROR, 8, 1)
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H A Dxlnx-versal-xramc.h5 * SPDX-License-Identifier: GPL-2.0-or-later
15 #define TYPE_XLNX_XRAM_CTRL "xlnx.versal-xramc"
76 FIELD(XRAM_PRDY_DBG, ISLAND2, 8, 4)
H A Dxlnx-versal-crl.h2 * QEMU model of the Clock-Reset-LPD (CRL).
5 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "target/arm/cpu-qom.h"
16 #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
37 FIELD(RPLL_CTRL, FBDIV, 8, 8)
57 FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
61 FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
65 FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
72 FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
76 FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
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/openbmc/u-boot/arch/arm/dts/
H A Dversal-mini-emmc1.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx Versal Mini eMMC1 Configuration
5 * (C) Copyright 2018-2019, Xilinx, Inc.
11 /dts-v1/;
14 compatible = "xlnx,versal";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 model = "Xilinx Versal MINI eMMC1";
20 compatible = "fixed-clock";
21 #clock-cells = <0x0>;
[all …]
H A Dversal-mini-emmc0.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx Versal Mini eMMC0 Configuration
5 * (C) Copyright 2018-2019, Xilinx, Inc.
11 /dts-v1/;
14 compatible = "xlnx,versal";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 model = "Xilinx Versal MINI eMMC0";
20 compatible = "fixed-clock";
21 #clock-cells = <0x0>;
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0+
3 dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb
4 dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
5 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
6 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
8 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
9 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
10 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
11 exynos4210-smdkv310.dtb \
12 exynos4210-universal_c210.dtb \
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/openbmc/qemu/tests/qtest/
H A Dxlnx-canfd-test.c2 * SPDX-License-Identifier: MIT
4 * QTests for the Xilinx Versal CANFD controller.
8 * Written-by: Vikram Garhwal<vikram.garhwal@amd.com>
119 qtest_writel(qts, CANFD0_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i, in enable_filters()
121 qtest_writel(qts, CANFD0_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i, in enable_filters()
125 qtest_writel(qts, CANFD1_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i, in enable_filters()
127 qtest_writel(qts, CANFD1_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i, in enable_filters()
172 for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) { in generate_random_data()
177 for (int i = 0; i < CAN_FRAME_SIZE - 2; i++) { in generate_random_data()
210 for (int i = 0; i < frame_size - 2; i++) { in read_data()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/openbmc/qemu/hw/arm/
H A Dxlnx-versal-virt.c2 * Xilinx Versal Virtual board.
13 #include "qemu/error-report.h"
20 #include "hw/qdev-properties.h"
21 #include "hw/arm/xlnx-versal.h"
26 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
34 Versal soc;
61 s->fdt = create_device_tree(&s->fdt_size); in fdt_create()
62 if (!s->fdt) { in fdt_create()
68 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); in fdt_create()
69 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { in fdt_create()
[all …]
/openbmc/linux/drivers/watchdog/
H A Dxilinx_wwdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Window watchdog device driver for Xilinx Versal WWDT
5 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
34 #define XWWDT_ESR_WSW_MASK BIT(8)
57 * struct xwwdt_device - Watchdog device structure
79 struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd; in xilinx_wwdt_start()
82 spin_lock(&xdev->spinlock); in xilinx_wwdt_start()
84 iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET); in xilinx_wwdt_start()
85 iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_start()
86 iowrite32((u32)xdev->closed_timeout, xdev->base + XWWDT_FWR_OFFSET); in xilinx_wwdt_start()
[all …]
/openbmc/qemu/hw/nvram/
H A Dxlnx-versal-efuse-cache.c26 #include "hw/nvram/xlnx-versal-efuse.h"
29 #include "hw/qdev-properties.h"
36 unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32); in efuse_cache_read()
37 unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32); in efuse_cache_read()
43 ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL); in efuse_cache_read()
46 ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL); in efuse_cache_read()
49 /* If 'addr' unaligned, the guest is always assumed to be little-endian. */ in efuse_cache_read()
52 ret >>= 8 * addr; in efuse_cache_read()
62 qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only", in efuse_cache_write()
81 memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s, in efuse_cache_init()
[all …]
H A Dxlnx-versal-efuse-ctrl.c2 * QEMU model of the Versal eFuse controller
27 #include "hw/nvram/xlnx-versal-efuse.h"
32 #include "hw/qdev-properties.h"
48 FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
58 FIELD(EFUSE_PGM_ADDR, ROW, 5, 8)
62 FIELD(EFUSE_RD_ADDR, ROW, 5, 8)
67 FIELD(TRD, VALUE, 0, 8)
69 FIELD(TSU_H_PS, VALUE, 0, 8)
71 FIELD(TSU_H_PS_CS, VALUE, 0, 8)
73 FIELD(TRDM, VALUE, 0, 8)
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpcie-xilinx-cpm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge
5 * (C) Copyright 2019 - 2020, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
45 #define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8
110 * struct xilinx_cpm_variant - CPM variant information
118 * struct xilinx_cpm_pcie - PCIe port information
145 return readl_relaxed(port->reg_base + reg); in pcie_read()
151 writel_relaxed(val, port->reg_base + reg); in pcie_write()
165 dev_dbg(port->dev, "Requester ID %lu\n", in cpm_pcie_clear_err_interrupts()
[all …]
/openbmc/linux/drivers/cdx/controller/
H A Dmc_cdx_pcol.h1 /* SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
19 * 0 7 8 16 20 22 23 24 31
22 * | | \--- Response
23 * | \------- Error
24 * \------------------------------ Resync (always set)
50 #define MCDI_HEADER_DATALEN_LBN 8
51 #define MCDI_HEADER_DATALEN_WIDTH 8
63 #define MCDI_HEADER_XFLAGS_WIDTH 8
76 * - To advance a shared memory request if XFLAGS_EVREQ was set
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
55 #define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8)
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-trng.c2 * Non-crypto strength model of the True Random Number Generator
3 * in the AMD/Xilinx Versal device family.
5 * Copyright (c) 2017-2020 Xilinx Inc.
29 #include "hw/misc/xlnx-versal-trng.h"
33 #include "qemu/error-report.h"
34 #include "qemu/guest-random.h"
38 #include "hw/qdev-properties.h"
60 FIELD(CTRL, EUMODE, 8, 1)
70 FIELD(CTRL_2, REPCOUNTTESTCUTOFF, 8, 9)
74 FIELD(CTRL_3, ADAPTPROPTESTCUTOFF, 8, 10)
[all …]
H A Dxlnx-versal-cfu.c10 * SPDX-License-Identifier: GPL-2.0-or-later
21 #include "hw/qdev-properties.h"
22 #include "hw/qdev-properties-system.h"
23 #include "hw/misc/xlnx-versal-cfu.h"
51 bool pending = s->regs[R_CFU_ISR] & ~s->regs[R_CFU_IMR]; in cfu_imr_update_irq()
52 qemu_set_irq(s->irq_cfu_imr, pending); in cfu_imr_update_irq()
57 XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque); in cfu_isr_postw()
63 XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque); in cfu_ier_prew()
66 s->regs[R_CFU_IMR] &= ~val; in cfu_ier_prew()
73 XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque); in cfu_idr_prew()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
149 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
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/openbmc/u-boot/arch/arm/
H A DKconfig14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
20 information that is embedded into the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
28 U-Boot typically uses a hard-coded value for the stack pointer
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that can be loaded and executed at arbitrary
41 Place a Linux kernel image header at the start of the U-Boot binary.
45 U-Boot needs to use, but which isn't part of the binary.
74 Do not enable instruction cache in U-Boot
[all …]

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