10  * SPDX-License-Identifier: GPL-2.0-or-later
21 #include "hw/qdev-properties.h"
22 #include "hw/qdev-properties-system.h"
23 #include "hw/misc/xlnx-versal-cfu.h"
51     bool pending = s->regs[R_CFU_ISR] & ~s->regs[R_CFU_IMR];  in cfu_imr_update_irq()
52     qemu_set_irq(s->irq_cfu_imr, pending);  in cfu_imr_update_irq()
57     XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);  in cfu_isr_postw()
63     XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);  in cfu_ier_prew()
66     s->regs[R_CFU_IMR] &= ~val;  in cfu_ier_prew()
73     XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);  in cfu_idr_prew()
76     s->regs[R_CFU_IMR] |= val;  in cfu_idr_prew()
83     XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);  in cfu_itr_prew()
86     s->regs[R_CFU_ISR] |= val;  in cfu_itr_prew()
93     XlnxVersalCFUAPB *s = XLNX_VERSAL_CFU_APB(reg->opaque);  in cfu_fgcr_postw()
98         ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_PASS, 1);  in cfu_fgcr_postw()
99         ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_DONE, 1);  in cfu_fgcr_postw()
167     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {  in cfu_apb_reset()
168         register_reset(&s->regs_info[i]);  in cfu_apb_reset()
170     memset(s->wfifo, 0, WFIFO_SZ * sizeof(uint32_t));  in cfu_apb_reset()
172     s->regs[R_CFU_STATUS] |= R_CFU_STATUS_HC_COMPLETE_MASK;  in cfu_apb_reset()
190         for (int i = 0; i < ARRAY_SIZE(s->cfg.cframe); i++) {  in cfu_transfer_cfi_packet()
191             if (s->cfg.cframe[i]) {  in cfu_transfer_cfi_packet()
192                 xlnx_cfi_transfer_packet(s->cfg.cframe[i], pkt);  in cfu_transfer_cfi_packet()
196             assert(row_addr < ARRAY_SIZE(s->cfg.cframe));  in cfu_transfer_cfi_packet()
198             if (s->cfg.cframe[row_addr]) {  in cfu_transfer_cfi_packet()
199                 xlnx_cfi_transfer_packet(s->cfg.cframe[row_addr], pkt);  in cfu_transfer_cfi_packet()
217     if (update_wfifo(addr, value, s->wfifo, wfifo)) {  in cfu_stream_write()
220         packet_type = extract32(wfifo[0], 24, 8);  in cfu_stream_write()
222         reg_addr = extract32(wfifo[0], 8, 6);  in cfu_stream_write()
225         if (ARRAY_FIELD_EX32(s->regs, CFU_CTL, DECOMPRESS) == 0) {  in cfu_stream_write()
226             if (s->regs[R_CFU_FDRI_CNT]) {  in cfu_stream_write()
235                 cfu_transfer_cfi_packet(s, s->fdri_row_addr, &pkt);  in cfu_stream_write()
237                 s->regs[R_CFU_FDRI_CNT]--;  in cfu_stream_write()
243                 s->regs[R_CFU_FDRI_CNT] = wfifo[1];  in cfu_stream_write()
246                 s->fdri_row_addr = row_addr;  in cfu_stream_write()
280     if (update_wfifo(addr, value, s->wfifo, wfifo)) {  in cfu_sfr_write()
286         if (s->cfg.cfu) {  in cfu_sfr_write()
287             cfu_transfer_cfi_packet(s->cfg.cfu, row_addr, &pkt);  in cfu_sfr_write()
297     if (!fifo32_is_empty(&s->fdro_data)) {  in cfu_fdro_read()
298         ret = fifo32_pop(&s->fdro_data);  in cfu_fdro_read()
317         .max_access_size = 8,
349     memory_region_init(&s->iomem, obj, TYPE_XLNX_VERSAL_CFU_APB, R_MAX * 4);  in cfu_apb_init()
353                               s->regs_info, s->regs,  in cfu_apb_init()
357     memory_region_add_subregion(&s->iomem,  in cfu_apb_init()
359                                 &reg_array->mem);  in cfu_apb_init()
360     sysbus_init_mmio(sbd, &s->iomem);  in cfu_apb_init()
362         name = g_strdup_printf(TYPE_XLNX_VERSAL_CFU_APB "-stream%d", i);  in cfu_apb_init()
363         memory_region_init_io(&s->iomem_stream[i], obj, &cfu_stream_ops, s,  in cfu_apb_init()
366         sysbus_init_mmio(sbd, &s->iomem_stream[i]);  in cfu_apb_init()
369     sysbus_init_irq(sbd, &s->irq_cfu_imr);  in cfu_apb_init()
377     memory_region_init_io(&s->iomem_sfr, obj, &cfu_sfr_ops, s,  in cfu_sfr_init()
379     sysbus_init_mmio(sbd, &s->iomem_sfr);  in cfu_sfr_init()
386     memset(s->wfifo, 0, WFIFO_SZ * sizeof(uint32_t));  in cfu_sfr_reset_enter()
394     memory_region_init_io(&s->iomem_fdro, obj, &cfu_fdro_ops, s,  in cfu_fdro_init()
396     sysbus_init_mmio(sbd, &s->iomem_fdro);  in cfu_fdro_init()
397     fifo32_create(&s->fdro_data, 8 * KiB / sizeof(uint32_t));  in cfu_fdro_init()
404     fifo32_destroy(&s->fdro_data);  in cfu_fdro_finalize()
411     fifo32_reset(&s->fdro_data);  in cfu_fdro_reset_enter()
418     if (fifo32_num_free(&s->fdro_data) >= ARRAY_SIZE(pkt->data)) {  in cfu_fdro_cfi_transfer_packet()
419         for (int i = 0; i < ARRAY_SIZE(pkt->data); i++) {  in cfu_fdro_cfi_transfer_packet()
420             fifo32_push(&s->fdro_data, pkt->data[i]);  in cfu_fdro_cfi_transfer_packet()
446         DEFINE_PROP_LINK("cframe8", XlnxVersalCFUAPB, cfg.cframe[8],
506     dc->vmsd = &vmstate_cfu_apb;  in cfu_apb_class_init()
516     dc->vmsd = &vmstate_cfu_fdro;  in cfu_fdro_class_init()
517     xcic->cfi_transfer_packet = cfu_fdro_cfi_transfer_packet;  in cfu_fdro_class_init()
518     rc->phases.enter = cfu_fdro_reset_enter;  in cfu_fdro_class_init()
527     dc->vmsd = &vmstate_cfu_sfr;  in cfu_sfr_class_init()
528     rc->phases.enter = cfu_sfr_reset_enter;  in cfu_sfr_class_init()