2  * QEMU model of the Versal eFuse controller
27 #include "hw/nvram/xlnx-versal-efuse.h"
32 #include "hw/qdev-properties.h"
48     FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
58     FIELD(EFUSE_PGM_ADDR, ROW, 5, 8)
62     FIELD(EFUSE_RD_ADDR, ROW, 5, 8)
67     FIELD(TRD, VALUE, 0, 8)
69     FIELD(TSU_H_PS, VALUE, 0, 8)
71     FIELD(TSU_H_PS_CS, VALUE, 0, 8)
73     FIELD(TRDM, VALUE, 0, 8)
75     FIELD(TSU_H_CS, VALUE, 0, 8)
84     FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1)
101     FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1)
118     FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1)
135     FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1)
161 …*   https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse…
193 #define EFUSE_PPK2_WR_LK            BIT_POS(43, 8)
220 QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs));
229     bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR];  in efuse_imr_update_irq()
230     qemu_set_irq(s->irq_efuse_imr, pending);  in efuse_imr_update_irq()
235     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_isr_postw()
241     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_ier_prew()
244     s->regs[R_EFUSE_IMR] &= ~val;  in efuse_ier_prew()
251     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_idr_prew()
254     s->regs[R_EFUSE_IMR] |= val;  in efuse_idr_prew()
261     uint32_t check = xlnx_efuse_tbits_check(s->efuse);  in efuse_status_tbits_sync()
262     uint32_t val = s->regs[R_STATUS];  in efuse_status_tbits_sync()
268     s->regs[R_STATUS] = val;  in efuse_status_tbits_sync()
275     if (!s->efuse || !s->efuse->init_tbits) {  in efuse_anchor_bits_check()
279     for (page = 0; page < s->efuse->efuse_nr; page++) {  in efuse_anchor_bits_check()
286         if (!xlnx_efuse_get_bit(s->efuse, bit)) {  in efuse_anchor_bits_check()
287             xlnx_efuse_set_bit(s->efuse, bit);  in efuse_anchor_bits_check()
291         if (!xlnx_efuse_get_bit(s->efuse, bit)) {  in efuse_anchor_bits_check()
292             xlnx_efuse_set_bit(s->efuse, bit);  in efuse_anchor_bits_check()
301     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_key_crc_check()
306      * if CRC-check fails or CRC-check disabled by lock fuse.  in efuse_key_crc_check()
308     r = s->regs[R_STATUS] | done_mask | pass_mask;  in efuse_key_crc_check()
310     lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask;  in efuse_key_crc_check()
311     if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) {  in efuse_key_crc_check()
315     s->regs[R_STATUS] = r ^ pass_mask;  in efuse_key_crc_check()
325     uint16_t r1 = ((const XlnxEFuseLkSpec *)a)->row;  in efuse_lk_spec_cmp()
326     uint16_t r2 = ((const XlnxEFuseLkSpec *)b)->row;  in efuse_lk_spec_cmp()
328     return (r1 > r2) - (r1 < r2);  in efuse_lk_spec_cmp()
333     XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;  in efuse_lk_spec_sort()
334     const uint32_t n8 = s->extra_pg0_lock_n16 * 2;  in efuse_lk_spec_sort()
345     const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;  in efuse_lk_spec_find()
346     const uint32_t n8  = s->extra_pg0_lock_n16 * 2;  in efuse_lk_spec_find()
357     return item ? item->lk_bit : 0;  in efuse_lk_spec_find()
362     /* Hard-coded locks */  in efuse_bit_locked()
367         [8 ... 11]  = EFUSE_DNA_WR_LK,  in efuse_bit_locked()
388     if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {  in efuse_pgm_locked()
395         if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) &&  in efuse_pgm_locked()
417         lock = xlnx_efuse_get_bit(s->efuse, lock);  in efuse_pgm_locked()
426     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_pgm_addr_postw()
430     /* Always zero out PGM_ADDR because it is write-only */  in efuse_pgm_addr_postw()
431     s->regs[R_EFUSE_PGM_ADDR] = 0;  in efuse_pgm_addr_postw()
434      * Indicate error if bit is write-protected (or read-only  in efuse_pgm_addr_postw()
451     } else if (xlnx_efuse_set_bit(s->efuse, bit)) {  in efuse_pgm_addr_postw()
459         ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);  in efuse_pgm_addr_postw()
462     ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);  in efuse_pgm_addr_postw()
468     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_rd_addr_postw()
472     /* Always zero out RD_ADDR because it is write-only */  in efuse_rd_addr_postw()
473     s->regs[R_EFUSE_RD_ADDR] = 0;  in efuse_rd_addr_postw()
476      * Indicate error if row is read-blocked.  in efuse_rd_addr_postw()
481     s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse,  in efuse_rd_addr_postw()
492         ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);  in efuse_rd_addr_postw()
495     ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);  in efuse_rd_addr_postw()
502     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_cache_load_prew()
507         ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);  in efuse_cache_load_prew()
516     XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);  in efuse_pgm_lock_prew()
522     val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK);  in efuse_pgm_lock_prew()
627     dev = reg_array->mem.owner;  in efuse_ctrl_reg_write()
632     if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {  in efuse_ctrl_reg_write()
645     if (!reg->data || !reg->access) {  in efuse_ctrl_register_reset()
650     switch (reg->access->addr) {  in efuse_ctrl_register_reset()
654         *(uint32_t *)reg->data = reg->access->reset;  in efuse_ctrl_register_reset()
666     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {  in efuse_ctrl_reset_hold()
667         efuse_ctrl_register_reset(&s->regs_info[i]);  in efuse_ctrl_reset_hold()
690     if (!s->efuse) {  in efuse_ctrl_realize()
693         error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",  in efuse_ctrl_realize()
698     /* Sort property-defined pgm-locks for bsearch lookup */  in efuse_ctrl_realize()
699     if ((s->extra_pg0_lock_n16 % lks_sz) != 0) {  in efuse_ctrl_realize()
703                    "%s.pg0-lock: array property item-count not multiple of %u",  in efuse_ctrl_realize()
716     s->reg_array =  in efuse_ctrl_init()
719                               s->regs_info, s->regs,  in efuse_ctrl_init()
724     sysbus_init_mmio(sbd, &s->reg_array->mem);  in efuse_ctrl_init()
725     sysbus_init_irq(sbd, &s->irq_efuse_imr);  in efuse_ctrl_init()
732     register_finalize_block(s->reg_array);  in efuse_ctrl_finalize()
733     g_free(s->extra_pg0_lock_spec);  in efuse_ctrl_finalize()
750     DEFINE_PROP_ARRAY("pg0-lock",
762     rc->phases.hold = efuse_ctrl_reset_hold;  in efuse_ctrl_class_init()
763     dc->realize = efuse_ctrl_realize;  in efuse_ctrl_class_init()
764     dc->vmsd = &vmstate_efuse_ctrl;  in efuse_ctrl_class_init()