Lines Matching +full:versal +full:- +full:8

2  * QEMU model of the Clock-Reset-LPD (CRL).
5  * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "target/arm/cpu-qom.h"
16 #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
37     FIELD(RPLL_CTRL, FBDIV, 8, 8)
57     FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
61     FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
65     FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
72     FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
76     FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
82     FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
88     FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
92     FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
96     FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
100     FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
104     FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
108     FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
112     FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
116     FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
120     FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
124     FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
128     FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
132     FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
136     FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
140     FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
144     FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
148     FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
152     FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
225         DeviceState *adma[8];