1*0fbd2a82SSiva Durga Prasad Paladugu// SPDX-License-Identifier: GPL-2.0 2*0fbd2a82SSiva Durga Prasad Paladugu/* 3*0fbd2a82SSiva Durga Prasad Paladugu * dts file for Xilinx Versal Mini eMMC0 Configuration 4*0fbd2a82SSiva Durga Prasad Paladugu * 5*0fbd2a82SSiva Durga Prasad Paladugu * (C) Copyright 2018-2019, Xilinx, Inc. 6*0fbd2a82SSiva Durga Prasad Paladugu * 7*0fbd2a82SSiva Durga Prasad Paladugu * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> 8*0fbd2a82SSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 9*0fbd2a82SSiva Durga Prasad Paladugu */ 10*0fbd2a82SSiva Durga Prasad Paladugu 11*0fbd2a82SSiva Durga Prasad Paladugu/dts-v1/; 12*0fbd2a82SSiva Durga Prasad Paladugu 13*0fbd2a82SSiva Durga Prasad Paladugu/ { 14*0fbd2a82SSiva Durga Prasad Paladugu compatible = "xlnx,versal"; 15*0fbd2a82SSiva Durga Prasad Paladugu #address-cells = <2>; 16*0fbd2a82SSiva Durga Prasad Paladugu #size-cells = <2>; 17*0fbd2a82SSiva Durga Prasad Paladugu model = "Xilinx Versal MINI eMMC0"; 18*0fbd2a82SSiva Durga Prasad Paladugu 19*0fbd2a82SSiva Durga Prasad Paladugu clk25: clk25 { 20*0fbd2a82SSiva Durga Prasad Paladugu compatible = "fixed-clock"; 21*0fbd2a82SSiva Durga Prasad Paladugu #clock-cells = <0x0>; 22*0fbd2a82SSiva Durga Prasad Paladugu clock-frequency = <25000000>; 23*0fbd2a82SSiva Durga Prasad Paladugu }; 24*0fbd2a82SSiva Durga Prasad Paladugu 25*0fbd2a82SSiva Durga Prasad Paladugu dcc: dcc { 26*0fbd2a82SSiva Durga Prasad Paladugu compatible = "arm,dcc"; 27*0fbd2a82SSiva Durga Prasad Paladugu status = "okay"; 28*0fbd2a82SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 29*0fbd2a82SSiva Durga Prasad Paladugu }; 30*0fbd2a82SSiva Durga Prasad Paladugu 31*0fbd2a82SSiva Durga Prasad Paladugu amba: amba { 32*0fbd2a82SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 33*0fbd2a82SSiva Durga Prasad Paladugu compatible = "simple-bus"; 34*0fbd2a82SSiva Durga Prasad Paladugu #address-cells = <0x2>; 35*0fbd2a82SSiva Durga Prasad Paladugu #size-cells = <0x2>; 36*0fbd2a82SSiva Durga Prasad Paladugu ranges; 37*0fbd2a82SSiva Durga Prasad Paladugu 38*0fbd2a82SSiva Durga Prasad Paladugu sdhci0: sdhci@f1040000 { 39*0fbd2a82SSiva Durga Prasad Paladugu compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; 40*0fbd2a82SSiva Durga Prasad Paladugu status = "okay"; 41*0fbd2a82SSiva Durga Prasad Paladugu reg = <0x0 0xf1040000 0x0 0x10000>; 42*0fbd2a82SSiva Durga Prasad Paladugu clock-names = "clk_xin", "clk_ahb"; 43*0fbd2a82SSiva Durga Prasad Paladugu clocks = <&clk25 &clk25>; 44*0fbd2a82SSiva Durga Prasad Paladugu xlnx,device_id = <0>; 45*0fbd2a82SSiva Durga Prasad Paladugu no-1-8-v; 46*0fbd2a82SSiva Durga Prasad Paladugu xlnx,mio_bank = <0>; 47*0fbd2a82SSiva Durga Prasad Paladugu #stream-id-cells = <1>; 48*0fbd2a82SSiva Durga Prasad Paladugu }; 49*0fbd2a82SSiva Durga Prasad Paladugu }; 50*0fbd2a82SSiva Durga Prasad Paladugu 51*0fbd2a82SSiva Durga Prasad Paladugu aliases { 52*0fbd2a82SSiva Durga Prasad Paladugu serial0 = &dcc; 53*0fbd2a82SSiva Durga Prasad Paladugu mmc0 = &sdhci0; 54*0fbd2a82SSiva Durga Prasad Paladugu }; 55*0fbd2a82SSiva Durga Prasad Paladugu 56*0fbd2a82SSiva Durga Prasad Paladugu chosen { 57*0fbd2a82SSiva Durga Prasad Paladugu stdout-path = "serial0:115200"; 58*0fbd2a82SSiva Durga Prasad Paladugu }; 59*0fbd2a82SSiva Durga Prasad Paladugu 60*0fbd2a82SSiva Durga Prasad Paladugu memory@0 { 61*0fbd2a82SSiva Durga Prasad Paladugu device_type = "memory"; 62*0fbd2a82SSiva Durga Prasad Paladugu reg = <0x0 0x0 0x0 0x20000000>; 63*0fbd2a82SSiva Durga Prasad Paladugu }; 64*0fbd2a82SSiva Durga Prasad Paladugu}; 65