1*369e5cb0SEdgar E. Iglesias /* 2*369e5cb0SEdgar E. Iglesias * QEMU model of the Clock-Reset-LPD (CRL). 3*369e5cb0SEdgar E. Iglesias * 4*369e5cb0SEdgar E. Iglesias * Copyright (c) 2022 Xilinx Inc. 5*369e5cb0SEdgar E. Iglesias * SPDX-License-Identifier: GPL-2.0-or-later 6*369e5cb0SEdgar E. Iglesias * 7*369e5cb0SEdgar E. Iglesias * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> 8*369e5cb0SEdgar E. Iglesias */ 9*369e5cb0SEdgar E. Iglesias #ifndef HW_MISC_XLNX_VERSAL_CRL_H 10*369e5cb0SEdgar E. Iglesias #define HW_MISC_XLNX_VERSAL_CRL_H 11*369e5cb0SEdgar E. Iglesias 12*369e5cb0SEdgar E. Iglesias #include "hw/sysbus.h" 13*369e5cb0SEdgar E. Iglesias #include "hw/register.h" 14*369e5cb0SEdgar E. Iglesias #include "target/arm/cpu.h" 15*369e5cb0SEdgar E. Iglesias 16*369e5cb0SEdgar E. Iglesias #define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl" 17*369e5cb0SEdgar E. Iglesias OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) 18*369e5cb0SEdgar E. Iglesias 19*369e5cb0SEdgar E. Iglesias REG32(ERR_CTRL, 0x0) 20*369e5cb0SEdgar E. Iglesias FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) 21*369e5cb0SEdgar E. Iglesias REG32(IR_STATUS, 0x4) 22*369e5cb0SEdgar E. Iglesias FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) 23*369e5cb0SEdgar E. Iglesias REG32(IR_MASK, 0x8) 24*369e5cb0SEdgar E. Iglesias FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) 25*369e5cb0SEdgar E. Iglesias REG32(IR_ENABLE, 0xc) 26*369e5cb0SEdgar E. Iglesias FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) 27*369e5cb0SEdgar E. Iglesias REG32(IR_DISABLE, 0x10) 28*369e5cb0SEdgar E. Iglesias FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) 29*369e5cb0SEdgar E. Iglesias REG32(WPROT, 0x1c) 30*369e5cb0SEdgar E. Iglesias FIELD(WPROT, ACTIVE, 0, 1) 31*369e5cb0SEdgar E. Iglesias REG32(PLL_CLK_OTHER_DMN, 0x20) 32*369e5cb0SEdgar E. Iglesias FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) 33*369e5cb0SEdgar E. Iglesias REG32(RPLL_CTRL, 0x40) 34*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CTRL, POST_SRC, 24, 3) 35*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CTRL, PRE_SRC, 20, 3) 36*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) 37*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CTRL, FBDIV, 8, 8) 38*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CTRL, BYPASS, 3, 1) 39*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CTRL, RESET, 0, 1) 40*369e5cb0SEdgar E. Iglesias REG32(RPLL_CFG, 0x44) 41*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CFG, LOCK_DLY, 25, 7) 42*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CFG, LOCK_CNT, 13, 10) 43*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CFG, LFHF, 10, 2) 44*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CFG, CP, 5, 4) 45*369e5cb0SEdgar E. Iglesias FIELD(RPLL_CFG, RES, 0, 4) 46*369e5cb0SEdgar E. Iglesias REG32(RPLL_FRAC_CFG, 0x48) 47*369e5cb0SEdgar E. Iglesias FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) 48*369e5cb0SEdgar E. Iglesias FIELD(RPLL_FRAC_CFG, SEED, 22, 3) 49*369e5cb0SEdgar E. Iglesias FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) 50*369e5cb0SEdgar E. Iglesias FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) 51*369e5cb0SEdgar E. Iglesias FIELD(RPLL_FRAC_CFG, DATA, 0, 16) 52*369e5cb0SEdgar E. Iglesias REG32(PLL_STATUS, 0x50) 53*369e5cb0SEdgar E. Iglesias FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) 54*369e5cb0SEdgar E. Iglesias FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) 55*369e5cb0SEdgar E. Iglesias REG32(RPLL_TO_XPD_CTRL, 0x100) 56*369e5cb0SEdgar E. Iglesias FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) 57*369e5cb0SEdgar E. Iglesias FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) 58*369e5cb0SEdgar E. Iglesias REG32(LPD_TOP_SWITCH_CTRL, 0x104) 59*369e5cb0SEdgar E. Iglesias FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) 60*369e5cb0SEdgar E. Iglesias FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) 61*369e5cb0SEdgar E. Iglesias FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) 62*369e5cb0SEdgar E. Iglesias FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) 63*369e5cb0SEdgar E. Iglesias REG32(LPD_LSBUS_CTRL, 0x108) 64*369e5cb0SEdgar E. Iglesias FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) 65*369e5cb0SEdgar E. Iglesias FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) 66*369e5cb0SEdgar E. Iglesias FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) 67*369e5cb0SEdgar E. Iglesias REG32(CPU_R5_CTRL, 0x10c) 68*369e5cb0SEdgar E. Iglesias FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) 69*369e5cb0SEdgar E. Iglesias FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) 70*369e5cb0SEdgar E. Iglesias FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) 71*369e5cb0SEdgar E. Iglesias FIELD(CPU_R5_CTRL, CLKACT, 25, 1) 72*369e5cb0SEdgar E. Iglesias FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) 73*369e5cb0SEdgar E. Iglesias FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) 74*369e5cb0SEdgar E. Iglesias REG32(IOU_SWITCH_CTRL, 0x114) 75*369e5cb0SEdgar E. Iglesias FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) 76*369e5cb0SEdgar E. Iglesias FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) 77*369e5cb0SEdgar E. Iglesias FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) 78*369e5cb0SEdgar E. Iglesias REG32(GEM0_REF_CTRL, 0x118) 79*369e5cb0SEdgar E. Iglesias FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) 80*369e5cb0SEdgar E. Iglesias FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) 81*369e5cb0SEdgar E. Iglesias FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) 82*369e5cb0SEdgar E. Iglesias FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) 83*369e5cb0SEdgar E. Iglesias FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) 84*369e5cb0SEdgar E. Iglesias REG32(GEM1_REF_CTRL, 0x11c) 85*369e5cb0SEdgar E. Iglesias FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) 86*369e5cb0SEdgar E. Iglesias FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) 87*369e5cb0SEdgar E. Iglesias FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) 88*369e5cb0SEdgar E. Iglesias FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) 89*369e5cb0SEdgar E. Iglesias FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) 90*369e5cb0SEdgar E. Iglesias REG32(GEM_TSU_REF_CTRL, 0x120) 91*369e5cb0SEdgar E. Iglesias FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) 92*369e5cb0SEdgar E. Iglesias FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) 93*369e5cb0SEdgar E. Iglesias FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) 94*369e5cb0SEdgar E. Iglesias REG32(USB0_BUS_REF_CTRL, 0x124) 95*369e5cb0SEdgar E. Iglesias FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) 96*369e5cb0SEdgar E. Iglesias FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) 97*369e5cb0SEdgar E. Iglesias FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) 98*369e5cb0SEdgar E. Iglesias REG32(UART0_REF_CTRL, 0x128) 99*369e5cb0SEdgar E. Iglesias FIELD(UART0_REF_CTRL, CLKACT, 25, 1) 100*369e5cb0SEdgar E. Iglesias FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) 101*369e5cb0SEdgar E. Iglesias FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) 102*369e5cb0SEdgar E. Iglesias REG32(UART1_REF_CTRL, 0x12c) 103*369e5cb0SEdgar E. Iglesias FIELD(UART1_REF_CTRL, CLKACT, 25, 1) 104*369e5cb0SEdgar E. Iglesias FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) 105*369e5cb0SEdgar E. Iglesias FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) 106*369e5cb0SEdgar E. Iglesias REG32(SPI0_REF_CTRL, 0x130) 107*369e5cb0SEdgar E. Iglesias FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) 108*369e5cb0SEdgar E. Iglesias FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) 109*369e5cb0SEdgar E. Iglesias FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) 110*369e5cb0SEdgar E. Iglesias REG32(SPI1_REF_CTRL, 0x134) 111*369e5cb0SEdgar E. Iglesias FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) 112*369e5cb0SEdgar E. Iglesias FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) 113*369e5cb0SEdgar E. Iglesias FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) 114*369e5cb0SEdgar E. Iglesias REG32(CAN0_REF_CTRL, 0x138) 115*369e5cb0SEdgar E. Iglesias FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) 116*369e5cb0SEdgar E. Iglesias FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) 117*369e5cb0SEdgar E. Iglesias FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) 118*369e5cb0SEdgar E. Iglesias REG32(CAN1_REF_CTRL, 0x13c) 119*369e5cb0SEdgar E. Iglesias FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) 120*369e5cb0SEdgar E. Iglesias FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) 121*369e5cb0SEdgar E. Iglesias FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) 122*369e5cb0SEdgar E. Iglesias REG32(I2C0_REF_CTRL, 0x140) 123*369e5cb0SEdgar E. Iglesias FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) 124*369e5cb0SEdgar E. Iglesias FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) 125*369e5cb0SEdgar E. Iglesias FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) 126*369e5cb0SEdgar E. Iglesias REG32(I2C1_REF_CTRL, 0x144) 127*369e5cb0SEdgar E. Iglesias FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) 128*369e5cb0SEdgar E. Iglesias FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) 129*369e5cb0SEdgar E. Iglesias FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) 130*369e5cb0SEdgar E. Iglesias REG32(DBG_LPD_CTRL, 0x148) 131*369e5cb0SEdgar E. Iglesias FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) 132*369e5cb0SEdgar E. Iglesias FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) 133*369e5cb0SEdgar E. Iglesias FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) 134*369e5cb0SEdgar E. Iglesias REG32(TIMESTAMP_REF_CTRL, 0x14c) 135*369e5cb0SEdgar E. Iglesias FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) 136*369e5cb0SEdgar E. Iglesias FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) 137*369e5cb0SEdgar E. Iglesias FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) 138*369e5cb0SEdgar E. Iglesias REG32(CRL_SAFETY_CHK, 0x150) 139*369e5cb0SEdgar E. Iglesias REG32(PSM_REF_CTRL, 0x154) 140*369e5cb0SEdgar E. Iglesias FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) 141*369e5cb0SEdgar E. Iglesias FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) 142*369e5cb0SEdgar E. Iglesias REG32(DBG_TSTMP_CTRL, 0x158) 143*369e5cb0SEdgar E. Iglesias FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) 144*369e5cb0SEdgar E. Iglesias FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) 145*369e5cb0SEdgar E. Iglesias FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) 146*369e5cb0SEdgar E. Iglesias REG32(CPM_TOPSW_REF_CTRL, 0x15c) 147*369e5cb0SEdgar E. Iglesias FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) 148*369e5cb0SEdgar E. Iglesias FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) 149*369e5cb0SEdgar E. Iglesias FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) 150*369e5cb0SEdgar E. Iglesias REG32(USB3_DUAL_REF_CTRL, 0x160) 151*369e5cb0SEdgar E. Iglesias FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) 152*369e5cb0SEdgar E. Iglesias FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) 153*369e5cb0SEdgar E. Iglesias FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) 154*369e5cb0SEdgar E. Iglesias REG32(RST_CPU_R5, 0x300) 155*369e5cb0SEdgar E. Iglesias FIELD(RST_CPU_R5, RESET_PGE, 4, 1) 156*369e5cb0SEdgar E. Iglesias FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) 157*369e5cb0SEdgar E. Iglesias FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) 158*369e5cb0SEdgar E. Iglesias FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) 159*369e5cb0SEdgar E. Iglesias REG32(RST_ADMA, 0x304) 160*369e5cb0SEdgar E. Iglesias FIELD(RST_ADMA, RESET, 0, 1) 161*369e5cb0SEdgar E. Iglesias REG32(RST_GEM0, 0x308) 162*369e5cb0SEdgar E. Iglesias FIELD(RST_GEM0, RESET, 0, 1) 163*369e5cb0SEdgar E. Iglesias REG32(RST_GEM1, 0x30c) 164*369e5cb0SEdgar E. Iglesias FIELD(RST_GEM1, RESET, 0, 1) 165*369e5cb0SEdgar E. Iglesias REG32(RST_SPARE, 0x310) 166*369e5cb0SEdgar E. Iglesias FIELD(RST_SPARE, RESET, 0, 1) 167*369e5cb0SEdgar E. Iglesias REG32(RST_USB0, 0x314) 168*369e5cb0SEdgar E. Iglesias FIELD(RST_USB0, RESET, 0, 1) 169*369e5cb0SEdgar E. Iglesias REG32(RST_UART0, 0x318) 170*369e5cb0SEdgar E. Iglesias FIELD(RST_UART0, RESET, 0, 1) 171*369e5cb0SEdgar E. Iglesias REG32(RST_UART1, 0x31c) 172*369e5cb0SEdgar E. Iglesias FIELD(RST_UART1, RESET, 0, 1) 173*369e5cb0SEdgar E. Iglesias REG32(RST_SPI0, 0x320) 174*369e5cb0SEdgar E. Iglesias FIELD(RST_SPI0, RESET, 0, 1) 175*369e5cb0SEdgar E. Iglesias REG32(RST_SPI1, 0x324) 176*369e5cb0SEdgar E. Iglesias FIELD(RST_SPI1, RESET, 0, 1) 177*369e5cb0SEdgar E. Iglesias REG32(RST_CAN0, 0x328) 178*369e5cb0SEdgar E. Iglesias FIELD(RST_CAN0, RESET, 0, 1) 179*369e5cb0SEdgar E. Iglesias REG32(RST_CAN1, 0x32c) 180*369e5cb0SEdgar E. Iglesias FIELD(RST_CAN1, RESET, 0, 1) 181*369e5cb0SEdgar E. Iglesias REG32(RST_I2C0, 0x330) 182*369e5cb0SEdgar E. Iglesias FIELD(RST_I2C0, RESET, 0, 1) 183*369e5cb0SEdgar E. Iglesias REG32(RST_I2C1, 0x334) 184*369e5cb0SEdgar E. Iglesias FIELD(RST_I2C1, RESET, 0, 1) 185*369e5cb0SEdgar E. Iglesias REG32(RST_DBG_LPD, 0x338) 186*369e5cb0SEdgar E. Iglesias FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) 187*369e5cb0SEdgar E. Iglesias FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) 188*369e5cb0SEdgar E. Iglesias FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) 189*369e5cb0SEdgar E. Iglesias FIELD(RST_DBG_LPD, RESET, 0, 1) 190*369e5cb0SEdgar E. Iglesias REG32(RST_GPIO, 0x33c) 191*369e5cb0SEdgar E. Iglesias FIELD(RST_GPIO, RESET, 0, 1) 192*369e5cb0SEdgar E. Iglesias REG32(RST_TTC, 0x344) 193*369e5cb0SEdgar E. Iglesias FIELD(RST_TTC, TTC3_RESET, 3, 1) 194*369e5cb0SEdgar E. Iglesias FIELD(RST_TTC, TTC2_RESET, 2, 1) 195*369e5cb0SEdgar E. Iglesias FIELD(RST_TTC, TTC1_RESET, 1, 1) 196*369e5cb0SEdgar E. Iglesias FIELD(RST_TTC, TTC0_RESET, 0, 1) 197*369e5cb0SEdgar E. Iglesias REG32(RST_TIMESTAMP, 0x348) 198*369e5cb0SEdgar E. Iglesias FIELD(RST_TIMESTAMP, RESET, 0, 1) 199*369e5cb0SEdgar E. Iglesias REG32(RST_SWDT, 0x34c) 200*369e5cb0SEdgar E. Iglesias FIELD(RST_SWDT, RESET, 0, 1) 201*369e5cb0SEdgar E. Iglesias REG32(RST_OCM, 0x350) 202*369e5cb0SEdgar E. Iglesias FIELD(RST_OCM, RESET, 0, 1) 203*369e5cb0SEdgar E. Iglesias REG32(RST_IPI, 0x354) 204*369e5cb0SEdgar E. Iglesias FIELD(RST_IPI, RESET, 0, 1) 205*369e5cb0SEdgar E. Iglesias REG32(RST_SYSMON, 0x358) 206*369e5cb0SEdgar E. Iglesias FIELD(RST_SYSMON, SEQ_RST, 1, 1) 207*369e5cb0SEdgar E. Iglesias FIELD(RST_SYSMON, CFG_RST, 0, 1) 208*369e5cb0SEdgar E. Iglesias REG32(RST_FPD, 0x360) 209*369e5cb0SEdgar E. Iglesias FIELD(RST_FPD, SRST, 1, 1) 210*369e5cb0SEdgar E. Iglesias FIELD(RST_FPD, POR, 0, 1) 211*369e5cb0SEdgar E. Iglesias REG32(PSM_RST_MODE, 0x370) 212*369e5cb0SEdgar E. Iglesias FIELD(PSM_RST_MODE, WAKEUP, 2, 1) 213*369e5cb0SEdgar E. Iglesias FIELD(PSM_RST_MODE, RST_MODE, 0, 2) 214*369e5cb0SEdgar E. Iglesias 215*369e5cb0SEdgar E. Iglesias #define CRL_R_MAX (R_PSM_RST_MODE + 1) 216*369e5cb0SEdgar E. Iglesias 217*369e5cb0SEdgar E. Iglesias #define RPU_MAX_CPU 2 218*369e5cb0SEdgar E. Iglesias 219*369e5cb0SEdgar E. Iglesias struct XlnxVersalCRL { 220*369e5cb0SEdgar E. Iglesias SysBusDevice parent_obj; 221*369e5cb0SEdgar E. Iglesias qemu_irq irq; 222*369e5cb0SEdgar E. Iglesias 223*369e5cb0SEdgar E. Iglesias struct { 224*369e5cb0SEdgar E. Iglesias ARMCPU *cpu_r5[RPU_MAX_CPU]; 225*369e5cb0SEdgar E. Iglesias DeviceState *adma[8]; 226*369e5cb0SEdgar E. Iglesias DeviceState *uart[2]; 227*369e5cb0SEdgar E. Iglesias DeviceState *gem[2]; 228*369e5cb0SEdgar E. Iglesias DeviceState *usb; 229*369e5cb0SEdgar E. Iglesias } cfg; 230*369e5cb0SEdgar E. Iglesias 231*369e5cb0SEdgar E. Iglesias RegisterInfoArray *reg_array; 232*369e5cb0SEdgar E. Iglesias uint32_t regs[CRL_R_MAX]; 233*369e5cb0SEdgar E. Iglesias RegisterInfo regs_info[CRL_R_MAX]; 234*369e5cb0SEdgar E. Iglesias }; 235*369e5cb0SEdgar E. Iglesias #endif 236