Revision tags: v9.1.0 |
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#
a7538ca0 |
| 19-Mar-2024 |
Cédric Le Goater <clg@redhat.com> |
aspeed/smc: Only wire flash devices at reset
The Aspeed machines have many Static Memory Controllers (SMC), up to 8, which can only drive flash memory devices. Commit 27a2c66c92ec ("aspeed/smc: Wire
aspeed/smc: Only wire flash devices at reset
The Aspeed machines have many Static Memory Controllers (SMC), up to 8, which can only drive flash memory devices. Commit 27a2c66c92ec ("aspeed/smc: Wire CS lines at reset") tried to ease the definitions of these devices by allowing flash devices from the command line to be attached to a SSI bus. For that, the wiring of the CS lines of the Aspeed SMC controller was moved at reset. Two assumptions are made though, first that the device has a SSI_GPIO_CS GPIO line, which is not always the case, and second that it is a flash device.
Correct this problem by ensuring that the devices attached to the bus are of the correct flash type. This fixes a QEMU abort when devices without a CS line, such as the max111x, are passed on the command line.
While at it, export TYPE_M25P80 used in the Xilinx Versal Virtual machine.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2228 Fixes: 27a2c66c92ec ("aspeed/smc: Wire CS lines at reset") Reported-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> [ clg: minor fixes in the commit log ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
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06005459 |
| 26-Feb-2024 |
Sai Pavan Boddu <sai.pavan.boddu@amd.com> |
arm: xlnx-versal-virt: Add machine property ospi-flash
This property allows users to change flash model on command line as below.
ex: "-M xlnx-versal-virt,ospi-flash=mt35xu02gbba"
Signed-off-by
arm: xlnx-versal-virt: Add machine property ospi-flash
This property allows users to change flash model on command line as below.
ex: "-M xlnx-versal-virt,ospi-flash=mt35xu02gbba"
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Message-id: 20240220091721.82954-3-sai.pavan.boddu@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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9404dcde |
| 18-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/arm: Build various units only once
Various files in hw/arm/ don't require "cpu.h" anymore. Except virt-acpi-build.c, all of them don't require any ARM specific knowledge anymore and can be build
hw/arm: Build various units only once
Various files in hw/arm/ don't require "cpu.h" anymore. Except virt-acpi-build.c, all of them don't require any ARM specific knowledge anymore and can be build once as target agnostic units. Update meson accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-21-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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e2d8cf9b |
| 18-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
Declare arm_cpu_mp_affinity() prototype in the new "target/arm/multiprocessing.h" header so units in hw/arm/ can use it withou
target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
Declare arm_cpu_mp_affinity() prototype in the new "target/arm/multiprocessing.h" header so units in hw/arm/ can use it without having to include the huge target-specific "cpu.h".
File list to include the new header generated using:
$ git grep -lw arm_cpu_mp_affinity
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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c4380f7b |
| 18-Jan-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Create arm_cpu_mp_affinity
Wrapper to return the mp affinity bits from the cpu.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <ph
target/arm: Create arm_cpu_mp_affinity
Wrapper to return the mp affinity bits from the cpu.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d95a3a75 |
| 25-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson
hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a617e65f |
| 06-Jun-2023 |
Cédric Le Goater <clg@kaod.org> |
hw/ssi: Check for duplicate CS indexes
This to avoid indexes conflicts on the same SSI bus. Adapt machines using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Iglesias" <edgar.i
hw/ssi: Check for duplicate CS indexes
This to avoid indexes conflicts on the same SSI bus. Adapt machines using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Alistair Francis <alistair@alistair23.me> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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85c0f9e5 |
| 16-Aug-2023 |
Cédric Le Goater <clg@kaod.org> |
hw/ssi: Check for duplicate CS indexes
This to avoid indexes conflicts on the same SSI bus. Adapt machines using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Iglesias" <edgar.i
hw/ssi: Check for duplicate CS indexes
This to avoid indexes conflicts on the same SSI bus. Adapt machines using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Alistair Francis <alistair@alistair23.me> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-ID: <20230607043943.1837186-8-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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042d6b02 |
| 06-Jun-2023 |
Vikram Garhwal <vikram.garhwal@amd.com> |
xlnx-versal: Connect Xilinx VERSAL CANFD controllers
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt document with CANFD command line examples.
Signed-off-by: Vikra
xlnx-versal: Connect Xilinx VERSAL CANFD controllers
Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt document with CANFD command line examples.
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b3db996f |
| 20-Apr-2023 |
Stefan Weil <sw@weilnetz.de> |
hw/arm: Fix some typos in comments (most found by codespell)
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230409200526.1156456-1-
hw/arm: Fix some typos in comments (most found by codespell)
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230409200526.1156456-1-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.0.0 |
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#
69816564 |
| 13-Apr-2023 |
Cédric Le Goater <clg@kaod.org> |
hw/ssi: Check for duplicate addresses
This is a simple test to avoid address conflicts on the same SSI bus. Adapt machines using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Ig
hw/ssi: Check for duplicate addresses
This is a simple test to avoid address conflicts on the same SSI bus. Adapt machines using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Alistair Francis <alistair@alistair23.me> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v7.2.0 |
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d24a7bc2 |
| 27-Apr-2022 |
Alistair Francis <alistair.francis@wdc.com> |
hw/core: Move the ARM sysbus-fdt to core
The ARM virt machine currently uses sysbus-fdt to create device tree entries for dynamically created MMIO devices.
The RISC-V virt machine can also benefit
hw/core: Move the ARM sysbus-fdt to core
The ARM virt machine currently uses sysbus-fdt to create device tree entries for dynamically created MMIO devices.
The RISC-V virt machine can also benefit from this, so move the code to the core directory.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v7.0.0 |
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#
67a645a3 |
| 06-Apr-2022 |
Edgar E. Iglesias <edgar.iglesias@amd.com> |
hw/arm: versal: Add the Cortex-R5Fs
Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) subsystem.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Igl
hw/arm: versal: Add the Cortex-R5Fs
Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) subsystem.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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40874a38 |
| 30-Jan-2022 |
Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
hw/arm: versal-virt: Always call arm_load_kernel()
Always call arm_load_kernel() regardless of kernel_filename being set. This is needed because arm_load_kernel() sets up reset for the CPUs.
Fixes:
hw/arm: versal-virt: Always call arm_load_kernel()
Always call arm_load_kernel() regardless of kernel_filename being set. This is needed because arm_load_kernel() sets up reset for the CPUs.
Fixes: 6f16da53ff (hw/arm: versal: Add a virtual Xilinx Versal board) Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220130110313.4045351-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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9437a76e |
| 27-Jan-2022 |
Peter Maydell <peter.maydell@linaro.org> |
hw/arm/versal: Let boot.c handle PSCI enablement
Instead of setting the CPU psci-conduit and start-powered-off properties in the xlnx-versal-virt board code, set the arm_boot_info psci_conduit field
hw/arm/versal: Let boot.c handle PSCI enablement
Instead of setting the CPU psci-conduit and start-powered-off properties in the xlnx-versal-virt board code, set the arm_boot_info psci_conduit field so that the boot.c code can do it.
This will fix a corner case where we were incorrectly enabling PSCI emulation when booting guest code into EL3 because it was an ELF file passed to -kernel. (EL3 guest code started via -bios, -pflash, or the generic loader was already being run with PSCI emulation disabled.)
Note that EL3 guest code has no way to turn on the secondary CPUs because there's no emulated power controller, but this was already true for EL3 guest code run via -bios, -pflash, or the generic loader.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Cédric Le Goater <clg@kaod.org> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20220127154639.2090164-8-peter.maydell@linaro.org
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#
4461f0fb |
| 21-Jan-2022 |
Francisco Iglesias <francisco.iglesias@xilinx.com> |
hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory controller.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xil
hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory controller.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220121161141.14389-10-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
9a6d4918 |
| 21-Jan-2022 |
Francisco Iglesias <francisco.iglesias@xilinx.com> |
hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xili
hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-3-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v6.2.0 |
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#
c29faeda |
| 17-Nov-2021 |
Markus Armbruster <armbru@redhat.com> |
hw/arm/xlnx-versal-virt: Replace drive_get_next() by drive_get()
drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=
hw/arm/xlnx-versal-virt: Replace drive_get_next() by drive_get()
drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type.
This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review.
Machine "xlnx-versal-virt" connects backends with drive_get_next() in a counting loop. Change it to use drive_get() directly. This makes the unit numbers explicit in the code.
Cc: Alistair Francis <alistair@alistair23.me> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20211117163409.3587705-9-armbru@redhat.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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#
5f4910ff |
| 17-Sep-2021 |
Tong Ho <tong.ho@xilinx.com> |
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
Connect the support for Versal eFUSE one-time field-programmable bit array.
The command argument: -drive if=pflash,index=1,... Can be used to opt
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
Connect the support for Versal eFUSE one-time field-programmable bit array.
The command argument: -drive if=pflash,index=1,... Can be used to optionally connect the bit array to a backend storage, such that field-programmed values in one invocation can be made available to next invocation.
The backend storage must be a seekable binary file, and its size must be 3072 bytes or larger. A file with all binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
393185bc |
| 17-Sep-2021 |
Tong Ho <tong.ho@xilinx.com> |
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
Connect the support for Versal Battery-Backed RAM (BBRAM)
The command argument: -drive if=pflash,index=0,... Can be used to optionally connect th
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
Connect the support for Versal Battery-Backed RAM (BBRAM)
The command argument: -drive if=pflash,index=0,... Can be used to optionally connect the bbram to a backend storage, such that field-programmed values in one invocation can be made available to next invocation.
The backend storage must be a seekable binary file, and its size must be 36 bytes or larger. A file with all binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v6.1.0 |
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#
6c769690 |
| 21-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vsementsov/tags/pull-simplebench-2021-05-04' into staging scripts/simplebench improvements for 2021-05-04 # gpg: Signature made Tue 04 May 2021
Merge remote-tracking branch 'remotes/vsementsov/tags/pull-simplebench-2021-05-04' into staging scripts/simplebench improvements for 2021-05-04 # gpg: Signature made Tue 04 May 2021 09:45:15 BST # gpg: using RSA key 8B9C26CDB2FD147C880E86A1561F24C1F19F79FB # gpg: Good signature from "Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8B9C 26CD B2FD 147C 880E 86A1 561F 24C1 F19F 79FB * remotes/vsementsov/tags/pull-simplebench-2021-05-04: MAINTAINERS: update Benchmark util: add git tree simplebench/bench-backup: add --drop-caches argument simplebench/bench-backup: add --count and --no-initial-run simplebench/bench-backup: support qcow2 source files simplebench/bench_block_job: handle error in BLOCK_JOB_COMPLETED simplebench/bench-backup: add target-cache argument simplebench/bench-backup: add --compressed option simplebench: bench_one(): support count=1 simplebench: bench_one(): add slow_limit argument Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
6005ee07 |
| 16-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc,pci,virtio: bugfixes, improvements Fixes all over the place. Faster boot for virtio. ioeventfd support f
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging pc,pci,virtio: bugfixes, improvements Fixes all over the place. Faster boot for virtio. ioeventfd support for mmio. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 14 May 2021 15:27:13 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: Fix build with 64 bits time_t vhost-vdpa: Make vhost_vdpa_get_device_id() static hw/virtio: enable ioeventfd configuring for mmio hw/smbios: support for type 41 (onboard devices extended information) checkpatch: Fix use of uninitialized value virtio-scsi: Configure all host notifiers in a single MR transaction virtio-scsi: Set host notifiers and callbacks separately virtio-blk: Configure all host notifiers in a single MR transaction virtio-blk: Fix rollback path in virtio_blk_data_plane_start() pc-dimm: remove unnecessary get_vmstate_memory_region() method amd_iommu: fix wrong MMIO operations virtio-net: Constify VirtIOFeature feature_sizes[] virtio-blk: Constify VirtIOFeature feature_sizes[] hw/virtio: Pass virtio_feature_get_config_size() a const argument x86: acpi: use offset instead of pointer when using build_header() amd_iommu: Fix pte_override_page_mask() Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/virt.c
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#
499063d0 |
| 14-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-6.1-v1' into staging Add a bus multiplexer device This patch set adds a bus multiplexer and the necessary infrastructure
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-6.1-v1' into staging Add a bus multiplexer device This patch set adds a bus multiplexer and the necessary infrastructure in the I2C code to allow it to work. These are common on systems with lots of I2C devices, like an IPMI BMC. # gpg: Signature made Thu 13 May 2021 22:48:07 BST # gpg: using RSA key FD0D5CE67CE0F59A6688268661F38C90919BFF81 # gpg: Good signature from "Corey Minyard <cminyard@mvista.com>" [unknown] # gpg: aka "Corey Minyard <minyard@acm.org>" [unknown] # gpg: aka "Corey Minyard <corey@minyard.net>" [unknown] # gpg: aka "Corey Minyard <minyard@mvista.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FD0D 5CE6 7CE0 F59A 6688 2686 61F3 8C90 919B FF81 * remotes/cminyard/tags/for-qemu-6.1-v1: hw/i2c: add pca954x i2c-mux switch hw/i2c: move search to i2c_scan_bus method hw/i2c: add match method for device search hw/i2c: name I2CNode list in I2CBus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
e4f3ede9 |
| 10-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210505-pull-request' into staging usb: fix some memory allocation issues (CVE-2021-3527). usb: add stubs, allow building without u
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210505-pull-request' into staging usb: fix some memory allocation issues (CVE-2021-3527). usb: add stubs, allow building without usb subsystem. # gpg: Signature made Wed 05 May 2021 14:07:02 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20210505-pull-request: usb: limit combined packets to 1 MiB (CVE-2021-3527) usb/mtp: avoid dynamic stack allocation usb/redir: avoid dynamic stack allocation (CVE-2021-3527) usb/hid: avoid dynamic stack allocation hw/usb: Do not build USB subsystem if not required hw/usb/host-stub: Remove unused header Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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74e31681 |
| 10-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210505' into staging qemu-sparc queue # gpg: Signature made Wed 05 May 2021 08:29:13 BST # gpg: u
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210505' into staging qemu-sparc queue # gpg: Signature made Wed 05 May 2021 08:29:13 BST # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20210505: hw/sparc*: Move cpu_check_irqs() to target/sparc/ hw/sparc64: Fix code style for checkpatch.pl hw/sparc64: Remove unused "hw/char/serial.h" header hw/sparc: Allow building without the leon3 machine hw/sparc/sun4m: Move each sun4m_hwdef definition in its class_init hw/sparc/sun4m: Fix code style for checkpatch.pl hw/sparc/sun4m: Register machine types in sun4m_machine_types[] hw/sparc/sun4m: Factor out sun4m_machine_class_init() hw/sparc/sun4m: Introduce Sun4mMachineClass hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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