| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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| /openbmc/linux/include/linux/ |
| H A D | etherdevice.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Definitions for the Ethernet handlers.
69 /* Reserved Ethernet Addresses per IEEE 802.1Q */
75 * is_link_local_ether_addr - Determine if given Ethernet address is link-local
76 * @addr: Pointer to a six-byte array containing the Ethernet address
98 * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
99 * @addr: Pointer to a six-byte array containing the Ethernet address
117 * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
118 * @addr: Pointer to a six-byte array containing the Ethernet address
131 return 0x01 & (a >> ((sizeof(a) * 8) - 8)); in is_multicast_ether_addr()
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| H A D | crc32.h | 15 * crc32_le_combine - Combine two crc32 check values into one. For two
42 * __crc32c_le_combine - Combine two crc32c check values into one. For two
69 * Helpers for hash table generation of ethernet nics:
71 * Ethernet sends the least significant bit of a byte first, thus crc32_le
|
| /openbmc/linux/net/l2tp/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Layer Two Tunneling Protocol (L2TP)
7 tristate "Layer Two Tunneling Protocol (L2TP)"
12 Layer Two Tunneling Protocol
18 possible to both end-users and applications.
54 Layer Two Tunneling Protocol Version 3
58 The Layer Two Tunneling Protocol (L2TP) provides a dynamic
60 packet-oriented data network (e.g., over IP). L2TP, as
62 tunneling Point-to-Point Protocol (PPP) [RFC1661] sessions.
65 ethernet frames.
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| /openbmc/u-boot/board/freescale/t1040qds/ |
| H A D | README | 2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
21 - Packet parsing, classification, and distribution
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| /openbmc/linux/drivers/usb/gadget/legacy/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
23 # Gadget drivers are hardware-neutral, or "platform independent",
44 Gadget Zero is a two-configuration device. It either sinks and
47 conformance. The driver needs only two bulk-capable endpoints, so
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| /openbmc/u-boot/board/freescale/t208xrdb/ |
| H A D | README | 1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
2 It can work in two mode: standalone mode and PCIe endpoint mode.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | Kconfig | 3 bool "Bit-banged ethernet MII management channel support"
9 bool "Ethernet PHY (physical media interface) support"
12 Enable Ethernet PHY (physical media interface) support.
32 bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
34 Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
49 bool "Marvel MV88E61xx Ethernet switch PHY support."
68 bool "Aquantia Ethernet PHYs support"
95 bool "Atheros Ethernet PHYs support"
98 bool "Broadcom Ethernet PHYs support"
101 bool "Cortina Ethernet PHYs support"
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| /openbmc/u-boot/board/freescale/t104xrdb/ |
| H A D | README | 2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
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| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | Kconfig | 11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
44 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
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| /openbmc/linux/net/hsr/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # IEC 62439-3 High-availability Seamless Redundancy
7 tristate "High-availability Seamless Redundancy (HSR & PRP)"
9 This enables IEC 62439 defined High-availability Seamless
15 needs (at least) two physical Ethernet interfaces.
18 with other HSR capable nodes. All Ethernet frames sent over the HSR
20 ports), giving a redundant, instant fail-over network. Each HSR node
24 For DANP, it must be connected as a node connecting to two
25 separate networks over the two slave interfaces. Like HSR, Ethernet
27 a redundant, instant fail-over network. Unlike HSR, PRP networks
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| /openbmc/linux/Documentation/infiniband/ |
| H A D | opa_vnic.rst | 2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
7 the Ethernet packets between HFI nodes.
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
14 permitted to exchange encapsulated Ethernet packets across a particular
15 virtual Ethernet switch. The virtual Ethernet switches are logical
18 nodes across the fabric exchange encapsulated Ethernet packets over a
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| /openbmc/u-boot/board/freescale/t102xrdb/ |
| H A D | README | 2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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| /openbmc/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
|
| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
|
| /openbmc/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
|
| /openbmc/linux/Documentation/networking/dsa/ |
| H A D | lan9303.rst | 2 LAN9303 Ethernet switch driver
5 The LAN9303 is a three port 10/100 Mbps ethernet switch with integrated phys for
6 the two external ethernet ports. The third port is an RMII/MII interface to a
20 At startup the driver configures the device to provide two separate network
36 - Support for VLAN filtering is not implemented
37 - The HW does not support VLAN-specific fdb entries
|
| /openbmc/u-boot/board/freescale/ls1021aiot/ |
| H A D | README | 2 --------
3 The LS1021A-IOT is a Freescale reference board that hosts
7 -------------------------
8 - DDR Controller
9 - Supports 1GB un-buffered DDR3L SDRAM discrete
10 devices(32-bit bus) with 4 bit ECC
11 - DDR power supplies 1.35V to all devices with
13 - Soldered DDR chip
14 - Supprot one fixed speed
15 - Ethernet
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| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | README | 2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | dsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Switch
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 This binding represents Ethernet Switches which have a dedicated CPU
16 port. That port is usually connected to an Ethernet Controller of the
21 $ref: /schemas/net/ethernet-switch.yaml#
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| /openbmc/linux/drivers/net/usb/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 comment "Host-side USB support is needed for USB Network Adapter support"
16 tristate "USB CATC NetMate-based Ethernet device support"
19 Say Y if you want to use one of the following 10Mbps USB Ethernet
27 This driver makes the adapter appear as a normal Ethernet interface,
28 typically on eth0, if it is the only ethernet device, or perhaps on
29 eth1, if you have a PCI or ISA ethernet card installed.
35 tristate "USB KLSI KL5USB101-based ethernet device support"
38 USB Ethernet adapters based on the KLSI KL5KUSB101B chipset:
40 ADS USB-10BT
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | adi,adin1110.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
14 PHY designed for industrial Ethernet applications. It integrates
15 an Ethernet PHY core with a MAC and all the associated analog
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
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| H A D | marvell-orion-net.txt | 1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
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| /openbmc/u-boot/drivers/net/ |
| H A D | Kconfig | 5 bool "Enable Driver Model for Ethernet drivers"
8 Enable driver model for Ethernet.
11 This is currently implemented in net/eth-uclass.c
34 bool "Atheros AG7xxx Ethernet MAC support"
38 This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is
43 bool "Altera Triple-Speed Ethernet MAC support"
47 This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
48 Please find details on the "Triple-Speed Ethernet MegaCore Function
52 bool "Broadcom SF2 (Starfighter2) Ethernet support"
60 int "Broadcom SF2 (Starfighter2) Ethernet default port number"
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | armada3700-periph-clock.txt | 6 There are two different blocks associated to north bridge and south
14 -----------------------------------
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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