1aba80048SShengzhou LiuT1024 SoC Overview 2aba80048SShengzhou Liu------------------ 3aba80048SShengzhou LiuThe T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor 4aba80048SShengzhou Liucombines two or one 64-bit Power Architecture e5500 core respectively with high 5aba80048SShengzhou Liuperformance datapath acceleration logic, and network peripheral bus interfaces 6aba80048SShengzhou Liurequired for networking and telecommunications. This processor can be used in 7aba80048SShengzhou Liuapplications such as enterprise WLAN access points, routers, switches, firewall 8aba80048SShengzhou Liuand other packet processing intensive small enterprise and branch office appliances, 9aba80048SShengzhou Liuand general-purpose embedded computing. Its high level of integration offers 10aba80048SShengzhou Liusignificant performance benefits and greatly helps to simplify board design. 11aba80048SShengzhou Liu 12aba80048SShengzhou Liu 13aba80048SShengzhou LiuThe T1024 SoC includes the following function and features: 14aba80048SShengzhou Liu- two e5500 cores, each with a private 256 KB L2 cache 15aba80048SShengzhou Liu - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) 16aba80048SShengzhou Liu - Three levels of instructions: User, supervisor, and hypervisor 17aba80048SShengzhou Liu - Independent boot and reset 18aba80048SShengzhou Liu - Secure boot capability 19aba80048SShengzhou Liu- 256 KB shared L3 CoreNet platform cache (CPC) 20aba80048SShengzhou Liu- Interconnect CoreNet platform 21aba80048SShengzhou Liu - CoreNet coherency manager supporting coherent and noncoherent transactions 22aba80048SShengzhou Liu with prioritization and bandwidth allocation amongst CoreNet endpoints 23aba80048SShengzhou Liu - 150 Gbps coherent read bandwidth 24aba80048SShengzhou Liu- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support 25aba80048SShengzhou Liu- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: 26aba80048SShengzhou Liu - Packet parsing, classification, and distribution 27aba80048SShengzhou Liu - Queue management for scheduling, packet sequencing, and congestion management 28aba80048SShengzhou Liu - Cryptography Acceleration (SEC 5.x) 29aba80048SShengzhou Liu - IEEE 1588 support 30aba80048SShengzhou Liu - Hardware buffer management for buffer allocation and deallocation 31aba80048SShengzhou Liu - MACSEC on DPAA-based Ethernet ports 32aba80048SShengzhou Liu- Ethernet interfaces 33aba80048SShengzhou Liu - Four 1 Gbps Ethernet controllers 34aba80048SShengzhou Liu- Parallel Ethernet interfaces 35aba80048SShengzhou Liu - Two RGMII interfaces 36aba80048SShengzhou Liu- High speed peripheral interfaces 37aba80048SShengzhou Liu - Three PCI Express 2.0 controllers/ports running at up to 5 GHz 38aba80048SShengzhou Liu - One SATA controller supporting 1.5 and 3.0 Gb/s operation 39aba80048SShengzhou Liu - One QSGMII interface 40aba80048SShengzhou Liu - Four SGMII interface supporting 1000 Mbps 41aba80048SShengzhou Liu - Three SGMII interfaces supporting up to 2500 Mbps 42aba80048SShengzhou Liu - 10GbE XFI or 10Base-KR interface 43aba80048SShengzhou Liu- Additional peripheral interfaces 44aba80048SShengzhou Liu - Two USB 2.0 controllers with integrated PHY 45aba80048SShengzhou Liu - SD/eSDHC/eMMC 46aba80048SShengzhou Liu - eSPI controller 47aba80048SShengzhou Liu - Four I2C controllers 48aba80048SShengzhou Liu - Four UARTs 49aba80048SShengzhou Liu - Four GPIO controllers 50aba80048SShengzhou Liu - Integrated flash controller (IFC) 51aba80048SShengzhou Liu - LCD interface (DIU) with 12 bit dual data rate 52aba80048SShengzhou Liu- Multicore programmable interrupt controller (PIC) 53aba80048SShengzhou Liu- Two 8-channel DMA engines 54aba80048SShengzhou Liu- Single source clocking implementation 55aba80048SShengzhou Liu- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) 56aba80048SShengzhou Liu- QUICC Engine block 57aba80048SShengzhou Liu - 32-bit RISC controller for flexible support of the communications peripherals 58aba80048SShengzhou Liu - Serial DMA channel for receive and transmit on all serial channels 59aba80048SShengzhou Liu - Two universal communication controllers, supporting TDM, HDLC, and UART 60aba80048SShengzhou Liu 61aba80048SShengzhou LiuT1023 Personality 62aba80048SShengzhou Liu------------------ 63aba80048SShengzhou LiuT1023 is a reduced personality of T1024 without QUICC Engine, DIU, and 64aba80048SShengzhou Liuunavailable deep sleep. Rest of the blocks are almost same as T1024. 65aba80048SShengzhou LiuDifferences between T1024 and T1023 66aba80048SShengzhou LiuFeature T1024 T1023 67aba80048SShengzhou LiuQUICC Engine: yes no 68aba80048SShengzhou LiuDIU: yes no 69aba80048SShengzhou LiuDeep Sleep: yes no 70aba80048SShengzhou LiuI2C controller: 4 3 71aba80048SShengzhou LiuDDR: 64-bit 32-bit 72aba80048SShengzhou LiuIFC: 32-bit 28-bit 73aba80048SShengzhou Liu 74aba80048SShengzhou Liu 75aba80048SShengzhou LiuT1024QDS board Overview 76aba80048SShengzhou Liu----------------------- 77aba80048SShengzhou Liu- SERDES Connections 78aba80048SShengzhou Liu 4 lanes supporting the following: 79aba80048SShengzhou Liu - PCI Express: supports Gen 1 and Gen 2 80aba80048SShengzhou Liu - SGMII 1G and SGMII 2.5G 81aba80048SShengzhou Liu - QSGMII 82aba80048SShengzhou Liu - XFI 83aba80048SShengzhou Liu - SATA 2.0 84aba80048SShengzhou Liu - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors. 85aba80048SShengzhou Liu - Aurora debug with dedicated connectors. 86aba80048SShengzhou Liu- DDR Controller 87aba80048SShengzhou Liu - Supports up to 1600 MTPS data-rate. 88aba80048SShengzhou Liu - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card. 89aba80048SShengzhou Liu - Supports Single-, dual- or quad-rank DIMMs 90aba80048SShengzhou Liu - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT. 91aba80048SShengzhou Liu- IFC/Local Bus 92aba80048SShengzhou Liu - NAND Flash: 8-bit, async, up to 2GB 93aba80048SShengzhou Liu - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB 94aba80048SShengzhou Liu - NOR devices support 8 virtual banks 95aba80048SShengzhou Liu - Socketed to allow alternate devices 96aba80048SShengzhou Liu - GASIC: Simple (minimal) target within QIXIS FPGA 97aba80048SShengzhou Liu - PromJET rapid memory download support 98aba80048SShengzhou Liu - IFC Debug/Development card 99aba80048SShengzhou Liu- Ethernet 100aba80048SShengzhou Liu - Two on-board RGMII 10M/100M/1G ethernet ports. 101aba80048SShengzhou Liu - One QSGMII interface 102aba80048SShengzhou Liu - Four SGMII interface supporting 1Gbps 103aba80048SShengzhou Liu - Three SGMII interfaces supporting 2.5Gbps 104aba80048SShengzhou Liu - one 10Gbps XFI or 10Base-KR interface 105aba80048SShengzhou Liu- QIXIS System Logic FPGA 106aba80048SShengzhou Liu - Manages system power and reset sequencing. 107aba80048SShengzhou Liu - Manages the configurations of DUT, board, and clock for dynamic shmoo. 108aba80048SShengzhou Liu - Collects V-I-T data in background for code/power profiling. 109aba80048SShengzhou Liu - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion). 110aba80048SShengzhou Liu - General fault monitoring and logging. 111aba80048SShengzhou Liu - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off. 112aba80048SShengzhou Liu- Clocks 113aba80048SShengzhou Liu - System and DDR clock (SYSCLK, DDRCLK). 114aba80048SShengzhou Liu - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz. 115aba80048SShengzhou Liu - Software programmable in 1 MHz increments from 1-200 MHz. 116aba80048SShengzhou Liu - SERDES clocks 117aba80048SShengzhou Liu - Provides clocks to SerDes blocks and slots. 118aba80048SShengzhou Liu - 100 MHz, 125 MHz and 156.25 MHz options. 119aba80048SShengzhou Liu - Spread-spectrum option for 100 MHz. 120aba80048SShengzhou Liu- Power Supplies 121aba80048SShengzhou Liu - Dedicated PMBus regulator for VDD and VDDC. 122aba80048SShengzhou Liu - Adjustable from 0.7V to 1.3V at 35A 123aba80048SShengzhou Liu - VDD can be disabled independanty from VDDC for “deep sleep”. 124aba80048SShengzhou Liu - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A. 125aba80048SShengzhou Liu - VTT/MVREF automatically track operating voltage. 126aba80048SShengzhou Liu - Dedicated 2.5V VPP supply. 127aba80048SShengzhou Liu - Dedicated regulators/filters for AVDD supplies. 128aba80048SShengzhou Liu - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD. 129aba80048SShengzhou Liu- Video 130aba80048SShengzhou Liu - DIU supports video up to 1280x1024x32 bpp. 131aba80048SShengzhou Liu - Chrontel CH7201 for HDMI connection. 132aba80048SShengzhou Liu - TI DS90C387R for direct LCD connection. 133aba80048SShengzhou Liu - Raw (not encoded) video connector for testing or other encoders. 134aba80048SShengzhou Liu- USB 135aba80048SShengzhou Liu - Supports two USB 2.0 ports with integrated PHYs. 136aba80048SShengzhou Liu - Two type A ports with 5V@1.5A per port. 137aba80048SShengzhou Liu - Second port can be converted to OTG mini-AB. 138aba80048SShengzhou Liu- SDHC 139aba80048SShengzhou Liu For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features: 140aba80048SShengzhou Liu - upport for optional clock feedback paths. 141aba80048SShengzhou Liu - Support for optional high-speed voltage translation direction controls. 142aba80048SShengzhou Liu - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC. 143aba80048SShengzhou Liu - Support for eMMC memory devices. 144aba80048SShengzhou Liu- SPI 145aba80048SShengzhou Liu -On-board support of 3 different devices and sizes. 146aba80048SShengzhou Liu- Other IO 147aba80048SShengzhou Liu - Two Serial ports 148aba80048SShengzhou Liu - ProfiBus port 149aba80048SShengzhou Liu - Four I2C ports 150aba80048SShengzhou Liu 151aba80048SShengzhou Liu 152aba80048SShengzhou LiuMemory map on T1024QDS 153aba80048SShengzhou Liu---------------------- 154aba80048SShengzhou LiuStart Address End Address Description Size 155aba80048SShengzhou Liu0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB 156aba80048SShengzhou Liu0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB 157aba80048SShengzhou Liu0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB 158aba80048SShengzhou Liu0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB 159aba80048SShengzhou Liu0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB 160aba80048SShengzhou Liu0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB 161aba80048SShengzhou Liu0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB 162aba80048SShengzhou Liu0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB 163aba80048SShengzhou Liu0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB 164aba80048SShengzhou Liu0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB 165aba80048SShengzhou Liu0xF_0000_0000 0xF_003F_FFFF DCSR 4MB 166aba80048SShengzhou Liu0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB 167aba80048SShengzhou Liu0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB 168aba80048SShengzhou Liu0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB 169aba80048SShengzhou Liu0x0_0000_0000 0x0_ffff_ffff DDR 4GB 170aba80048SShengzhou Liu 171aba80048SShengzhou Liu 172aba80048SShengzhou Liu128MB NOR Flash memory Map 173aba80048SShengzhou Liu-------------------------- 174aba80048SShengzhou LiuStart Address End Address Definition Max size 175*a187559eSBin Meng0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB 176*a187559eSBin Meng0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB 177aba80048SShengzhou Liu0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 178aba80048SShengzhou Liu0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB 179aba80048SShengzhou Liu0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB 180aba80048SShengzhou Liu0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB 181aba80048SShengzhou Liu0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 182aba80048SShengzhou Liu0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 183*a187559eSBin Meng0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB 184*a187559eSBin Meng0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB 185aba80048SShengzhou Liu0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 186aba80048SShengzhou Liu0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB 187aba80048SShengzhou Liu0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB 188aba80048SShengzhou Liu0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB 189aba80048SShengzhou Liu0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 190aba80048SShengzhou Liu0xE8000000 0xE801FFFF RCW (current bank) 128KB 191aba80048SShengzhou Liu 192aba80048SShengzhou Liu 193aba80048SShengzhou LiuSerDes clock vs DIP-switch settings 194aba80048SShengzhou Liu----------------------------------- 195aba80048SShengzhou LiuSRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4] 196aba80048SShengzhou Liu0x6F 100MHz 125MHz 1101 197aba80048SShengzhou Liu0xD6 100MHz 100MHz 1111 198aba80048SShengzhou Liu0x99 156.25MHz 100MHz 1011 199aba80048SShengzhou Liu 200aba80048SShengzhou Liu 201aba80048SShengzhou LiuT1024 Clock frequency 202aba80048SShengzhou Liu---------------------- 203aba80048SShengzhou LiuBIN Core DDR Platform FMan 204aba80048SShengzhou LiuBin1: 1400MHz 1600MT/s 400MHz 700MHz 205aba80048SShengzhou LiuBin2: 1200MHz 1600MT/s 400MHz 600MHz 206aba80048SShengzhou LiuBin3: 1000MHz 1600MT/s 400MHz 500MHz 207aba80048SShengzhou Liu 208aba80048SShengzhou Liu 209aba80048SShengzhou Liu 210aba80048SShengzhou LiuSoftware configurations and board settings 211aba80048SShengzhou Liu------------------------------------------ 212aba80048SShengzhou Liu1. NOR boot: 213aba80048SShengzhou Liu a. build NOR boot image 214aba80048SShengzhou Liu $ make T1024QDS_defconfig (For DDR3L, by default) 215aba80048SShengzhou Liu or make T1024QDS_D4_defconfig (For DDR4) 216aba80048SShengzhou Liu $ make 217aba80048SShengzhou Liu b. program u-boot.bin image to NOR flash 218aba80048SShengzhou Liu => tftp 1000000 u-boot.bin 219aba80048SShengzhou Liu => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize 220aba80048SShengzhou Liu set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot 221aba80048SShengzhou Liu 222aba80048SShengzhou Liu Switching between default bank0 and alternate bank4 on NOR flash 223aba80048SShengzhou Liu To change boot source to vbank4: 224*a187559eSBin Meng via software: run command 'qixis_reset altbank' in U-Boot. 225aba80048SShengzhou Liu via DIP-switch: set SW6[1:4] = '0100' 226aba80048SShengzhou Liu 227aba80048SShengzhou Liu To change boot source to vbank0: 228*a187559eSBin Meng via software: run command 'qixis_reset' in U-Boot. 229aba80048SShengzhou Liu via DIP-Switch: set SW6[1:4] = '0000' 230aba80048SShengzhou Liu 231aba80048SShengzhou Liu2. NAND Boot: 232aba80048SShengzhou Liu a. build PBL image for NAND boot 233aba80048SShengzhou Liu $ make T1024QDS_NAND_defconfig 234aba80048SShengzhou Liu $ make 235aba80048SShengzhou Liu b. program u-boot-with-spl-pbl.bin to NAND flash 236aba80048SShengzhou Liu => tftp 1000000 u-boot-with-spl-pbl.bin 237aba80048SShengzhou Liu => nand erase 0 $filesize 238aba80048SShengzhou Liu => nand write 1000000 0 $filesize 239aba80048SShengzhou Liu set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot 240aba80048SShengzhou Liu 241aba80048SShengzhou Liu3. SPI Boot: 242aba80048SShengzhou Liu a. build PBL image for SPI boot 243aba80048SShengzhou Liu $ make T1024QDS_SPIFLASH_defconfig 244aba80048SShengzhou Liu $ make 245aba80048SShengzhou Liu b. program u-boot-with-spl-pbl.bin to SPI flash 246aba80048SShengzhou Liu => tftp 1000000 u-boot-with-spl-pbl.bin 247aba80048SShengzhou Liu => sf probe 0 248aba80048SShengzhou Liu => sf erase 0 f0000 249aba80048SShengzhou Liu => sf write 1000000 0 $filesize 250aba80048SShengzhou Liu set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 251aba80048SShengzhou Liu 252aba80048SShengzhou Liu4. SD Boot: 253aba80048SShengzhou Liu a. build PBL image for SD boot 254aba80048SShengzhou Liu $ make T1024QDS_SDCARD_defconfig 255aba80048SShengzhou Liu $ make 256aba80048SShengzhou Liu b. program u-boot-with-spl-pbl.bin to SD/MMC card 257aba80048SShengzhou Liu => tftp 1000000 u-boot-with-spl-pbl.bin 258aba80048SShengzhou Liu => mmc write 1000000 8 0x800 259aba80048SShengzhou Liu => tftp 1000000 fsl_fman_ucode_t1024_xx.bin 260aba80048SShengzhou Liu => mmc write 1000000 0x820 80 261aba80048SShengzhou Liu set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot 262aba80048SShengzhou Liu 263aba80048SShengzhou Liu 264aba80048SShengzhou LiuDIU/QE-TDM/SDXC settings 265aba80048SShengzhou Liu------------------- 266aba80048SShengzhou Liua) For TDM Riser: set pin_mux=tdm in hwconfig 267aba80048SShengzhou Liub) For UCC(ProfiBus): set pin_mux=ucc in hwconfig 268aba80048SShengzhou Liuc) For HDMI(DVI): set pin_mux=hdmi in hwconfig 269aba80048SShengzhou Liud) For LCD(DFP): set pin_mux=lcd in hwconfig 270aba80048SShengzhou Liue) For SDXC: set adaptor=sdxc in hwconfig 271aba80048SShengzhou Liu 272aba80048SShengzhou Liu2-stage NAND/SPI/SD boot loader 273aba80048SShengzhou Liu------------------------------- 274aba80048SShengzhou LiuPBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. 275aba80048SShengzhou LiuSPL further initializes DDR using SPD and environment variables 276*a187559eSBin Mengand copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. 277*a187559eSBin MengFinally SPL transers control to U-Boot for futher booting. 278aba80048SShengzhou Liu 279aba80048SShengzhou LiuSPL has following features: 280aba80048SShengzhou Liu - Executes within 256K 281aba80048SShengzhou Liu - No relocation required 282aba80048SShengzhou Liu 283aba80048SShengzhou LiuRun time view of SPL framework 284aba80048SShengzhou Liu------------------------------------------------- 285aba80048SShengzhou Liu|Area | Address | 286aba80048SShengzhou Liu------------------------------------------------- 287aba80048SShengzhou Liu|SecureBoot header | 0xFFFC0000 (32KB) | 288aba80048SShengzhou Liu------------------------------------------------- 289aba80048SShengzhou Liu|GD, BD | 0xFFFC8000 (4KB) | 290aba80048SShengzhou Liu------------------------------------------------- 291aba80048SShengzhou Liu|ENV | 0xFFFC9000 (8KB) | 292aba80048SShengzhou Liu------------------------------------------------- 293aba80048SShengzhou Liu|HEAP | 0xFFFCB000 (30KB) | 294aba80048SShengzhou Liu------------------------------------------------- 295aba80048SShengzhou Liu|STACK | 0xFFFD8000 (22KB) | 296aba80048SShengzhou Liu------------------------------------------------- 297*a187559eSBin Meng|U-Boot SPL | 0xFFFD8000 (160KB) | 298aba80048SShengzhou Liu------------------------------------------------- 299aba80048SShengzhou Liu 300aba80048SShengzhou LiuNAND Flash memory Map on T1024QDS 301aba80048SShengzhou Liu------------------------------------------------------------- 302aba80048SShengzhou LiuStart End Definition Size 303*a187559eSBin Meng0x000000 0x0FFFFF U-Boot 1MB 304*a187559eSBin Meng0x100000 0x15FFFF U-Boot env 8KB 305aba80048SShengzhou Liu0x160000 0x17FFFF FMAN Ucode 128KB 306aba80048SShengzhou Liu0x180000 0x19FFFF QE Firmware 128KB 307aba80048SShengzhou Liu 308aba80048SShengzhou Liu 309aba80048SShengzhou LiuSD Card memory Map on T1024QDS 310aba80048SShengzhou Liu---------------------------------------------------- 311aba80048SShengzhou LiuBlock #blocks Definition Size 312*a187559eSBin Meng0x008 2048 U-Boot img 1MB 313*a187559eSBin Meng0x800 0016 U-Boot env 8KB 314aba80048SShengzhou Liu0x820 0256 FMAN Ucode 128KB 315aba80048SShengzhou Liu0x920 0256 QE Firmware 128KB 316aba80048SShengzhou Liu 317aba80048SShengzhou Liu 318aba80048SShengzhou LiuSPI Flash memory Map on T1024QDS 319aba80048SShengzhou Liu---------------------------------------------------- 320aba80048SShengzhou LiuStart End Definition Size 321*a187559eSBin Meng0x000000 0x0FFFFF U-Boot img 1MB 322*a187559eSBin Meng0x100000 0x101FFF U-Boot env 8KB 323aba80048SShengzhou Liu0x110000 0x12FFFF FMAN Ucode 128KB 324aba80048SShengzhou Liu0x130000 0x14FFFF QE Firmware 128KB 325aba80048SShengzhou Liu 326aba80048SShengzhou Liu 327aba80048SShengzhou LiuFor more details, please refer to T1024QDS Reference Manual and access 328aba80048SShengzhou Liuwebsite www.freescale.com and Freescale QorIQ SDK Infocenter document. 329