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/openbmc/u-boot/include/
H A Dfsl_dtsec.h21 u32 tctrl; /* Transmit control register */
45 /* transmit and receive counter */
71 /* transmit counters */
72 u32 tbyt; /* Transmit byte counter */
73 u32 tpkt; /* Transmit packet */
74 u32 tmca; /* Transmit multicast packet */
75 u32 tbca; /* Transmit broadcast packet */
76 u32 txpf; /* Transmit pause control frame */
77 u32 tdfr; /* Transmit deferral packet */
78 u32 tedf; /* Transmit excessive deferral pkt */
[all …]
H A Dtsec.h215 /* Transmit and Receive Counters */
241 /* Transmit Counters */
242 u32 tbyt; /* Transmit Byte Counter */
243 u32 tpkt; /* Transmit Packet */
244 u32 tmca; /* Transmit Multicast Packet */
245 u32 tbca; /* Transmit Broadcast Packet */
246 u32 txpf; /* Transmit Pause Control Frame */
247 u32 tdfr; /* Transmit Deferral Packet */
248 u32 tedf; /* Transmit Excessive Deferral Packet */
249 u32 tscl; /* Transmit Single Collision Packet */
[all …]
/openbmc/qemu/include/hw/net/
H A Dnpcm_gmac.h148 /* Transmit End of Ring */
152 /* Transmit Buffer 2 Size */
154 /* Transmit Buffer 1 Size */
178 /* Transmit Process State */
180 /* Transmit States */
193 /* Transmit Process State */
214 /* Early transmit Interrupt */
224 /* Transmit Underflow */
228 /* Transmit Jabber Timeout */
230 /* Transmit Buffer Unavailable */
[all …]
H A Dnpcm7xx_emc.h107 /* Enable Transmit Descriptor Unavailable Interrupt */
109 /* Enable Transmit Completion Interrupt */
111 /* Enable Transmit Interrupt */
122 /* Transmit Bus Error Interrupt */
124 /* Transmit Descriptor Unavailable Interrupt */
126 /* Transmit Completion Interrupt */
128 /* Transmit Interrupt */
159 /* Transmit and receive descriptors */
180 /* Transmit interrupt enable */
209 /* Transmit interrupt */
[all …]
H A Dallwinner-sun8i-emac.h91 uint32_t tx_ctl0; /**< Transmit Control 0 */
92 uint32_t tx_ctl1; /**< Transmit Control 1 */
93 uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
94 uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
95 uint32_t tx_flowctl; /**< Transmit Flow Control */
/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c42 {0x08C, "FIFO_TX_THR", "FIFO transmit threshold register", ACC_RW, 0x00000…
43 {0x098, "FIFO_TX_STARVE", "FIFO transmit starve register", ACC_RW, 0x00000…
44 {0x09C, "FIFO_TX_STARVE_SHUTOFF", "FIFO transmit starve shut-off register", ACC_RW, 0x00000…
46 /* eTSEC Transmit Control and Status Registers */
48 {0x100, "TCTRL", "Transmit control register", ACC_RW, 0x00000000},
49 {0x104, "TSTAT", "Transmit status register", ACC_W1C, 0x00000000},
51 {0x110, "TXIC", "Transmit interrupt coalescing register", ACC_RW, 0x00000000},
52 {0x114, "TQUEUE", "Transmit queue control register", ACC_RW, 0x00008000},
159 /* eTSEC, "Transmit", "and", Receive, Counters */
161 {0x680, "TR64", "Transmit and receive 64-byte frame counter ", ACC_RW, 0x0000000…
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pdc.h12 u32 tpr; /* 0x108 Transmit Pointer Register */
13 u32 tcr; /* 0x10C Transmit Counter Register */
16 u32 tnpr; /* 0x118 Transmit Next Pointer Register */
17 u32 tncr; /* 0x11C Transmit Next Counter Register */
H A Dat91_spi.h21 u32 tdr; /* 0x0C Transmit Data Register */
56 #define AT91_SPI_TDR 0x0c /* Transmit Data Register */
57 #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
63 #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
100 #define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
102 #define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
108 #define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
110 #define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
/openbmc/u-boot/include/linux/
H A Dimmap_qe.h185 u32 spitd; /* SPI transmit data register (cpu mode) */
281 u16 utodr; /* UCCx transmit on demand register */
383 u16 utodr; /* UCCx transmit on demand register */
397 u32 utfb; /* UCC transmit FIFO base */
398 u16 utfs; /* UCC transmit FIFO size */
400 u16 utfet; /* UCC transmit FIFO emergency threshold */
402 u16 utftt; /* UCC transmit FIFO transmit threshold */
404 u16 utpt; /* UCC transmit polling timer */
461 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
462 u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
[all …]
/openbmc/qemu/hw/net/
H A Dallwinner-sun8i-emac.c42 REG_TX_CTL_0 = 0x0010, /* Transmit Control 0 */
43 REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
44 REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
45 REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
56 REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
57 REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
58 REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
157 /* Transmit/receive frame descriptor */
171 /* Transmit frame descriptor flags */
519 /* Read all transmit descriptors */ in allwinner_sun8i_emac_transmit()
[all …]
H A Dxgmac.c53 #define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */
71 #define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */
74 #define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */
95 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
103 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
108 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
110 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
111 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
112 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
113 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcpm_85xx.h113 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
333 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
374 /* Buffer descriptor control/status used by Ethernet transmit.
409 ushort scc_toseq; /* Transmit out of sequence char */
508 uint fcc_tbase; /* Transmit BD base */
587 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
675 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
678 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
681 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
692 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
[all …]
H A Dimmap_86xx.h297 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
299 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
300 uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
305 uint tctrl; /* 0x24100 - Transmit Control Register */
306 uint tstat; /* 0x24104 - Transmit Status Register */
309 uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
310 uint tqueue; /* 0x24114 - Transmit Queue Control Register */
315 uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
317 uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
319 uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
[all …]
/openbmc/u-boot/drivers/net/
H A D8390.h25 #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
31 #define E8390_TRANS 0x04 /* Transmit a frame */
56 #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
57 #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
114 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
115 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
116 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
118 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
H A Dep93xx_eth.h57 * Transmit descriptor queue entry
67 * Transmit status queue entry
77 * Transmit descriptor queue
86 * Transmit status queue
H A Dbcm-sf2-eth-gmac.h59 /* transmit channel control */
60 /* transmit enable */
62 /* transmit suspend request */
70 /* transmit descriptor table pointer */
74 /* transmit channel status */
75 /* transmit state */
H A Dcs8900.h99 #define PP_TxCFG 0x0106 /* Transmit configuration */
108 #define PP_TxCmd 0x0108 /* Transmit command status */
179 #define PP_TER 0x0128 /* Transmit event */
184 #define PP_TER_Jabber 0x0400 /* Stuck transmit? */
192 #define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
199 #define PP_TxCol 0x0132 /* Transmit collision counter */
223 /* initiate transmit registers */
H A Dlpc32xx_eth.c46 u32 statusinfo; /* Transmit Descriptor status */
47 u32 statushashcrc; /* Transmit Descriptor CRCs */
59 u32 packet; /* Transmit packet pointer */
71 u32 statusinfo; /* Transmit Descriptor status */
112 u32 tsv0; /* Transmit status vector register 0 */
113 u32 tsv1; /* Transmit status vector register 1 */
363 /* time out if transmit descriptor array remains full too long */ in lpc32xx_eth_send()
372 /* determine next transmit packet index to use */ in lpc32xx_eth_send()
375 /* set up transmit packet */ in lpc32xx_eth_send()
381 /* pass transmit packet to DMA engine */ in lpc32xx_eth_send()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h44 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
49 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
50 #define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
70 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
73 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
/openbmc/u-boot/drivers/sound/
H A Dbroadwell_i2s.h141 /* Transmit FIFO Underrun */
152 /* Transmit FIFO Level */
159 /* Transmit FIFO Service Request */
165 /* Transmit FIFO Not Full */
180 /* Transmit FIFO Underrun Interrupt Mask */
225 /* Receive without Transmit */
246 /* Transmit FIFO Trigger Threshold */
249 /* Microwire Transmit Data Size */
257 /* Transmit FIFO Interrupt Enable */
/openbmc/qemu/tests/qtest/
H A Dpnv-spi-seeprom-test.c18 /* To transmit READ opcode and address */
21 * N1 shift - tx 4 bytes (transmit opcode and address)
28 /* To transmit WREN(Set Write Enable Latch in status0 register) opcode */
30 /* To transmit WRITE opcode, address and data */
32 /* N1 shift - tx 8 bytes (transmit opcode, address and data) */
/openbmc/u-boot/arch/m68k/include/asm/
H A Dfsl_mcdmafec.h82 u16 txTask; /* DMA Transmit Task Number */
84 u16 txPri; /* DMA Transmit Priority */
86 u16 txInit; /* DMA Transmit Initiator */
87 u16 usedTbdIdx; /* next transmit BD to clean */
88 u16 cleanTbdNum; /* the number of available transmit BDs */
/openbmc/qemu/include/hw/char/
H A Dserial.h41 uint8_t thr; /* transmit holding register */
42 uint8_t tsr; /* transmit shift register */
74 uint64_t char_transmit_time; /* time to transmit a char in ticks */
/openbmc/u-boot/drivers/i2c/
H A Domap24xx_i2c.h13 #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
24 #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
27 #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
46 #define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
H A Ddavinci_i2c.h34 #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
44 #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
47 #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */

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