1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2ac2916a2SAlbert ARIBAUD \(3ADEV\) /*
3ac2916a2SAlbert ARIBAUD \(3ADEV\) * LPC32xx Ethernet MAC interface driver
4ac2916a2SAlbert ARIBAUD \(3ADEV\) *
5ac2916a2SAlbert ARIBAUD \(3ADEV\) * (C) Copyright 2014 DENX Software Engineering GmbH
6ac2916a2SAlbert ARIBAUD \(3ADEV\) * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
7ac2916a2SAlbert ARIBAUD \(3ADEV\) */
8ac2916a2SAlbert ARIBAUD \(3ADEV\)
9ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <common.h>
10ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <net.h>
11ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <malloc.h>
12ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <miiphy.h>
13ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <asm/io.h>
141221ce45SMasahiro Yamada #include <linux/errno.h>
15ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <asm/types.h>
16ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <asm/system.h>
17ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <asm/byteorder.h>
18ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <asm/arch/cpu.h>
19ac2916a2SAlbert ARIBAUD \(3ADEV\) #include <asm/arch/config.h>
20ac2916a2SAlbert ARIBAUD \(3ADEV\)
21ac2916a2SAlbert ARIBAUD \(3ADEV\) /*
22ac2916a2SAlbert ARIBAUD \(3ADEV\) * Notes:
23ac2916a2SAlbert ARIBAUD \(3ADEV\) *
24ac2916a2SAlbert ARIBAUD \(3ADEV\) * 1. Unless specified otherwise, all references to tables or paragraphs
25ac2916a2SAlbert ARIBAUD \(3ADEV\) * are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
26ac2916a2SAlbert ARIBAUD \(3ADEV\) *
27ac2916a2SAlbert ARIBAUD \(3ADEV\) * 2. Only bitfield masks/values which are actually used by the driver
28ac2916a2SAlbert ARIBAUD \(3ADEV\) * are defined.
29ac2916a2SAlbert ARIBAUD \(3ADEV\) */
30ac2916a2SAlbert ARIBAUD \(3ADEV\)
31ac2916a2SAlbert ARIBAUD \(3ADEV\) /* a single RX descriptor. The controller has an array of these */
32ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_rxdesc {
33ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 packet; /* Receive packet pointer */
34ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 control; /* Descriptor command status */
35ac2916a2SAlbert ARIBAUD \(3ADEV\) };
36ac2916a2SAlbert ARIBAUD \(3ADEV\)
37ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
38ac2916a2SAlbert ARIBAUD \(3ADEV\)
39ac2916a2SAlbert ARIBAUD \(3ADEV\) /* RX control bitfields/masks (see Table 330) */
40ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
41ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
42ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
43ac2916a2SAlbert ARIBAUD \(3ADEV\)
44ac2916a2SAlbert ARIBAUD \(3ADEV\) /* a single RX status. The controller has an array of these */
45ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_rxstat {
46ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 statusinfo; /* Transmit Descriptor status */
47ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 statushashcrc; /* Transmit Descriptor CRCs */
48ac2916a2SAlbert ARIBAUD \(3ADEV\) };
49ac2916a2SAlbert ARIBAUD \(3ADEV\)
50ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
51ac2916a2SAlbert ARIBAUD \(3ADEV\)
52ac2916a2SAlbert ARIBAUD \(3ADEV\) /* RX statusinfo bitfields/masks (see Table 333) */
53ac2916a2SAlbert ARIBAUD \(3ADEV\) #define RX_STAT_RXSIZE 0x000007FF
54ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Helper: OR of all errors except RANGE */
55ac2916a2SAlbert ARIBAUD \(3ADEV\) #define RX_STAT_ERRORS 0x1B800000
56ac2916a2SAlbert ARIBAUD \(3ADEV\)
57ac2916a2SAlbert ARIBAUD \(3ADEV\) /* a single TX descriptor. The controller has an array of these */
58ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_txdesc {
59ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 packet; /* Transmit packet pointer */
60ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 control; /* Descriptor control */
61ac2916a2SAlbert ARIBAUD \(3ADEV\) };
62ac2916a2SAlbert ARIBAUD \(3ADEV\)
63ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
64ac2916a2SAlbert ARIBAUD \(3ADEV\)
65ac2916a2SAlbert ARIBAUD \(3ADEV\) /* TX control bitfields/masks (see Table 335) */
66ac2916a2SAlbert ARIBAUD \(3ADEV\) #define TX_CTRL_TXSIZE 0x000007FF
67ac2916a2SAlbert ARIBAUD \(3ADEV\) #define TX_CTRL_LAST 0x40000000
68ac2916a2SAlbert ARIBAUD \(3ADEV\)
69ac2916a2SAlbert ARIBAUD \(3ADEV\) /* a single TX status. The controller has an array of these */
70ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_txstat {
71ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 statusinfo; /* Transmit Descriptor status */
72ac2916a2SAlbert ARIBAUD \(3ADEV\) };
73ac2916a2SAlbert ARIBAUD \(3ADEV\)
74ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
75ac2916a2SAlbert ARIBAUD \(3ADEV\)
76ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Ethernet MAC interface registers (see Table 283) */
77ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers {
78ac2916a2SAlbert ARIBAUD \(3ADEV\) /* MAC registers - 0x3106_0000 to 0x3106_01FC */
79ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mac1; /* MAC configuration register 1 */
80ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mac2; /* MAC configuration register 2 */
81ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
82ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 ipgr; /* Non-back-to-back IPG register */
83ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 clrt; /* Collision Window / Retry register */
84ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 maxf; /* Maximum Frame register */
85ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 supp; /* Phy Support register */
86ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 test;
87ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mcfg; /* MII management configuration reg. */
88ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mcmd; /* MII management command register */
89ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 madr; /* MII management address register */
90ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mwtd; /* MII management wite data register */
91ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mrdd; /* MII management read data register */
92ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mind; /* MII management indicators register */
93ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved1[2];
94ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 sa0; /* Station address register 0 */
95ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 sa1; /* Station address register 1 */
96ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 sa2; /* Station address register 2 */
97ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved2[45];
98ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Control registers */
99ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 command;
100ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 status;
101ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxdescriptor;
102ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxstatus;
103ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxdescriptornumber; /* actually, number MINUS ONE */
104ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxproduceindex; /* head of rx desc fifo */
105ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxconsumeindex; /* tail of rx desc fifo */
106ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 txdescriptor;
107ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 txstatus;
108ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 txdescriptornumber; /* actually, number MINUS ONE */
109ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 txproduceindex; /* head of rx desc fifo */
110ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 txconsumeindex; /* tail of rx desc fifo */
111ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved3[10];
112ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 tsv0; /* Transmit status vector register 0 */
113ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 tsv1; /* Transmit status vector register 1 */
114ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rsv; /* Receive status vector register */
115ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved4[3];
116ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 flowcontrolcounter;
117ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 flowcontrolstatus;
118ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved5[34];
119ac2916a2SAlbert ARIBAUD \(3ADEV\) /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
120ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxfilterctrl;
121ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxfilterwolstatus;
122ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 rxfilterwolclear;
123ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved6;
124ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 hashfilterl;
125ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 hashfilterh;
126ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved7[882];
127ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
128ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 intstatus; /* Interrupt status register */
129ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 intenable;
130ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 intclear;
131ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 intset;
132ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved8;
133ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 powerdown;
134ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 reserved9;
135ac2916a2SAlbert ARIBAUD \(3ADEV\) };
136ac2916a2SAlbert ARIBAUD \(3ADEV\)
137ac2916a2SAlbert ARIBAUD \(3ADEV\) /* MAC1 register bitfields/masks and offsets (see Table 283) */
138ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MAC1_RECV_ENABLE 0x00000001
139ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
140ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MAC1_SOFT_RESET 0x00008000
141ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Helper: general reset */
142ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MAC1_RESETS 0x0000CF00
143ac2916a2SAlbert ARIBAUD \(3ADEV\)
144ac2916a2SAlbert ARIBAUD \(3ADEV\) /* MAC2 register bitfields/masks and offsets (see Table 284) */
145ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MAC2_FULL_DUPLEX 0x00000001
146ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MAC2_CRC_ENABLE 0x00000010
147ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MAC2_PAD_CRC_ENABLE 0x00000020
148ac2916a2SAlbert ARIBAUD \(3ADEV\)
149ac2916a2SAlbert ARIBAUD \(3ADEV\) /* SUPP register bitfields/masks and offsets (see Table 290) */
150ac2916a2SAlbert ARIBAUD \(3ADEV\) #define SUPP_SPEED 0x00000100
151ac2916a2SAlbert ARIBAUD \(3ADEV\)
152ac2916a2SAlbert ARIBAUD \(3ADEV\) /* MCFG register bitfields/masks and offsets (see Table 292) */
15323f5db0eSVladimir Zapolskiy #define MCFG_RESET_MII_MGMT 0x00008000
154ac2916a2SAlbert ARIBAUD \(3ADEV\) /* divide clock by 28 (see Table 293) */
155ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
156ac2916a2SAlbert ARIBAUD \(3ADEV\)
157ac2916a2SAlbert ARIBAUD \(3ADEV\) /* MADR register bitfields/masks and offsets (see Table 295) */
158ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MADR_REG_MASK 0x0000001F
159ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MADR_PHY_MASK 0x00001F00
160ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MADR_REG_OFFSET 0
161ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MADR_PHY_OFFSET 8
162ac2916a2SAlbert ARIBAUD \(3ADEV\)
163ac2916a2SAlbert ARIBAUD \(3ADEV\) /* MIND register bitfields/masks (see Table 298) */
164ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MIND_BUSY 0x00000001
165ac2916a2SAlbert ARIBAUD \(3ADEV\)
166ac2916a2SAlbert ARIBAUD \(3ADEV\) /* COMMAND register bitfields/masks and offsets (see Table 283) */
167ac2916a2SAlbert ARIBAUD \(3ADEV\) #define COMMAND_RXENABLE 0x00000001
168ac2916a2SAlbert ARIBAUD \(3ADEV\) #define COMMAND_TXENABLE 0x00000002
169ac2916a2SAlbert ARIBAUD \(3ADEV\) #define COMMAND_PASSRUNTFRAME 0x00000040
1701a791892SVladimir Zapolskiy #define COMMAND_RMII 0x00000200
171ac2916a2SAlbert ARIBAUD \(3ADEV\) #define COMMAND_FULL_DUPLEX 0x00000400
172ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Helper: general reset */
1736e039b4cSVladimir Zapolskiy #define COMMAND_RESETS 0x00000038
174ac2916a2SAlbert ARIBAUD \(3ADEV\)
175ac2916a2SAlbert ARIBAUD \(3ADEV\) /* STATUS register bitfields/masks and offsets (see Table 283) */
176ac2916a2SAlbert ARIBAUD \(3ADEV\) #define STATUS_RXSTATUS 0x00000001
177ac2916a2SAlbert ARIBAUD \(3ADEV\) #define STATUS_TXSTATUS 0x00000002
178ac2916a2SAlbert ARIBAUD \(3ADEV\)
179ac2916a2SAlbert ARIBAUD \(3ADEV\) /* RXFILTERCTRL register bitfields/masks (see Table 319) */
180ac2916a2SAlbert ARIBAUD \(3ADEV\) #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
181ac2916a2SAlbert ARIBAUD \(3ADEV\) #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
182ac2916a2SAlbert ARIBAUD \(3ADEV\)
183ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Buffers and descriptors */
184ac2916a2SAlbert ARIBAUD \(3ADEV\)
185ac2916a2SAlbert ARIBAUD \(3ADEV\) #define ATTRS(n) __aligned(n)
186ac2916a2SAlbert ARIBAUD \(3ADEV\)
187ac2916a2SAlbert ARIBAUD \(3ADEV\) #define TX_BUF_COUNT 4
188ac2916a2SAlbert ARIBAUD \(3ADEV\) #define RX_BUF_COUNT 4
189ac2916a2SAlbert ARIBAUD \(3ADEV\)
190ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_buffers {
191ac2916a2SAlbert ARIBAUD \(3ADEV\) ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
192ac2916a2SAlbert ARIBAUD \(3ADEV\) ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
193ac2916a2SAlbert ARIBAUD \(3ADEV\) ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
194ac2916a2SAlbert ARIBAUD \(3ADEV\) ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
195ac2916a2SAlbert ARIBAUD \(3ADEV\) ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
196ac2916a2SAlbert ARIBAUD \(3ADEV\) ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
197ac2916a2SAlbert ARIBAUD \(3ADEV\) };
198ac2916a2SAlbert ARIBAUD \(3ADEV\)
199ac2916a2SAlbert ARIBAUD \(3ADEV\) /* port device data struct */
200ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device {
201ac2916a2SAlbert ARIBAUD \(3ADEV\) struct eth_device dev;
202ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs;
203ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_buffers *bufs;
2041a791892SVladimir Zapolskiy bool phy_rmii;
205ac2916a2SAlbert ARIBAUD \(3ADEV\) };
206ac2916a2SAlbert ARIBAUD \(3ADEV\)
207ac2916a2SAlbert ARIBAUD \(3ADEV\) #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
208ac2916a2SAlbert ARIBAUD \(3ADEV\)
209ac2916a2SAlbert ARIBAUD \(3ADEV\) /* generic macros */
210ac2916a2SAlbert ARIBAUD \(3ADEV\) #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
211ac2916a2SAlbert ARIBAUD \(3ADEV\)
212ac2916a2SAlbert ARIBAUD \(3ADEV\) /* timeout for MII polling */
213ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MII_TIMEOUT 10000000
214ac2916a2SAlbert ARIBAUD \(3ADEV\)
215ac2916a2SAlbert ARIBAUD \(3ADEV\) /* limits for PHY and register addresses */
216ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
217ac2916a2SAlbert ARIBAUD \(3ADEV\)
218ac2916a2SAlbert ARIBAUD \(3ADEV\) #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
219ac2916a2SAlbert ARIBAUD \(3ADEV\)
220ac2916a2SAlbert ARIBAUD \(3ADEV\) #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
221ac2916a2SAlbert ARIBAUD \(3ADEV\) /*
222ac2916a2SAlbert ARIBAUD \(3ADEV\) * mii_reg_read - miiphy_read callback function.
223ac2916a2SAlbert ARIBAUD \(3ADEV\) *
224ac2916a2SAlbert ARIBAUD \(3ADEV\) * Returns 16bit phy register value, or 0xffff on error
225ac2916a2SAlbert ARIBAUD \(3ADEV\) */
mii_reg_read(struct mii_dev * bus,int phy_adr,int devad,int reg_ofs)2265a49f174SJoe Hershberger static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad,
2275a49f174SJoe Hershberger int reg_ofs)
228ac2916a2SAlbert ARIBAUD \(3ADEV\) {
2295a49f174SJoe Hershberger u16 data = 0;
2305a49f174SJoe Hershberger struct eth_device *dev = eth_get_dev_by_name(bus->name);
231ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
232ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
233ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mind_reg;
234ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 timeout;
235ac2916a2SAlbert ARIBAUD \(3ADEV\)
236ac2916a2SAlbert ARIBAUD \(3ADEV\) /* check parameters */
237ac2916a2SAlbert ARIBAUD \(3ADEV\) if (phy_adr > MII_MAX_PHY) {
238ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("%s:%u: Invalid PHY address %d\n",
239ac2916a2SAlbert ARIBAUD \(3ADEV\) __func__, __LINE__, phy_adr);
240ac2916a2SAlbert ARIBAUD \(3ADEV\) return -EFAULT;
241ac2916a2SAlbert ARIBAUD \(3ADEV\) }
242ac2916a2SAlbert ARIBAUD \(3ADEV\) if (reg_ofs > MII_MAX_REG) {
243ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("%s:%u: Invalid register offset %d\n",
244ac2916a2SAlbert ARIBAUD \(3ADEV\) __func__, __LINE__, reg_ofs);
245ac2916a2SAlbert ARIBAUD \(3ADEV\) return -EFAULT;
246ac2916a2SAlbert ARIBAUD \(3ADEV\) }
247ac2916a2SAlbert ARIBAUD \(3ADEV\)
248ac2916a2SAlbert ARIBAUD \(3ADEV\) /* write the phy and reg addressse into the MII address reg */
249ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
250ac2916a2SAlbert ARIBAUD \(3ADEV\) ®s->madr);
251ac2916a2SAlbert ARIBAUD \(3ADEV\)
252ac2916a2SAlbert ARIBAUD \(3ADEV\) /* write 1 to the MII command register to cause a read */
253ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(1, ®s->mcmd);
254ac2916a2SAlbert ARIBAUD \(3ADEV\)
255ac2916a2SAlbert ARIBAUD \(3ADEV\) /* wait till the MII is not busy */
256ac2916a2SAlbert ARIBAUD \(3ADEV\) timeout = MII_TIMEOUT;
257ac2916a2SAlbert ARIBAUD \(3ADEV\) do {
258ac2916a2SAlbert ARIBAUD \(3ADEV\) /* read MII indicators register */
259ac2916a2SAlbert ARIBAUD \(3ADEV\) mind_reg = readl(®s->mind);
260ac2916a2SAlbert ARIBAUD \(3ADEV\) if (--timeout == 0)
261ac2916a2SAlbert ARIBAUD \(3ADEV\) break;
262ac2916a2SAlbert ARIBAUD \(3ADEV\) } while (mind_reg & MIND_BUSY);
263ac2916a2SAlbert ARIBAUD \(3ADEV\)
264ac2916a2SAlbert ARIBAUD \(3ADEV\) /* write 0 to the MII command register to finish the read */
265ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(0, ®s->mcmd);
266ac2916a2SAlbert ARIBAUD \(3ADEV\)
267ac2916a2SAlbert ARIBAUD \(3ADEV\) if (timeout == 0) {
268ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
269ac2916a2SAlbert ARIBAUD \(3ADEV\) return -EFAULT;
270ac2916a2SAlbert ARIBAUD \(3ADEV\) }
271ac2916a2SAlbert ARIBAUD \(3ADEV\)
2725a49f174SJoe Hershberger data = (u16) readl(®s->mrdd);
273ac2916a2SAlbert ARIBAUD \(3ADEV\)
274ac2916a2SAlbert ARIBAUD \(3ADEV\) debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
2755a49f174SJoe Hershberger reg_ofs, data);
276ac2916a2SAlbert ARIBAUD \(3ADEV\)
2775a49f174SJoe Hershberger return data;
278ac2916a2SAlbert ARIBAUD \(3ADEV\) }
279ac2916a2SAlbert ARIBAUD \(3ADEV\)
280ac2916a2SAlbert ARIBAUD \(3ADEV\) /*
281ac2916a2SAlbert ARIBAUD \(3ADEV\) * mii_reg_write - imiiphy_write callback function.
282ac2916a2SAlbert ARIBAUD \(3ADEV\) *
283ac2916a2SAlbert ARIBAUD \(3ADEV\) * Returns 0 if write succeed, -EINVAL on bad parameters
284ac2916a2SAlbert ARIBAUD \(3ADEV\) * -ETIME on timeout
285ac2916a2SAlbert ARIBAUD \(3ADEV\) */
mii_reg_write(struct mii_dev * bus,int phy_adr,int devad,int reg_ofs,u16 data)2865a49f174SJoe Hershberger static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
2875a49f174SJoe Hershberger int reg_ofs, u16 data)
288ac2916a2SAlbert ARIBAUD \(3ADEV\) {
2895a49f174SJoe Hershberger struct eth_device *dev = eth_get_dev_by_name(bus->name);
290ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
291ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
292ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 mind_reg;
293ac2916a2SAlbert ARIBAUD \(3ADEV\) u32 timeout;
294ac2916a2SAlbert ARIBAUD \(3ADEV\)
295ac2916a2SAlbert ARIBAUD \(3ADEV\) /* check parameters */
296ac2916a2SAlbert ARIBAUD \(3ADEV\) if (phy_adr > MII_MAX_PHY) {
297ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("%s:%u: Invalid PHY address %d\n",
298ac2916a2SAlbert ARIBAUD \(3ADEV\) __func__, __LINE__, phy_adr);
299ac2916a2SAlbert ARIBAUD \(3ADEV\) return -EFAULT;
300ac2916a2SAlbert ARIBAUD \(3ADEV\) }
301ac2916a2SAlbert ARIBAUD \(3ADEV\) if (reg_ofs > MII_MAX_REG) {
302ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("%s:%u: Invalid register offset %d\n",
303ac2916a2SAlbert ARIBAUD \(3ADEV\) __func__, __LINE__, reg_ofs);
304ac2916a2SAlbert ARIBAUD \(3ADEV\) return -EFAULT;
305ac2916a2SAlbert ARIBAUD \(3ADEV\) }
306ac2916a2SAlbert ARIBAUD \(3ADEV\)
30779206c04SVladimir Zapolskiy /* write the phy and reg addressse into the MII address reg */
30879206c04SVladimir Zapolskiy writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
30979206c04SVladimir Zapolskiy ®s->madr);
31079206c04SVladimir Zapolskiy
31179206c04SVladimir Zapolskiy /* write data to the MII write register */
31279206c04SVladimir Zapolskiy writel(data, ®s->mwtd);
31379206c04SVladimir Zapolskiy
314ac2916a2SAlbert ARIBAUD \(3ADEV\) /* wait till the MII is not busy */
315ac2916a2SAlbert ARIBAUD \(3ADEV\) timeout = MII_TIMEOUT;
316ac2916a2SAlbert ARIBAUD \(3ADEV\) do {
317ac2916a2SAlbert ARIBAUD \(3ADEV\) /* read MII indicators register */
318ac2916a2SAlbert ARIBAUD \(3ADEV\) mind_reg = readl(®s->mind);
319ac2916a2SAlbert ARIBAUD \(3ADEV\) if (--timeout == 0)
320ac2916a2SAlbert ARIBAUD \(3ADEV\) break;
321ac2916a2SAlbert ARIBAUD \(3ADEV\) } while (mind_reg & MIND_BUSY);
322ac2916a2SAlbert ARIBAUD \(3ADEV\)
323ac2916a2SAlbert ARIBAUD \(3ADEV\) if (timeout == 0) {
324ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("%s:%u: MII busy timeout\n", __func__,
325ac2916a2SAlbert ARIBAUD \(3ADEV\) __LINE__);
326ac2916a2SAlbert ARIBAUD \(3ADEV\) return -EFAULT;
327ac2916a2SAlbert ARIBAUD \(3ADEV\) }
328ac2916a2SAlbert ARIBAUD \(3ADEV\)
329ac2916a2SAlbert ARIBAUD \(3ADEV\) /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
330ac2916a2SAlbert ARIBAUD \(3ADEV\) reg_ofs, data);*/
331ac2916a2SAlbert ARIBAUD \(3ADEV\)
332ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
333ac2916a2SAlbert ARIBAUD \(3ADEV\) }
334ac2916a2SAlbert ARIBAUD \(3ADEV\) #endif
335ac2916a2SAlbert ARIBAUD \(3ADEV\)
336ac2916a2SAlbert ARIBAUD \(3ADEV\) /*
33768a77668SSylvain Lemieux * Provide default Ethernet buffers base address if target did not.
338ac2916a2SAlbert ARIBAUD \(3ADEV\) * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
339ac2916a2SAlbert ARIBAUD \(3ADEV\) * maximize throughput.
340ac2916a2SAlbert ARIBAUD \(3ADEV\) */
34168a77668SSylvain Lemieux #if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
34268a77668SSylvain Lemieux #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
34368a77668SSylvain Lemieux #endif
344ac2916a2SAlbert ARIBAUD \(3ADEV\)
345ac2916a2SAlbert ARIBAUD \(3ADEV\) static struct lpc32xx_eth_device lpc32xx_eth = {
346ac2916a2SAlbert ARIBAUD \(3ADEV\) .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
34768a77668SSylvain Lemieux .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
3481a791892SVladimir Zapolskiy #if defined(CONFIG_RMII)
3491a791892SVladimir Zapolskiy .phy_rmii = true,
3501a791892SVladimir Zapolskiy #endif
351ac2916a2SAlbert ARIBAUD \(3ADEV\) };
352ac2916a2SAlbert ARIBAUD \(3ADEV\)
353ac2916a2SAlbert ARIBAUD \(3ADEV\) #define TX_TIMEOUT 10000
354ac2916a2SAlbert ARIBAUD \(3ADEV\)
lpc32xx_eth_send(struct eth_device * dev,void * dataptr,int datasize)355ac2916a2SAlbert ARIBAUD \(3ADEV\) static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
356ac2916a2SAlbert ARIBAUD \(3ADEV\) {
357ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device *lpc32xx_eth_device =
358ac2916a2SAlbert ARIBAUD \(3ADEV\) container_of(dev, struct lpc32xx_eth_device, dev);
359ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
360ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
361ac2916a2SAlbert ARIBAUD \(3ADEV\) int timeout, tx_index;
362ac2916a2SAlbert ARIBAUD \(3ADEV\)
363ac2916a2SAlbert ARIBAUD \(3ADEV\) /* time out if transmit descriptor array remains full too long */
364ac2916a2SAlbert ARIBAUD \(3ADEV\) timeout = TX_TIMEOUT;
365ac2916a2SAlbert ARIBAUD \(3ADEV\) while ((readl(®s->status) & STATUS_TXSTATUS) &&
366ac2916a2SAlbert ARIBAUD \(3ADEV\) (readl(®s->txconsumeindex)
367ac2916a2SAlbert ARIBAUD \(3ADEV\) == readl(®s->txproduceindex))) {
368ac2916a2SAlbert ARIBAUD \(3ADEV\) if (timeout-- == 0)
369ac2916a2SAlbert ARIBAUD \(3ADEV\) return -1;
370ac2916a2SAlbert ARIBAUD \(3ADEV\) }
371ac2916a2SAlbert ARIBAUD \(3ADEV\)
372ac2916a2SAlbert ARIBAUD \(3ADEV\) /* determine next transmit packet index to use */
373ac2916a2SAlbert ARIBAUD \(3ADEV\) tx_index = readl(®s->txproduceindex);
374ac2916a2SAlbert ARIBAUD \(3ADEV\)
375ac2916a2SAlbert ARIBAUD \(3ADEV\) /* set up transmit packet */
376ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((u32)dataptr, &bufs->tx_desc[tx_index].packet);
377ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
378ac2916a2SAlbert ARIBAUD \(3ADEV\) &bufs->tx_desc[tx_index].control);
379ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(0, &bufs->tx_stat[tx_index].statusinfo);
380ac2916a2SAlbert ARIBAUD \(3ADEV\)
381ac2916a2SAlbert ARIBAUD \(3ADEV\) /* pass transmit packet to DMA engine */
382ac2916a2SAlbert ARIBAUD \(3ADEV\) tx_index = (tx_index + 1) % TX_BUF_COUNT;
383ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(tx_index, ®s->txproduceindex);
384ac2916a2SAlbert ARIBAUD \(3ADEV\)
385ac2916a2SAlbert ARIBAUD \(3ADEV\) /* transmission succeeded */
386ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
387ac2916a2SAlbert ARIBAUD \(3ADEV\) }
388ac2916a2SAlbert ARIBAUD \(3ADEV\)
389ac2916a2SAlbert ARIBAUD \(3ADEV\) #define RX_TIMEOUT 1000000
390ac2916a2SAlbert ARIBAUD \(3ADEV\)
lpc32xx_eth_recv(struct eth_device * dev)391ac2916a2SAlbert ARIBAUD \(3ADEV\) static int lpc32xx_eth_recv(struct eth_device *dev)
392ac2916a2SAlbert ARIBAUD \(3ADEV\) {
393ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device *lpc32xx_eth_device =
394ac2916a2SAlbert ARIBAUD \(3ADEV\) container_of(dev, struct lpc32xx_eth_device, dev);
395ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
396ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
397ac2916a2SAlbert ARIBAUD \(3ADEV\) int timeout, rx_index;
398ac2916a2SAlbert ARIBAUD \(3ADEV\)
399ac2916a2SAlbert ARIBAUD \(3ADEV\) /* time out if receive descriptor array remains empty too long */
400ac2916a2SAlbert ARIBAUD \(3ADEV\) timeout = RX_TIMEOUT;
401ac2916a2SAlbert ARIBAUD \(3ADEV\) while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) {
402ac2916a2SAlbert ARIBAUD \(3ADEV\) if (timeout-- == 0)
403ac2916a2SAlbert ARIBAUD \(3ADEV\) return -1;
404ac2916a2SAlbert ARIBAUD \(3ADEV\) }
405ac2916a2SAlbert ARIBAUD \(3ADEV\)
406ac2916a2SAlbert ARIBAUD \(3ADEV\) /* determine next receive packet index to use */
407ac2916a2SAlbert ARIBAUD \(3ADEV\) rx_index = readl(®s->rxconsumeindex);
408ac2916a2SAlbert ARIBAUD \(3ADEV\)
409ac2916a2SAlbert ARIBAUD \(3ADEV\) /* if data was valid, pass it on */
4101fd92db8SJoe Hershberger if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
4111fd92db8SJoe Hershberger net_process_received_packet(
4121fd92db8SJoe Hershberger &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
413ac2916a2SAlbert ARIBAUD \(3ADEV\) (bufs->rx_stat[rx_index].statusinfo
414ac2916a2SAlbert ARIBAUD \(3ADEV\) & RX_STAT_RXSIZE) + 1);
4151fd92db8SJoe Hershberger }
416ac2916a2SAlbert ARIBAUD \(3ADEV\)
417ac2916a2SAlbert ARIBAUD \(3ADEV\) /* pass receive slot back to DMA engine */
418ac2916a2SAlbert ARIBAUD \(3ADEV\) rx_index = (rx_index + 1) % RX_BUF_COUNT;
419ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(rx_index, ®s->rxconsumeindex);
420ac2916a2SAlbert ARIBAUD \(3ADEV\)
421ac2916a2SAlbert ARIBAUD \(3ADEV\) /* reception successful */
422ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
423ac2916a2SAlbert ARIBAUD \(3ADEV\) }
424ac2916a2SAlbert ARIBAUD \(3ADEV\)
lpc32xx_eth_write_hwaddr(struct eth_device * dev)425ac2916a2SAlbert ARIBAUD \(3ADEV\) static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
426ac2916a2SAlbert ARIBAUD \(3ADEV\) {
427ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device *lpc32xx_eth_device =
428ac2916a2SAlbert ARIBAUD \(3ADEV\) container_of(dev, struct lpc32xx_eth_device, dev);
429ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
430ac2916a2SAlbert ARIBAUD \(3ADEV\)
431ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Save station address */
432ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((unsigned long) (dev->enetaddr[0] |
433ac2916a2SAlbert ARIBAUD \(3ADEV\) (dev->enetaddr[1] << 8)), ®s->sa2);
434ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((unsigned long) (dev->enetaddr[2] |
435ac2916a2SAlbert ARIBAUD \(3ADEV\) (dev->enetaddr[3] << 8)), ®s->sa1);
436ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((unsigned long) (dev->enetaddr[4] |
437ac2916a2SAlbert ARIBAUD \(3ADEV\) (dev->enetaddr[5] << 8)), ®s->sa0);
438ac2916a2SAlbert ARIBAUD \(3ADEV\)
439ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
440ac2916a2SAlbert ARIBAUD \(3ADEV\) }
441ac2916a2SAlbert ARIBAUD \(3ADEV\)
lpc32xx_eth_init(struct eth_device * dev)442ac2916a2SAlbert ARIBAUD \(3ADEV\) static int lpc32xx_eth_init(struct eth_device *dev)
443ac2916a2SAlbert ARIBAUD \(3ADEV\) {
444ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device *lpc32xx_eth_device =
445ac2916a2SAlbert ARIBAUD \(3ADEV\) container_of(dev, struct lpc32xx_eth_device, dev);
446ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
447ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
448ac2916a2SAlbert ARIBAUD \(3ADEV\) int index;
449ac2916a2SAlbert ARIBAUD \(3ADEV\)
45023f5db0eSVladimir Zapolskiy /* Initial MAC initialization */
45123f5db0eSVladimir Zapolskiy writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1);
45223f5db0eSVladimir Zapolskiy writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2);
45323f5db0eSVladimir Zapolskiy writel(PKTSIZE_ALIGN, ®s->maxf);
45423f5db0eSVladimir Zapolskiy
45523f5db0eSVladimir Zapolskiy /* Retries: 15 (0xF). Collision window: 57 (0x37). */
45623f5db0eSVladimir Zapolskiy writel(0x370F, ®s->clrt);
45723f5db0eSVladimir Zapolskiy
45823f5db0eSVladimir Zapolskiy /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
45923f5db0eSVladimir Zapolskiy writel(0x0012, ®s->ipgr);
46023f5db0eSVladimir Zapolskiy
46123f5db0eSVladimir Zapolskiy /* pass runt (smaller than 64 bytes) frames */
4621a791892SVladimir Zapolskiy if (lpc32xx_eth_device->phy_rmii)
4631a791892SVladimir Zapolskiy writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command);
4641a791892SVladimir Zapolskiy else
46523f5db0eSVladimir Zapolskiy writel(COMMAND_PASSRUNTFRAME, ®s->command);
466ac2916a2SAlbert ARIBAUD \(3ADEV\)
467ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Configure Full/Half Duplex mode */
468ac2916a2SAlbert ARIBAUD \(3ADEV\) if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
469ac2916a2SAlbert ARIBAUD \(3ADEV\) setbits_le32(®s->mac2, MAC2_FULL_DUPLEX);
470ac2916a2SAlbert ARIBAUD \(3ADEV\) setbits_le32(®s->command, COMMAND_FULL_DUPLEX);
471ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(0x15, ®s->ipgt);
472ac2916a2SAlbert ARIBAUD \(3ADEV\) } else {
473ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(0x12, ®s->ipgt);
474ac2916a2SAlbert ARIBAUD \(3ADEV\) }
475ac2916a2SAlbert ARIBAUD \(3ADEV\)
476ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Configure 100MBit/10MBit mode */
477ac2916a2SAlbert ARIBAUD \(3ADEV\) if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
478ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(SUPP_SPEED, ®s->supp);
479ac2916a2SAlbert ARIBAUD \(3ADEV\) else
480ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(0, ®s->supp);
481ac2916a2SAlbert ARIBAUD \(3ADEV\)
482ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Save station address */
483ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((unsigned long) (dev->enetaddr[0] |
484ac2916a2SAlbert ARIBAUD \(3ADEV\) (dev->enetaddr[1] << 8)), ®s->sa2);
485ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((unsigned long) (dev->enetaddr[2] |
486ac2916a2SAlbert ARIBAUD \(3ADEV\) (dev->enetaddr[3] << 8)), ®s->sa1);
487ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((unsigned long) (dev->enetaddr[4] |
488ac2916a2SAlbert ARIBAUD \(3ADEV\) (dev->enetaddr[5] << 8)), ®s->sa0);
489ac2916a2SAlbert ARIBAUD \(3ADEV\)
490ac2916a2SAlbert ARIBAUD \(3ADEV\) /* set up transmit buffers */
491ac2916a2SAlbert ARIBAUD \(3ADEV\) for (index = 0; index < TX_BUF_COUNT; index++) {
492ac2916a2SAlbert ARIBAUD \(3ADEV\) bufs->tx_desc[index].control = 0;
493ac2916a2SAlbert ARIBAUD \(3ADEV\) bufs->tx_stat[index].statusinfo = 0;
494ac2916a2SAlbert ARIBAUD \(3ADEV\) }
495ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor);
496ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((u32)(&bufs->tx_stat), ®s->txstatus);
497ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(TX_BUF_COUNT-1, ®s->txdescriptornumber);
498ac2916a2SAlbert ARIBAUD \(3ADEV\)
499ac2916a2SAlbert ARIBAUD \(3ADEV\) /* set up receive buffers */
500ac2916a2SAlbert ARIBAUD \(3ADEV\) for (index = 0; index < RX_BUF_COUNT; index++) {
501ac2916a2SAlbert ARIBAUD \(3ADEV\) bufs->rx_desc[index].packet =
502ac2916a2SAlbert ARIBAUD \(3ADEV\) (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
503ac2916a2SAlbert ARIBAUD \(3ADEV\) bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
504ac2916a2SAlbert ARIBAUD \(3ADEV\) bufs->rx_stat[index].statusinfo = 0;
505ac2916a2SAlbert ARIBAUD \(3ADEV\) bufs->rx_stat[index].statushashcrc = 0;
506ac2916a2SAlbert ARIBAUD \(3ADEV\) }
507ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((u32)(&bufs->rx_desc), ®s->rxdescriptor);
508ac2916a2SAlbert ARIBAUD \(3ADEV\) writel((u32)(&bufs->rx_stat), ®s->rxstatus);
509ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber);
510ac2916a2SAlbert ARIBAUD \(3ADEV\)
511ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Enable broadcast and matching address packets */
512ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(RXFILTERCTRL_ACCEPTBROADCAST |
513ac2916a2SAlbert ARIBAUD \(3ADEV\) RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl);
514ac2916a2SAlbert ARIBAUD \(3ADEV\)
515ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Clear and disable interrupts */
516ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(0xFFFF, ®s->intclear);
517ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(0, ®s->intenable);
518ac2916a2SAlbert ARIBAUD \(3ADEV\)
519ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Enable receive and transmit mode of MAC ethernet core */
520ac2916a2SAlbert ARIBAUD \(3ADEV\) setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
521ac2916a2SAlbert ARIBAUD \(3ADEV\) setbits_le32(®s->mac1, MAC1_RECV_ENABLE);
522ac2916a2SAlbert ARIBAUD \(3ADEV\)
523ac2916a2SAlbert ARIBAUD \(3ADEV\) /*
524ac2916a2SAlbert ARIBAUD \(3ADEV\) * Perform a 'dummy' first send to work around Ethernet.1
525ac2916a2SAlbert ARIBAUD \(3ADEV\) * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
526ac2916a2SAlbert ARIBAUD \(3ADEV\) * Use zeroed "index" variable as the dummy.
527ac2916a2SAlbert ARIBAUD \(3ADEV\) */
528ac2916a2SAlbert ARIBAUD \(3ADEV\)
529ac2916a2SAlbert ARIBAUD \(3ADEV\) index = 0;
530ac2916a2SAlbert ARIBAUD \(3ADEV\) lpc32xx_eth_send(dev, &index, 4);
531ac2916a2SAlbert ARIBAUD \(3ADEV\)
532ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
533ac2916a2SAlbert ARIBAUD \(3ADEV\) }
534ac2916a2SAlbert ARIBAUD \(3ADEV\)
lpc32xx_eth_halt(struct eth_device * dev)535ac2916a2SAlbert ARIBAUD \(3ADEV\) static int lpc32xx_eth_halt(struct eth_device *dev)
536ac2916a2SAlbert ARIBAUD \(3ADEV\) {
537ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_device *lpc32xx_eth_device =
538ac2916a2SAlbert ARIBAUD \(3ADEV\) container_of(dev, struct lpc32xx_eth_device, dev);
539ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
540ac2916a2SAlbert ARIBAUD \(3ADEV\)
541ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Reset all MAC logic */
542ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(MAC1_RESETS, ®s->mac1);
543ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(COMMAND_RESETS, ®s->command);
544ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Let reset condition settle */
545ac2916a2SAlbert ARIBAUD \(3ADEV\) udelay(2000);
546ac2916a2SAlbert ARIBAUD \(3ADEV\)
547ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
548ac2916a2SAlbert ARIBAUD \(3ADEV\) }
549ac2916a2SAlbert ARIBAUD \(3ADEV\)
550ac2916a2SAlbert ARIBAUD \(3ADEV\) #if defined(CONFIG_PHYLIB)
lpc32xx_eth_phylib_init(struct eth_device * dev,int phyid)551ac2916a2SAlbert ARIBAUD \(3ADEV\) int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
552ac2916a2SAlbert ARIBAUD \(3ADEV\) {
5531a791892SVladimir Zapolskiy struct lpc32xx_eth_device *lpc32xx_eth_device =
5541a791892SVladimir Zapolskiy container_of(dev, struct lpc32xx_eth_device, dev);
555ac2916a2SAlbert ARIBAUD \(3ADEV\) struct mii_dev *bus;
556ac2916a2SAlbert ARIBAUD \(3ADEV\) struct phy_device *phydev;
557ac2916a2SAlbert ARIBAUD \(3ADEV\) int ret;
558ac2916a2SAlbert ARIBAUD \(3ADEV\)
559ac2916a2SAlbert ARIBAUD \(3ADEV\) bus = mdio_alloc();
560ac2916a2SAlbert ARIBAUD \(3ADEV\) if (!bus) {
561ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("mdio_alloc failed\n");
562ac2916a2SAlbert ARIBAUD \(3ADEV\) return -ENOMEM;
563ac2916a2SAlbert ARIBAUD \(3ADEV\) }
564875e0bc6SJoe Hershberger bus->read = mii_reg_read;
565875e0bc6SJoe Hershberger bus->write = mii_reg_write;
566192bc694SBen Whitten strcpy(bus->name, dev->name);
567ac2916a2SAlbert ARIBAUD \(3ADEV\)
568ac2916a2SAlbert ARIBAUD \(3ADEV\) ret = mdio_register(bus);
569ac2916a2SAlbert ARIBAUD \(3ADEV\) if (ret) {
570ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("mdio_register failed\n");
571ac2916a2SAlbert ARIBAUD \(3ADEV\) free(bus);
572ac2916a2SAlbert ARIBAUD \(3ADEV\) return -ENOMEM;
573ac2916a2SAlbert ARIBAUD \(3ADEV\) }
574ac2916a2SAlbert ARIBAUD \(3ADEV\)
5751a791892SVladimir Zapolskiy if (lpc32xx_eth_device->phy_rmii)
5761a791892SVladimir Zapolskiy phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
5771a791892SVladimir Zapolskiy else
578ac2916a2SAlbert ARIBAUD \(3ADEV\) phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
5791a791892SVladimir Zapolskiy
580ac2916a2SAlbert ARIBAUD \(3ADEV\) if (!phydev) {
581ac2916a2SAlbert ARIBAUD \(3ADEV\) printf("phy_connect failed\n");
582ac2916a2SAlbert ARIBAUD \(3ADEV\) return -ENODEV;
583ac2916a2SAlbert ARIBAUD \(3ADEV\) }
584ac2916a2SAlbert ARIBAUD \(3ADEV\)
585ac2916a2SAlbert ARIBAUD \(3ADEV\) phy_config(phydev);
586ac2916a2SAlbert ARIBAUD \(3ADEV\) phy_startup(phydev);
587ac2916a2SAlbert ARIBAUD \(3ADEV\)
588ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
589ac2916a2SAlbert ARIBAUD \(3ADEV\) }
590ac2916a2SAlbert ARIBAUD \(3ADEV\) #endif
591ac2916a2SAlbert ARIBAUD \(3ADEV\)
lpc32xx_eth_initialize(bd_t * bis)592ac2916a2SAlbert ARIBAUD \(3ADEV\) int lpc32xx_eth_initialize(bd_t *bis)
593ac2916a2SAlbert ARIBAUD \(3ADEV\) {
594ac2916a2SAlbert ARIBAUD \(3ADEV\) struct eth_device *dev = &lpc32xx_eth.dev;
595ac2916a2SAlbert ARIBAUD \(3ADEV\) struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
596ac2916a2SAlbert ARIBAUD \(3ADEV\)
597ac2916a2SAlbert ARIBAUD \(3ADEV\) /*
598ac2916a2SAlbert ARIBAUD \(3ADEV\) * Set RMII management clock rate. With HCLK at 104 MHz and
599ac2916a2SAlbert ARIBAUD \(3ADEV\) * a divider of 28, this will be 3.72 MHz.
600ac2916a2SAlbert ARIBAUD \(3ADEV\) */
60123f5db0eSVladimir Zapolskiy writel(MCFG_RESET_MII_MGMT, ®s->mcfg);
602ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg);
603ac2916a2SAlbert ARIBAUD \(3ADEV\)
604ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Reset all MAC logic */
605ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(MAC1_RESETS, ®s->mac1);
606ac2916a2SAlbert ARIBAUD \(3ADEV\) writel(COMMAND_RESETS, ®s->command);
607ac2916a2SAlbert ARIBAUD \(3ADEV\)
608ac2916a2SAlbert ARIBAUD \(3ADEV\) /* wait 10 ms for the whole I/F to reset */
609ac2916a2SAlbert ARIBAUD \(3ADEV\) udelay(10000);
610ac2916a2SAlbert ARIBAUD \(3ADEV\)
611ac2916a2SAlbert ARIBAUD \(3ADEV\) /* must be less than sizeof(dev->name) */
612ac2916a2SAlbert ARIBAUD \(3ADEV\) strcpy(dev->name, "eth0");
613ac2916a2SAlbert ARIBAUD \(3ADEV\)
614ac2916a2SAlbert ARIBAUD \(3ADEV\) dev->init = (void *)lpc32xx_eth_init;
615ac2916a2SAlbert ARIBAUD \(3ADEV\) dev->halt = (void *)lpc32xx_eth_halt;
616ac2916a2SAlbert ARIBAUD \(3ADEV\) dev->send = (void *)lpc32xx_eth_send;
617ac2916a2SAlbert ARIBAUD \(3ADEV\) dev->recv = (void *)lpc32xx_eth_recv;
618ac2916a2SAlbert ARIBAUD \(3ADEV\) dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
619ac2916a2SAlbert ARIBAUD \(3ADEV\)
620ac2916a2SAlbert ARIBAUD \(3ADEV\) /* Release SOFT reset to let MII talk to PHY */
621ac2916a2SAlbert ARIBAUD \(3ADEV\) clrbits_le32(®s->mac1, MAC1_SOFT_RESET);
622ac2916a2SAlbert ARIBAUD \(3ADEV\)
623ac2916a2SAlbert ARIBAUD \(3ADEV\) /* register driver before talking to phy */
624ac2916a2SAlbert ARIBAUD \(3ADEV\) eth_register(dev);
625ac2916a2SAlbert ARIBAUD \(3ADEV\)
626ac2916a2SAlbert ARIBAUD \(3ADEV\) #if defined(CONFIG_PHYLIB)
627fe0596caSVladimir Zapolskiy lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
628ac2916a2SAlbert ARIBAUD \(3ADEV\) #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
6295a49f174SJoe Hershberger int retval;
6305a49f174SJoe Hershberger struct mii_dev *mdiodev = mdio_alloc();
6315a49f174SJoe Hershberger if (!mdiodev)
6325a49f174SJoe Hershberger return -ENOMEM;
6335a49f174SJoe Hershberger strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
6345a49f174SJoe Hershberger mdiodev->read = mii_reg_read;
6355a49f174SJoe Hershberger mdiodev->write = mii_reg_write;
6365a49f174SJoe Hershberger
6375a49f174SJoe Hershberger retval = mdio_register(mdiodev);
6385a49f174SJoe Hershberger if (retval < 0)
6395a49f174SJoe Hershberger return retval;
640ac2916a2SAlbert ARIBAUD \(3ADEV\) #endif
641ac2916a2SAlbert ARIBAUD \(3ADEV\)
642ac2916a2SAlbert ARIBAUD \(3ADEV\) return 0;
643ac2916a2SAlbert ARIBAUD \(3ADEV\) }
644