1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2356d15ebSKaricheri, Muralidharan /* 3356d15ebSKaricheri, Muralidharan * (C) Copyright 2004-2014 4356d15ebSKaricheri, Muralidharan * Texas Instruments, <www.ti.com> 5356d15ebSKaricheri, Muralidharan * 6356d15ebSKaricheri, Muralidharan * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7356d15ebSKaricheri, Muralidharan */ 8356d15ebSKaricheri, Muralidharan #ifndef _DAVINCI_I2C_H_ 9356d15ebSKaricheri, Muralidharan #define _DAVINCI_I2C_H_ 10356d15ebSKaricheri, Muralidharan 11356d15ebSKaricheri, Muralidharan #define I2C_WRITE 0 12356d15ebSKaricheri, Muralidharan #define I2C_READ 1 13356d15ebSKaricheri, Muralidharan 14e8459dccSVitaly Andrianov struct i2c_regs { 15e8459dccSVitaly Andrianov u32 i2c_oa; 16e8459dccSVitaly Andrianov u32 i2c_ie; 17e8459dccSVitaly Andrianov u32 i2c_stat; 18e8459dccSVitaly Andrianov u32 i2c_scll; 19e8459dccSVitaly Andrianov u32 i2c_sclh; 20e8459dccSVitaly Andrianov u32 i2c_cnt; 21e8459dccSVitaly Andrianov u32 i2c_drr; 22e8459dccSVitaly Andrianov u32 i2c_sa; 23e8459dccSVitaly Andrianov u32 i2c_dxr; 24e8459dccSVitaly Andrianov u32 i2c_con; 25e8459dccSVitaly Andrianov u32 i2c_iv; 26e8459dccSVitaly Andrianov u32 res_2c; 27e8459dccSVitaly Andrianov u32 i2c_psc; 28e8459dccSVitaly Andrianov }; 29356d15ebSKaricheri, Muralidharan 30356d15ebSKaricheri, Muralidharan /* I2C masks */ 31356d15ebSKaricheri, Muralidharan 32356d15ebSKaricheri, Muralidharan /* I2C Interrupt Enable Register (I2C_IE): */ 33356d15ebSKaricheri, Muralidharan #define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ 34356d15ebSKaricheri, Muralidharan #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ 35356d15ebSKaricheri, Muralidharan #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ 36356d15ebSKaricheri, Muralidharan #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ 37356d15ebSKaricheri, Muralidharan #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ 38356d15ebSKaricheri, Muralidharan #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ 39356d15ebSKaricheri, Muralidharan 40356d15ebSKaricheri, Muralidharan /* I2C Status Register (I2C_STAT): */ 41356d15ebSKaricheri, Muralidharan 42356d15ebSKaricheri, Muralidharan #define I2C_STAT_BB (1 << 12) /* Bus busy */ 43356d15ebSKaricheri, Muralidharan #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 44356d15ebSKaricheri, Muralidharan #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 45356d15ebSKaricheri, Muralidharan #define I2C_STAT_AAS (1 << 9) /* Address as slave */ 46356d15ebSKaricheri, Muralidharan #define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ 47356d15ebSKaricheri, Muralidharan #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 48356d15ebSKaricheri, Muralidharan #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 49356d15ebSKaricheri, Muralidharan #define I2C_STAT_ARDY (1 << 2) /* Register access ready */ 50356d15ebSKaricheri, Muralidharan #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ 51356d15ebSKaricheri, Muralidharan #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ 52356d15ebSKaricheri, Muralidharan 53356d15ebSKaricheri, Muralidharan /* I2C Interrupt Code Register (I2C_INTCODE): */ 54356d15ebSKaricheri, Muralidharan 55356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_MASK 7 56356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_NONE 0 57356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_AL 1 /* Arbitration lost */ 58356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ 59356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_ARDY 3 /* Register access ready */ 60356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_RRDY 4 /* Rcv data ready */ 61356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_XRDY 5 /* Xmit data ready */ 62356d15ebSKaricheri, Muralidharan #define I2C_INTCODE_SCD 6 /* Stop condition detect */ 63356d15ebSKaricheri, Muralidharan 64356d15ebSKaricheri, Muralidharan /* I2C Configuration Register (I2C_CON): */ 65356d15ebSKaricheri, Muralidharan 66356d15ebSKaricheri, Muralidharan #define I2C_CON_EN (1 << 5) /* I2C module enable */ 67356d15ebSKaricheri, Muralidharan #define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ 68356d15ebSKaricheri, Muralidharan #define I2C_CON_MST (1 << 10) /* Master/slave mode */ 69356d15ebSKaricheri, Muralidharan #define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */ 70356d15ebSKaricheri, Muralidharan #define I2C_CON_XA (1 << 8) /* Expand address */ 71356d15ebSKaricheri, Muralidharan #define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ 72356d15ebSKaricheri, Muralidharan #define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ 73356d15ebSKaricheri, Muralidharan #define I2C_CON_FREE (1 << 14) /* Free run on emulation */ 74356d15ebSKaricheri, Muralidharan 75356d15ebSKaricheri, Muralidharan #define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ 76356d15ebSKaricheri, Muralidharan 77356d15ebSKaricheri, Muralidharan #endif 78