Lines Matching full:transmit

42     REG_TX_CTL_0           = 0x0010, /* Transmit Control 0 */
43 REG_TX_CTL_1 = 0x0014, /* Transmit Control 1 */
44 REG_TX_FLOW_CTL = 0x001C, /* Transmit Flow Control */
45 REG_TX_DMA_DESC_LIST = 0x0020, /* Transmit Descriptor List Address */
56 REG_TX_DMA_STA = 0x00B0, /* Transmit DMA Status */
57 REG_TX_CUR_DESC = 0x00B4, /* Transmit Current Descriptor */
58 REG_TX_CUR_BUF = 0x00B8, /* Transmit Current Buffer */
157 /* Transmit/receive frame descriptor */
171 /* Transmit frame descriptor flags */
519 /* Read all transmit descriptors */ in allwinner_sun8i_emac_transmit()
550 /* Raise transmit completed interrupt */ in allwinner_sun8i_emac_transmit()
605 case REG_TX_CTL_0: /* Transmit Control 0 */ in allwinner_sun8i_emac_read()
608 case REG_TX_CTL_1: /* Transmit Control 1 */ in allwinner_sun8i_emac_read()
611 case REG_TX_FLOW_CTL: /* Transmit Flow Control */ in allwinner_sun8i_emac_read()
614 case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ in allwinner_sun8i_emac_read()
644 case REG_TX_DMA_STA: /* Transmit DMA Status */ in allwinner_sun8i_emac_read()
646 case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ in allwinner_sun8i_emac_read()
649 case REG_TX_CUR_BUF: /* Transmit Current Buffer */ in allwinner_sun8i_emac_read()
712 case REG_TX_CTL_0: /* Transmit Control 0 */ in allwinner_sun8i_emac_write()
715 case REG_TX_CTL_1: /* Transmit Control 1 */ in allwinner_sun8i_emac_write()
721 case REG_TX_FLOW_CTL: /* Transmit Flow Control */ in allwinner_sun8i_emac_write()
724 case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */ in allwinner_sun8i_emac_write()
761 case REG_TX_DMA_STA: /* Transmit DMA Status */ in allwinner_sun8i_emac_write()
762 case REG_TX_CUR_DESC: /* Transmit Current Descriptor */ in allwinner_sun8i_emac_write()
763 case REG_TX_CUR_BUF: /* Transmit Current Buffer */ in allwinner_sun8i_emac_write()