1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * LPC32xx Ethernet MAC interface driver
4 *
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
7 */
8
9 #include <common.h>
10 #include <net.h>
11 #include <malloc.h>
12 #include <miiphy.h>
13 #include <asm/io.h>
14 #include <linux/errno.h>
15 #include <asm/types.h>
16 #include <asm/system.h>
17 #include <asm/byteorder.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/config.h>
20
21 /*
22 * Notes:
23 *
24 * 1. Unless specified otherwise, all references to tables or paragraphs
25 * are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
26 *
27 * 2. Only bitfield masks/values which are actually used by the driver
28 * are defined.
29 */
30
31 /* a single RX descriptor. The controller has an array of these */
32 struct lpc32xx_eth_rxdesc {
33 u32 packet; /* Receive packet pointer */
34 u32 control; /* Descriptor command status */
35 };
36
37 #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
38
39 /* RX control bitfields/masks (see Table 330) */
40 #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
41 #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
42 #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
43
44 /* a single RX status. The controller has an array of these */
45 struct lpc32xx_eth_rxstat {
46 u32 statusinfo; /* Transmit Descriptor status */
47 u32 statushashcrc; /* Transmit Descriptor CRCs */
48 };
49
50 #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
51
52 /* RX statusinfo bitfields/masks (see Table 333) */
53 #define RX_STAT_RXSIZE 0x000007FF
54 /* Helper: OR of all errors except RANGE */
55 #define RX_STAT_ERRORS 0x1B800000
56
57 /* a single TX descriptor. The controller has an array of these */
58 struct lpc32xx_eth_txdesc {
59 u32 packet; /* Transmit packet pointer */
60 u32 control; /* Descriptor control */
61 };
62
63 #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
64
65 /* TX control bitfields/masks (see Table 335) */
66 #define TX_CTRL_TXSIZE 0x000007FF
67 #define TX_CTRL_LAST 0x40000000
68
69 /* a single TX status. The controller has an array of these */
70 struct lpc32xx_eth_txstat {
71 u32 statusinfo; /* Transmit Descriptor status */
72 };
73
74 #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
75
76 /* Ethernet MAC interface registers (see Table 283) */
77 struct lpc32xx_eth_registers {
78 /* MAC registers - 0x3106_0000 to 0x3106_01FC */
79 u32 mac1; /* MAC configuration register 1 */
80 u32 mac2; /* MAC configuration register 2 */
81 u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
82 u32 ipgr; /* Non-back-to-back IPG register */
83 u32 clrt; /* Collision Window / Retry register */
84 u32 maxf; /* Maximum Frame register */
85 u32 supp; /* Phy Support register */
86 u32 test;
87 u32 mcfg; /* MII management configuration reg. */
88 u32 mcmd; /* MII management command register */
89 u32 madr; /* MII management address register */
90 u32 mwtd; /* MII management wite data register */
91 u32 mrdd; /* MII management read data register */
92 u32 mind; /* MII management indicators register */
93 u32 reserved1[2];
94 u32 sa0; /* Station address register 0 */
95 u32 sa1; /* Station address register 1 */
96 u32 sa2; /* Station address register 2 */
97 u32 reserved2[45];
98 /* Control registers */
99 u32 command;
100 u32 status;
101 u32 rxdescriptor;
102 u32 rxstatus;
103 u32 rxdescriptornumber; /* actually, number MINUS ONE */
104 u32 rxproduceindex; /* head of rx desc fifo */
105 u32 rxconsumeindex; /* tail of rx desc fifo */
106 u32 txdescriptor;
107 u32 txstatus;
108 u32 txdescriptornumber; /* actually, number MINUS ONE */
109 u32 txproduceindex; /* head of rx desc fifo */
110 u32 txconsumeindex; /* tail of rx desc fifo */
111 u32 reserved3[10];
112 u32 tsv0; /* Transmit status vector register 0 */
113 u32 tsv1; /* Transmit status vector register 1 */
114 u32 rsv; /* Receive status vector register */
115 u32 reserved4[3];
116 u32 flowcontrolcounter;
117 u32 flowcontrolstatus;
118 u32 reserved5[34];
119 /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
120 u32 rxfilterctrl;
121 u32 rxfilterwolstatus;
122 u32 rxfilterwolclear;
123 u32 reserved6;
124 u32 hashfilterl;
125 u32 hashfilterh;
126 u32 reserved7[882];
127 /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
128 u32 intstatus; /* Interrupt status register */
129 u32 intenable;
130 u32 intclear;
131 u32 intset;
132 u32 reserved8;
133 u32 powerdown;
134 u32 reserved9;
135 };
136
137 /* MAC1 register bitfields/masks and offsets (see Table 283) */
138 #define MAC1_RECV_ENABLE 0x00000001
139 #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
140 #define MAC1_SOFT_RESET 0x00008000
141 /* Helper: general reset */
142 #define MAC1_RESETS 0x0000CF00
143
144 /* MAC2 register bitfields/masks and offsets (see Table 284) */
145 #define MAC2_FULL_DUPLEX 0x00000001
146 #define MAC2_CRC_ENABLE 0x00000010
147 #define MAC2_PAD_CRC_ENABLE 0x00000020
148
149 /* SUPP register bitfields/masks and offsets (see Table 290) */
150 #define SUPP_SPEED 0x00000100
151
152 /* MCFG register bitfields/masks and offsets (see Table 292) */
153 #define MCFG_RESET_MII_MGMT 0x00008000
154 /* divide clock by 28 (see Table 293) */
155 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
156
157 /* MADR register bitfields/masks and offsets (see Table 295) */
158 #define MADR_REG_MASK 0x0000001F
159 #define MADR_PHY_MASK 0x00001F00
160 #define MADR_REG_OFFSET 0
161 #define MADR_PHY_OFFSET 8
162
163 /* MIND register bitfields/masks (see Table 298) */
164 #define MIND_BUSY 0x00000001
165
166 /* COMMAND register bitfields/masks and offsets (see Table 283) */
167 #define COMMAND_RXENABLE 0x00000001
168 #define COMMAND_TXENABLE 0x00000002
169 #define COMMAND_PASSRUNTFRAME 0x00000040
170 #define COMMAND_RMII 0x00000200
171 #define COMMAND_FULL_DUPLEX 0x00000400
172 /* Helper: general reset */
173 #define COMMAND_RESETS 0x00000038
174
175 /* STATUS register bitfields/masks and offsets (see Table 283) */
176 #define STATUS_RXSTATUS 0x00000001
177 #define STATUS_TXSTATUS 0x00000002
178
179 /* RXFILTERCTRL register bitfields/masks (see Table 319) */
180 #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
181 #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
182
183 /* Buffers and descriptors */
184
185 #define ATTRS(n) __aligned(n)
186
187 #define TX_BUF_COUNT 4
188 #define RX_BUF_COUNT 4
189
190 struct lpc32xx_eth_buffers {
191 ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
192 ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
193 ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
194 ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
195 ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
196 ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
197 };
198
199 /* port device data struct */
200 struct lpc32xx_eth_device {
201 struct eth_device dev;
202 struct lpc32xx_eth_registers *regs;
203 struct lpc32xx_eth_buffers *bufs;
204 bool phy_rmii;
205 };
206
207 #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
208
209 /* generic macros */
210 #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
211
212 /* timeout for MII polling */
213 #define MII_TIMEOUT 10000000
214
215 /* limits for PHY and register addresses */
216 #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
217
218 #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
219
220 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
221 /*
222 * mii_reg_read - miiphy_read callback function.
223 *
224 * Returns 16bit phy register value, or 0xffff on error
225 */
mii_reg_read(struct mii_dev * bus,int phy_adr,int devad,int reg_ofs)226 static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad,
227 int reg_ofs)
228 {
229 u16 data = 0;
230 struct eth_device *dev = eth_get_dev_by_name(bus->name);
231 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
232 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
233 u32 mind_reg;
234 u32 timeout;
235
236 /* check parameters */
237 if (phy_adr > MII_MAX_PHY) {
238 printf("%s:%u: Invalid PHY address %d\n",
239 __func__, __LINE__, phy_adr);
240 return -EFAULT;
241 }
242 if (reg_ofs > MII_MAX_REG) {
243 printf("%s:%u: Invalid register offset %d\n",
244 __func__, __LINE__, reg_ofs);
245 return -EFAULT;
246 }
247
248 /* write the phy and reg addressse into the MII address reg */
249 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
250 ®s->madr);
251
252 /* write 1 to the MII command register to cause a read */
253 writel(1, ®s->mcmd);
254
255 /* wait till the MII is not busy */
256 timeout = MII_TIMEOUT;
257 do {
258 /* read MII indicators register */
259 mind_reg = readl(®s->mind);
260 if (--timeout == 0)
261 break;
262 } while (mind_reg & MIND_BUSY);
263
264 /* write 0 to the MII command register to finish the read */
265 writel(0, ®s->mcmd);
266
267 if (timeout == 0) {
268 printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
269 return -EFAULT;
270 }
271
272 data = (u16) readl(®s->mrdd);
273
274 debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
275 reg_ofs, data);
276
277 return data;
278 }
279
280 /*
281 * mii_reg_write - imiiphy_write callback function.
282 *
283 * Returns 0 if write succeed, -EINVAL on bad parameters
284 * -ETIME on timeout
285 */
mii_reg_write(struct mii_dev * bus,int phy_adr,int devad,int reg_ofs,u16 data)286 static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
287 int reg_ofs, u16 data)
288 {
289 struct eth_device *dev = eth_get_dev_by_name(bus->name);
290 struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
291 struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
292 u32 mind_reg;
293 u32 timeout;
294
295 /* check parameters */
296 if (phy_adr > MII_MAX_PHY) {
297 printf("%s:%u: Invalid PHY address %d\n",
298 __func__, __LINE__, phy_adr);
299 return -EFAULT;
300 }
301 if (reg_ofs > MII_MAX_REG) {
302 printf("%s:%u: Invalid register offset %d\n",
303 __func__, __LINE__, reg_ofs);
304 return -EFAULT;
305 }
306
307 /* write the phy and reg addressse into the MII address reg */
308 writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
309 ®s->madr);
310
311 /* write data to the MII write register */
312 writel(data, ®s->mwtd);
313
314 /* wait till the MII is not busy */
315 timeout = MII_TIMEOUT;
316 do {
317 /* read MII indicators register */
318 mind_reg = readl(®s->mind);
319 if (--timeout == 0)
320 break;
321 } while (mind_reg & MIND_BUSY);
322
323 if (timeout == 0) {
324 printf("%s:%u: MII busy timeout\n", __func__,
325 __LINE__);
326 return -EFAULT;
327 }
328
329 /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
330 reg_ofs, data);*/
331
332 return 0;
333 }
334 #endif
335
336 /*
337 * Provide default Ethernet buffers base address if target did not.
338 * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
339 * maximize throughput.
340 */
341 #if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
342 #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
343 #endif
344
345 static struct lpc32xx_eth_device lpc32xx_eth = {
346 .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
347 .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
348 #if defined(CONFIG_RMII)
349 .phy_rmii = true,
350 #endif
351 };
352
353 #define TX_TIMEOUT 10000
354
lpc32xx_eth_send(struct eth_device * dev,void * dataptr,int datasize)355 static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
356 {
357 struct lpc32xx_eth_device *lpc32xx_eth_device =
358 container_of(dev, struct lpc32xx_eth_device, dev);
359 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
360 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
361 int timeout, tx_index;
362
363 /* time out if transmit descriptor array remains full too long */
364 timeout = TX_TIMEOUT;
365 while ((readl(®s->status) & STATUS_TXSTATUS) &&
366 (readl(®s->txconsumeindex)
367 == readl(®s->txproduceindex))) {
368 if (timeout-- == 0)
369 return -1;
370 }
371
372 /* determine next transmit packet index to use */
373 tx_index = readl(®s->txproduceindex);
374
375 /* set up transmit packet */
376 writel((u32)dataptr, &bufs->tx_desc[tx_index].packet);
377 writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
378 &bufs->tx_desc[tx_index].control);
379 writel(0, &bufs->tx_stat[tx_index].statusinfo);
380
381 /* pass transmit packet to DMA engine */
382 tx_index = (tx_index + 1) % TX_BUF_COUNT;
383 writel(tx_index, ®s->txproduceindex);
384
385 /* transmission succeeded */
386 return 0;
387 }
388
389 #define RX_TIMEOUT 1000000
390
lpc32xx_eth_recv(struct eth_device * dev)391 static int lpc32xx_eth_recv(struct eth_device *dev)
392 {
393 struct lpc32xx_eth_device *lpc32xx_eth_device =
394 container_of(dev, struct lpc32xx_eth_device, dev);
395 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
396 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
397 int timeout, rx_index;
398
399 /* time out if receive descriptor array remains empty too long */
400 timeout = RX_TIMEOUT;
401 while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) {
402 if (timeout-- == 0)
403 return -1;
404 }
405
406 /* determine next receive packet index to use */
407 rx_index = readl(®s->rxconsumeindex);
408
409 /* if data was valid, pass it on */
410 if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
411 net_process_received_packet(
412 &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
413 (bufs->rx_stat[rx_index].statusinfo
414 & RX_STAT_RXSIZE) + 1);
415 }
416
417 /* pass receive slot back to DMA engine */
418 rx_index = (rx_index + 1) % RX_BUF_COUNT;
419 writel(rx_index, ®s->rxconsumeindex);
420
421 /* reception successful */
422 return 0;
423 }
424
lpc32xx_eth_write_hwaddr(struct eth_device * dev)425 static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
426 {
427 struct lpc32xx_eth_device *lpc32xx_eth_device =
428 container_of(dev, struct lpc32xx_eth_device, dev);
429 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
430
431 /* Save station address */
432 writel((unsigned long) (dev->enetaddr[0] |
433 (dev->enetaddr[1] << 8)), ®s->sa2);
434 writel((unsigned long) (dev->enetaddr[2] |
435 (dev->enetaddr[3] << 8)), ®s->sa1);
436 writel((unsigned long) (dev->enetaddr[4] |
437 (dev->enetaddr[5] << 8)), ®s->sa0);
438
439 return 0;
440 }
441
lpc32xx_eth_init(struct eth_device * dev)442 static int lpc32xx_eth_init(struct eth_device *dev)
443 {
444 struct lpc32xx_eth_device *lpc32xx_eth_device =
445 container_of(dev, struct lpc32xx_eth_device, dev);
446 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
447 struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
448 int index;
449
450 /* Initial MAC initialization */
451 writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1);
452 writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2);
453 writel(PKTSIZE_ALIGN, ®s->maxf);
454
455 /* Retries: 15 (0xF). Collision window: 57 (0x37). */
456 writel(0x370F, ®s->clrt);
457
458 /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
459 writel(0x0012, ®s->ipgr);
460
461 /* pass runt (smaller than 64 bytes) frames */
462 if (lpc32xx_eth_device->phy_rmii)
463 writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, ®s->command);
464 else
465 writel(COMMAND_PASSRUNTFRAME, ®s->command);
466
467 /* Configure Full/Half Duplex mode */
468 if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
469 setbits_le32(®s->mac2, MAC2_FULL_DUPLEX);
470 setbits_le32(®s->command, COMMAND_FULL_DUPLEX);
471 writel(0x15, ®s->ipgt);
472 } else {
473 writel(0x12, ®s->ipgt);
474 }
475
476 /* Configure 100MBit/10MBit mode */
477 if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
478 writel(SUPP_SPEED, ®s->supp);
479 else
480 writel(0, ®s->supp);
481
482 /* Save station address */
483 writel((unsigned long) (dev->enetaddr[0] |
484 (dev->enetaddr[1] << 8)), ®s->sa2);
485 writel((unsigned long) (dev->enetaddr[2] |
486 (dev->enetaddr[3] << 8)), ®s->sa1);
487 writel((unsigned long) (dev->enetaddr[4] |
488 (dev->enetaddr[5] << 8)), ®s->sa0);
489
490 /* set up transmit buffers */
491 for (index = 0; index < TX_BUF_COUNT; index++) {
492 bufs->tx_desc[index].control = 0;
493 bufs->tx_stat[index].statusinfo = 0;
494 }
495 writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor);
496 writel((u32)(&bufs->tx_stat), ®s->txstatus);
497 writel(TX_BUF_COUNT-1, ®s->txdescriptornumber);
498
499 /* set up receive buffers */
500 for (index = 0; index < RX_BUF_COUNT; index++) {
501 bufs->rx_desc[index].packet =
502 (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
503 bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
504 bufs->rx_stat[index].statusinfo = 0;
505 bufs->rx_stat[index].statushashcrc = 0;
506 }
507 writel((u32)(&bufs->rx_desc), ®s->rxdescriptor);
508 writel((u32)(&bufs->rx_stat), ®s->rxstatus);
509 writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber);
510
511 /* Enable broadcast and matching address packets */
512 writel(RXFILTERCTRL_ACCEPTBROADCAST |
513 RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl);
514
515 /* Clear and disable interrupts */
516 writel(0xFFFF, ®s->intclear);
517 writel(0, ®s->intenable);
518
519 /* Enable receive and transmit mode of MAC ethernet core */
520 setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
521 setbits_le32(®s->mac1, MAC1_RECV_ENABLE);
522
523 /*
524 * Perform a 'dummy' first send to work around Ethernet.1
525 * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
526 * Use zeroed "index" variable as the dummy.
527 */
528
529 index = 0;
530 lpc32xx_eth_send(dev, &index, 4);
531
532 return 0;
533 }
534
lpc32xx_eth_halt(struct eth_device * dev)535 static int lpc32xx_eth_halt(struct eth_device *dev)
536 {
537 struct lpc32xx_eth_device *lpc32xx_eth_device =
538 container_of(dev, struct lpc32xx_eth_device, dev);
539 struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
540
541 /* Reset all MAC logic */
542 writel(MAC1_RESETS, ®s->mac1);
543 writel(COMMAND_RESETS, ®s->command);
544 /* Let reset condition settle */
545 udelay(2000);
546
547 return 0;
548 }
549
550 #if defined(CONFIG_PHYLIB)
lpc32xx_eth_phylib_init(struct eth_device * dev,int phyid)551 int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
552 {
553 struct lpc32xx_eth_device *lpc32xx_eth_device =
554 container_of(dev, struct lpc32xx_eth_device, dev);
555 struct mii_dev *bus;
556 struct phy_device *phydev;
557 int ret;
558
559 bus = mdio_alloc();
560 if (!bus) {
561 printf("mdio_alloc failed\n");
562 return -ENOMEM;
563 }
564 bus->read = mii_reg_read;
565 bus->write = mii_reg_write;
566 strcpy(bus->name, dev->name);
567
568 ret = mdio_register(bus);
569 if (ret) {
570 printf("mdio_register failed\n");
571 free(bus);
572 return -ENOMEM;
573 }
574
575 if (lpc32xx_eth_device->phy_rmii)
576 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
577 else
578 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
579
580 if (!phydev) {
581 printf("phy_connect failed\n");
582 return -ENODEV;
583 }
584
585 phy_config(phydev);
586 phy_startup(phydev);
587
588 return 0;
589 }
590 #endif
591
lpc32xx_eth_initialize(bd_t * bis)592 int lpc32xx_eth_initialize(bd_t *bis)
593 {
594 struct eth_device *dev = &lpc32xx_eth.dev;
595 struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
596
597 /*
598 * Set RMII management clock rate. With HCLK at 104 MHz and
599 * a divider of 28, this will be 3.72 MHz.
600 */
601 writel(MCFG_RESET_MII_MGMT, ®s->mcfg);
602 writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg);
603
604 /* Reset all MAC logic */
605 writel(MAC1_RESETS, ®s->mac1);
606 writel(COMMAND_RESETS, ®s->command);
607
608 /* wait 10 ms for the whole I/F to reset */
609 udelay(10000);
610
611 /* must be less than sizeof(dev->name) */
612 strcpy(dev->name, "eth0");
613
614 dev->init = (void *)lpc32xx_eth_init;
615 dev->halt = (void *)lpc32xx_eth_halt;
616 dev->send = (void *)lpc32xx_eth_send;
617 dev->recv = (void *)lpc32xx_eth_recv;
618 dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
619
620 /* Release SOFT reset to let MII talk to PHY */
621 clrbits_le32(®s->mac1, MAC1_SOFT_RESET);
622
623 /* register driver before talking to phy */
624 eth_register(dev);
625
626 #if defined(CONFIG_PHYLIB)
627 lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
628 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
629 int retval;
630 struct mii_dev *mdiodev = mdio_alloc();
631 if (!mdiodev)
632 return -ENOMEM;
633 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
634 mdiodev->read = mii_reg_read;
635 mdiodev->write = mii_reg_write;
636
637 retval = mdio_register(mdiodev);
638 if (retval < 0)
639 return retval;
640 #endif
641
642 return 0;
643 }
644