include/asm/immap_86xx.h

297 	uint	fifo_tx_thr;	/* 0x2408c - FIFO transmit threshold register */
299 	uint	fifo_tx_starve;	/* 0x24098 - FIFO transmit starve register */
300 	uint	fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
305 	uint	tctrl;		/* 0x24100 - Transmit Control Register */
306 	uint	tstat;		/* 0x24104 - Transmit Status Register */
309 	uint    txic;		/* 0x24110 - Transmit interrupt coalescing Register */
310 	uint    tqueue;         /* 0x24114 - Transmit Queue Control Register */
315 	uint	tbdbph;	        /* 0x2417c - Transmit Data Buffer Pointer High Register */
317 	uint    tbptr0;         /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
319 	uint    tbptr1;         /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
321 	uint    tbptr2;         /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
323 	uint    tbptr3;         /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
325 	uint    tbptr4;         /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
327 	uint    tbptr5;         /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
329 	uint    tbptr6;         /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
331 	uint    tbptr7;         /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
333 	uint	tbaseh;		/* 0x24200 - Transmit Descriptor Base Address High Register */
334 	uint	tbase0;		/* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
336 	uint    tbase1;         /* 0x2420C - Transmit Descriptor base address of Ring 1 */
338 	uint    tbase2;         /* 0x24214 - Transmit Descriptor base address of Ring 2 */
340 	uint    tbase3;         /* 0x2421C - Transmit Descriptor base address of Ring 3 */
342 	uint    tbase4;         /* 0x24224 - Transmit Descriptor base address of Ring 4 */
344 	uint    tbase5;         /* 0x2422C - Transmit Descriptor base address of Ring 5 */
346 	uint    tbase6;         /* 0x24234 - Transmit Descriptor base address of Ring 6 */
348 	uint    tbase7;         /* 0x2423C - Transmit Descriptor base address of Ring 7 */
444 	uint	tr64;		/* 0x24680 - Transmit and Receive 64-byte Frame Counter */
445 	uint	tr127;		/* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
446 	uint	tr255;		/* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
447 	uint	tr511;		/* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
448 	uint	tr1k;		/* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
449 	uint	trmax;		/* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
450 	uint	trmgv;		/* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
468 	uint	tbyt;		/* 0x246e0 - Transmit Byte Counter Counter */
469 	uint	tpkt;		/* 0x246e4 - Transmit Packet Counter */
470 	uint	tmca;		/* 0x246e8 - Transmit Multicast Packet Counter */
471 	uint	tbca;		/* 0x246ec - Transmit Broadcast Packet Counter */
472 	uint	txpf;		/* 0x246f0 - Transmit Pause Control Frame Counter */
473 	uint	tdfr;		/* 0x246f4 - Transmit Deferral Packet Counter */
474 	uint	tedf;		/* 0x246f8 - Transmit Excessive Deferral Packet Counter */
475 	uint	tscl;		/* 0x246fc - Transmit Single Collision Packet Counter */
476 	uint	tmcl;		/* 0x24700 - Transmit Multiple Collision Packet Counter */
477 	uint	tlcl;		/* 0x24704 - Transmit Late Collision Packet Counter */
478 	uint	txcl;		/* 0x24708 - Transmit Excessive Collision Packet Counter */
479 	uint	tncl;		/* 0x2470c - Transmit Total Collision Counter */
481 	uint	tdrp;		/* 0x24714 - Transmit Drop Frame Counter */
482 	uint	tjbr;		/* 0x24718 - Transmit Jabber Frame Counter */
483 	uint	tfcs;		/* 0x2471c - Transmit FCS Error Counter */
484 	uint	txcf;		/* 0x24720 - Transmit Control Frame Counter */
485 	uint	tovr;		/* 0x24724 - Transmit Oversize Frame Counter */
486 	uint	tund;		/* 0x24728 - Transmit Undersize Frame Counter */
487 	uint	tfrg;		/* 0x2472c - Transmit Fragments Frame Counter */