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/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610.c110 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, in ddrmc_ctrl_init_ddr3() argument
120 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
121 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
123 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
124 writel(DDRMC_CR12_WRLAT(timings->wrlat) | in ddrmc_ctrl_init_ddr3()
125 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
126 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) | in ddrmc_ctrl_init_ddr3()
127 DDRMC_CR13_TCCD(timings->tccd) | in ddrmc_ctrl_init_ddr3()
128 DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval), in ddrmc_ctrl_init_ddr3()
130 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | in ddrmc_ctrl_init_ddr3()
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/openbmc/u-boot/board/overo/
H A Dspl.c22 * so we have to setup the DDR timings ourself on both banks.
24 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
26 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
29 timings->mcfg = MICRON_V_MCFG_165(256 << 20); in get_board_mem_timings()
30 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
31 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
32 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
36 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
37 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
38 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
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/openbmc/u-boot/board/isee/igep00x0/
H A Dspl.c13 * so we have to setup the DDR timings ourself on both banks.
15 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
19 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
23 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
24 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
25 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
28 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
29 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
30 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
36 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
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/openbmc/linux/include/media/
H A Dv4l2-dv-timings.h3 * v4l2-dv-timings - Internal header with dv-timings helper functions
16 * @t: Timings for the video mode.
30 * typedef v4l2_check_dv_timings_fnc - timings check callback
35 * Returns true if the given timings are valid.
40 * v4l2_valid_dv_timings() - are these timings valid?
58 * timings based on capabilities
66 * timings, filtering out any timings that are not supported based on the
78 * v4l2_find_dv_timings_cap() - Find the closest timings struct
84 * @fnc: callback to check if a given timings struct is OK. May be NULL.
87 * This function tries to map the given timings to an entry in the
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/openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_wp.c145 struct omap_video_timings *timings) in hdmi_wp_video_config_interface() argument
151 vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; in hdmi_wp_video_config_interface()
152 hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; in hdmi_wp_video_config_interface()
157 r = FLD_MOD(r, timings->interlace, 3, 3); in hdmi_wp_video_config_interface()
163 struct omap_video_timings *timings) in hdmi_wp_video_config_timing() argument
170 timing_h |= FLD_VAL(timings->hbp, 31, 20); in hdmi_wp_video_config_timing()
171 timing_h |= FLD_VAL(timings->hfp, 19, 8); in hdmi_wp_video_config_timing()
172 timing_h |= FLD_VAL(timings->hsw, 7, 0); in hdmi_wp_video_config_timing()
175 timing_v |= FLD_VAL(timings->vbp, 31, 20); in hdmi_wp_video_config_timing()
176 timing_v |= FLD_VAL(timings->vfp, 19, 8); in hdmi_wp_video_config_timing()
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/openbmc/u-boot/board/sunxi/
H A Ddram_timings_sun4i.h4 # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
10 # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
16 # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
22 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
28 # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
34 # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
40 # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
46 # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
52 # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
58 # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
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/openbmc/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst23 GPMC has certain timings that has to be programmed for proper
25 timings. To have peripheral work with gpmc, peripheral timings has to
28 dependency for certain gpmc timings on gpmc clock frequency. Hence a
31 Generic routine provides a generic method to calculate gpmc timings
32 from gpmc peripheral timings. struct gpmc_device_timings fields has to
33 be updated with timings from the datasheet of the peripheral that is
34 connected to gpmc. A few of the peripheral timings can be fed either
49 on understanding of gpmc timings, peripheral timings, available
54 gpmc timing dependency on peripheral timings:
172 Many of gpmc timings are dependent on other gpmc timings (a few
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/openbmc/qemu/hw/display/
H A Dedid-generate.c19 /* dea/dta extension timings (all @ 50 Hz) */
27 /* dea/dta extension timings (all @ 60 Hz) */
30 /* additional standard timings 3 (all @ 60Hz) */
45 /* established timings (all @ 60Hz) */
51 typedef struct Timings { struct
61 } Timings; argument
63 static void generate_timings(Timings *timings, uint32_t refresh_rate, in generate_timings() argument
66 /* pull some realistic looking timings out of thin air */ in generate_timings()
67 timings->xfront = xres * 25 / 100; in generate_timings()
68 timings->xsync = xres * 3 / 100; in generate_timings()
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/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Ddv-timings.rst3 .. _dv-timings:
6 Digital Video (DV) Timings
10 and the corresponding video timings. Today there are many more different
13 extend the API to select the video timings for these interfaces. Since
16 set/get video timings at the input and output.
18 These ioctls deal with the detailed digital video timings that define
21 widths etc. The ``linux/v4l2-dv-timings.h`` header can be used to get
22 the timings of the formats in the :ref:`cea861` and :ref:`vesadmt`
25 To enumerate and query the attributes of the DV timings supported by a
29 DV timings for the device applications use the
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H A Dvidioc-query-dv-timings.rst38 The hardware may be able to detect the current DV timings automatically,
42 the timings, it will fill in the timings structure.
46 Drivers shall *not* switch timings automatically if new
47 timings are detected. Instead, drivers should send the
50 The reason is that new timings usually mean different buffer sizes as
53 :ref:`VIDIOC_QUERY_DV_TIMINGS`, and if the detected timings are valid they
54 will have to stop streaming, set the new timings, allocate new buffers
57 If the timings could not be detected because there was no signal, then
62 capabilities), then the driver fills in whatever timings it could find
65 found timings with the hardware's capabilities in order to give more
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H A Dvidioc-enum-dv-timings.rst13 VIDIOC_ENUM_DV_TIMINGS - VIDIOC_SUBDEV_ENUM_DV_TIMINGS - Enumerate supported Digital Video timings
38 While some DV receivers or transmitters support a wide range of timings,
39 others support only a limited number of timings. With this ioctl
40 applications can enumerate a list of known supported timings. Call
42 also supports other standards or even custom timings that are not in
45 To query the available timings, applications initialize the ``index``
51 DV timings, applications shall begin at index zero, incrementing by one
56 Drivers may enumerate a different set of DV timings after
59 When implemented by the driver DV timings of subdevices can be queried
61 subdevice node. The DV timings are specific to inputs (for DV receivers)
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H A Dvidioc-g-dv-timings.rst13 … VIDIOC_SUBDEV_G_DV_TIMINGS - VIDIOC_SUBDEV_S_DV_TIMINGS - Get or set DV timings for input or outp…
46 To set DV timings for the input or output, applications use the
47 :ref:`VIDIOC_S_DV_TIMINGS <VIDIOC_G_DV_TIMINGS>` ioctl and to get the current timings,
59 The ``linux/v4l2-dv-timings.h`` header can be used to get the timings of
61 the current input or output does not support DV timings (e.g. if
77 Digital video timings are not supported for this input or output.
80 The device is busy and therefore can not change the timings.
187 - Type of DV timings as listed in :ref:`dv-timing-types`.
192 - Timings defined by BT.656/1120 specifications
216 - BT.656/1120 timings
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/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c98 * - Takes CS and associated timings and initalize SDRAM
102 struct board_sdrc_timings *timings) in write_sdrc_timings() argument
104 /* Setup timings we got from the board. */ in write_sdrc_timings()
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
106 writel(timings->ctrla, &sdrc_actim_base->ctrla); in write_sdrc_timings()
107 writel(timings->ctrlb, &sdrc_actim_base->ctrlb); in write_sdrc_timings()
108 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
113 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
132 struct board_sdrc_timings timings; in do_sdrc_init() local
137 /* set some default timings */ in do_sdrc_init()
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/openbmc/linux/Documentation/fb/
H A Dviafb.modes31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
117 geometry 640 480 640 480 32 timings 19081 104 40 31 1 64 3 endmode
138 geometry 720 480 720 480 32 timings 37202 88 16 14 1 72 3 endmode
159 geometry 800 480 800 480 32 timings 33805 96 24 10 3 72 7 endmode
180 geometry 720 576 720 576 32 timings 30611 96 24 17 1 72 3 endmode
202 timings 25000 88 40 23 1 128 4 hsync high vsync high endmode
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/openbmc/linux/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c13 #include <media/v4l2-dv-timings.h>
16 #include <uapi/linux/v4l2-dv-timings.h>
48 struct v4l2_dv_timings timings; member
96 fmt->field = hdmi->timings.bt.interlaced ? in adv748x_hdmi_fill_format()
102 fmt->width = hdmi->timings.bt.width; in adv748x_hdmi_fill_format()
103 fmt->height = hdmi->timings.bt.height; in adv748x_hdmi_fill_format()
109 static void adv748x_fill_optional_dv_timings(struct v4l2_dv_timings *timings) in adv748x_fill_optional_dv_timings() argument
111 v4l2_find_dv_timings_cap(timings, &adv748x_hdmi_timings_cap, in adv748x_fill_optional_dv_timings()
172 const struct v4l2_dv_timings *timings) in adv748x_hdmi_set_video_timings() argument
179 if (v4l2_match_dv_timings(timings, &stds[i].timings, 250000, in adv748x_hdmi_set_video_timings()
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/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_timings.c26 .timings.mode = 0,
27 .timings.sdr = {
71 .timings.mode = 1,
72 .timings.sdr = {
116 .timings.mode = 2,
117 .timings.sdr = {
161 .timings.mode = 3,
162 .timings.sdr = {
206 .timings.mode = 4,
207 .timings.sdr = {
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/openbmc/linux/drivers/memory/tegra/
H A Dtegra210-emc-table.c16 struct tegra210_emc_timing *timings; in tegra210_emc_table_device_init() local
19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init()
20 if (!timings) { in tegra210_emc_table_device_init()
26 if (timings[i].revision == 0) in tegra210_emc_table_device_init()
42 memunmap(timings); in tegra210_emc_table_device_init()
46 emc->derated = timings; in tegra210_emc_table_device_init()
49 emc->nominal = timings; in tegra210_emc_table_device_init()
54 rmem->priv = timings; in tegra210_emc_table_device_init()
62 struct tegra210_emc_timing *timings = rmem->priv; in tegra210_emc_table_device_release() local
65 if ((emc->nominal && timings != emc->nominal) && in tegra210_emc_table_device_release()
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/openbmc/linux/drivers/video/fbdev/omap2/omapfb/displays/
H A Dencoder-tfp410.c26 struct omap_video_timings timings; member
83 in->ops.dpi->set_timings(in, &ddata->timings); in tfp410_enable()
115 static void tfp410_fix_timings(struct omap_video_timings *timings) in tfp410_fix_timings() argument
117 timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; in tfp410_fix_timings()
118 timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; in tfp410_fix_timings()
119 timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH; in tfp410_fix_timings()
123 struct omap_video_timings *timings) in tfp410_set_timings() argument
128 tfp410_fix_timings(timings); in tfp410_set_timings()
130 ddata->timings = *timings; in tfp410_set_timings()
131 dssdev->panel.timings = *timings; in tfp410_set_timings()
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H A Dconnector-analog-tv.c22 struct omap_video_timings timings; member
85 in->ops.atv->set_timings(in, &ddata->timings); in tvc_enable()
119 struct omap_video_timings *timings) in tvc_set_timings() argument
124 ddata->timings = *timings; in tvc_set_timings()
125 dssdev->panel.timings = *timings; in tvc_set_timings()
127 in->ops.atv->set_timings(in, timings); in tvc_set_timings()
131 struct omap_video_timings *timings) in tvc_get_timings() argument
135 *timings = ddata->timings; in tvc_get_timings()
139 struct omap_video_timings *timings) in tvc_check_timings() argument
144 return in->ops.atv->check_timings(in, timings); in tvc_check_timings()
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/openbmc/u-boot/drivers/video/
H A Dmali_dp.c159 struct display_timing *timings) in malidp_setup_timings() argument
161 u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) | in malidp_setup_timings()
162 MALIDP_V_SYNCWIDTH(timings->vsync_len.typ); in malidp_setup_timings()
165 val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) | in malidp_setup_timings()
166 MALIDP_H_FRONTPORCH(timings->hfront_porch.typ); in malidp_setup_timings()
169 val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) | in malidp_setup_timings()
170 MALIDP_V_FRONTPORCH(timings->vfront_porch.typ); in malidp_setup_timings()
173 val = MALIDP_H_ACTIVE(timings->hactive.typ) | in malidp_setup_timings()
174 MALIDP_V_ACTIVE(timings->vactive.typ); in malidp_setup_timings()
183 struct display_timing *timings) in malidp_setup_mode() argument
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/openbmc/linux/drivers/video/fbdev/core/
H A Dfbmon.c224 printk("fbmon: trying to fix monitor timings\n"); in fix_edid()
639 DPRINTK(" Detailed Timings\n"); in fb_create_modedb()
656 DPRINTK(" Standard Timings\n"); in fb_create_modedb()
1148 static void fb_timings_vfreq(struct __fb_timings *timings) in fb_timings_vfreq() argument
1150 timings->hfreq = fb_get_hfreq(timings->vfreq, timings->vactive); in fb_timings_vfreq()
1151 timings->vblank = fb_get_vblank(timings->hfreq); in fb_timings_vfreq()
1152 timings->vtotal = timings->vactive + timings->vblank; in fb_timings_vfreq()
1153 timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq, in fb_timings_vfreq()
1154 timings->hactive); in fb_timings_vfreq()
1155 timings->htotal = timings->hactive + timings->hblank; in fb_timings_vfreq()
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/openbmc/linux/drivers/media/rc/
H A Drc-ir-raw.c303 * @timings: Manchester modulation timings.
308 * modulation with the timing characteristics described by @timings, writing up
317 const struct ir_raw_timings_manchester *timings, in ir_raw_gen_manchester() argument
326 if (timings->leader_pulse) { in ir_raw_gen_manchester()
329 init_ir_raw_event_duration((*ev), 1, timings->leader_pulse); in ir_raw_gen_manchester()
330 if (timings->leader_space) { in ir_raw_gen_manchester()
334 timings->leader_space); in ir_raw_gen_manchester()
344 if (timings->invert) in ir_raw_gen_manchester()
347 (*ev)->duration += timings->clock; in ir_raw_gen_manchester()
352 timings->clock); in ir_raw_gen_manchester()
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/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.c143 * so we have to setup the DDR timings ourself on both banks.
145 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
151 * we know what timings to use. If we can't identify it then in get_board_mem_timings()
156 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
161 timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); in get_board_mem_timings()
162 timings->ctrla = NUMONYX_V_ACTIMA_165; in get_board_mem_timings()
163 timings->ctrlb = NUMONYX_V_ACTIMB_165; in get_board_mem_timings()
164 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
168 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
169 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
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/openbmc/linux/drivers/media/spi/
H A Dgs1662.c23 #include <media/v4l2-dv-timings.h>
24 #include <linux/v4l2-dv-timings.h>
113 /* Implement following timings before enable it.
114 * Because of we don't have access to these theoretical timings yet.
229 static int gs_status_format(u16 status, struct v4l2_dv_timings *timings) in gs_status_format() argument
236 *timings = reg_fmt[i].format; in gs_status_format()
244 static u16 get_register_timings(struct v4l2_dv_timings *timings) in get_register_timings() argument
249 if (v4l2_match_dv_timings(timings, &reg_fmt[i].format, 0, in get_register_timings()
263 struct v4l2_dv_timings *timings) in gs_s_dv_timings() argument
268 reg_value = get_register_timings(timings); in gs_s_dv_timings()
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/openbmc/u-boot/board/corscience/tricorder/
H A Dtricorder.c159 * so we have to setup the DDR timings ourself on the first bank. This
163 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
170 /* use optimized timings for our SDRAM device */ in get_board_mem_timings()
171 timings->mcfg = MCFG((256 << 20), 14); in get_board_mem_timings()
181 timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC, in get_board_mem_timings()
191 timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE, in get_board_mem_timings()
194 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
195 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
197 /* use conservative beagleboard timings as default */ in get_board_mem_timings()
198 timings->mcfg = MICRON_V_MCFG_165(128 << 20); in get_board_mem_timings()
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