98  *  - Takes CS and associated timings and initalize SDRAM
102 			struct board_sdrc_timings *timings)  in write_sdrc_timings()  argument
104 	/* Setup timings we got from the board. */  in write_sdrc_timings()
105 	writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);  in write_sdrc_timings()
106 	writel(timings->ctrla, &sdrc_actim_base->ctrla);  in write_sdrc_timings()
107 	writel(timings->ctrlb, &sdrc_actim_base->ctrlb);  in write_sdrc_timings()
108 	writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);  in write_sdrc_timings()
113 	writel(timings->mr, &sdrc_base->cs[cs].mr);  in write_sdrc_timings()
132 	struct board_sdrc_timings timings;  in do_sdrc_init()  local
137 	/* set some default timings */  in do_sdrc_init()
138 	timings.sharing = SDRC_SHARING;  in do_sdrc_init()
142 	 * need to set all of the timings.  This ends up being board  in do_sdrc_init()
150 	/* set/modify board-specific timings */  in do_sdrc_init()
151 	get_board_mem_timings(&timings);  in do_sdrc_init()
161 		writel(timings.sharing, &sdrc_base->sharing);  in do_sdrc_init()
170 		write_sdrc_timings(CS0, sdrc_actim_base0, &timings);  in do_sdrc_init()
172 		write_sdrc_timings(CS1, sdrc_actim_base1, &timings);  in do_sdrc_init()
184 		timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),  in do_sdrc_init()
185 		timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);  in do_sdrc_init()
186 		timings.ctrla = readl(&sdrc_actim_base0->ctrla);  in do_sdrc_init()
187 		timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);  in do_sdrc_init()
188 		timings.mr = readl(&sdrc_base->cs[CS0].mr);  in do_sdrc_init()
189 		write_sdrc_timings(cs, sdrc_actim_base1, &timings);  in do_sdrc_init()