Lines Matching full:timings
13 * so we have to setup the DDR timings ourself on both banks.
15 void get_board_mem_timings(struct board_sdrc_timings *timings) in get_board_mem_timings() argument
19 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
23 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); in get_board_mem_timings()
24 timings->ctrla = HYNIX_V_ACTIMA_200; in get_board_mem_timings()
25 timings->ctrlb = HYNIX_V_ACTIMB_200; in get_board_mem_timings()
28 timings->mcfg = MICRON_V_MCFG_200(256 << 20); in get_board_mem_timings()
29 timings->ctrla = MICRON_V_ACTIMA_200; in get_board_mem_timings()
30 timings->ctrlb = MICRON_V_ACTIMB_200; in get_board_mem_timings()
36 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()
40 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); in get_board_mem_timings()
41 timings->ctrla = NUMONYX_V_ACTIMA_165; in get_board_mem_timings()
42 timings->ctrlb = NUMONYX_V_ACTIMB_165; in get_board_mem_timings()
43 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
45 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); in get_board_mem_timings()
46 timings->ctrla = NUMONYX_V_ACTIMA_200; in get_board_mem_timings()
47 timings->ctrlb = NUMONYX_V_ACTIMB_200; in get_board_mem_timings()
48 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; in get_board_mem_timings()