183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2552a848eSStefano Babic /*
3552a848eSStefano Babic * Copyright 2015 Toradex, Inc.
4552a848eSStefano Babic *
5552a848eSStefano Babic * Based on vf610twr:
6552a848eSStefano Babic * Copyright 2013 Freescale Semiconductor, Inc.
7552a848eSStefano Babic */
8552a848eSStefano Babic
9552a848eSStefano Babic #include <asm/io.h>
10552a848eSStefano Babic #include <asm/arch/imx-regs.h>
11552a848eSStefano Babic #include <asm/arch/iomux-vf610.h>
12552a848eSStefano Babic #include <asm/arch/ddrmc-vf610.h>
13*dc619924SLukasz Majewski #include "ddrmc-vf610-calibration.h"
14552a848eSStefano Babic
ddrmc_setup_iomux(const iomux_v3_cfg_t * pads,int pads_count)15552a848eSStefano Babic void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
16552a848eSStefano Babic {
17552a848eSStefano Babic static const iomux_v3_cfg_t default_pads[] = {
18552a848eSStefano Babic VF610_PAD_DDR_A15__DDR_A_15,
19552a848eSStefano Babic VF610_PAD_DDR_A14__DDR_A_14,
20552a848eSStefano Babic VF610_PAD_DDR_A13__DDR_A_13,
21552a848eSStefano Babic VF610_PAD_DDR_A12__DDR_A_12,
22552a848eSStefano Babic VF610_PAD_DDR_A11__DDR_A_11,
23552a848eSStefano Babic VF610_PAD_DDR_A10__DDR_A_10,
24552a848eSStefano Babic VF610_PAD_DDR_A9__DDR_A_9,
25552a848eSStefano Babic VF610_PAD_DDR_A8__DDR_A_8,
26552a848eSStefano Babic VF610_PAD_DDR_A7__DDR_A_7,
27552a848eSStefano Babic VF610_PAD_DDR_A6__DDR_A_6,
28552a848eSStefano Babic VF610_PAD_DDR_A5__DDR_A_5,
29552a848eSStefano Babic VF610_PAD_DDR_A4__DDR_A_4,
30552a848eSStefano Babic VF610_PAD_DDR_A3__DDR_A_3,
31552a848eSStefano Babic VF610_PAD_DDR_A2__DDR_A_2,
32552a848eSStefano Babic VF610_PAD_DDR_A1__DDR_A_1,
33552a848eSStefano Babic VF610_PAD_DDR_A0__DDR_A_0,
34552a848eSStefano Babic VF610_PAD_DDR_BA2__DDR_BA_2,
35552a848eSStefano Babic VF610_PAD_DDR_BA1__DDR_BA_1,
36552a848eSStefano Babic VF610_PAD_DDR_BA0__DDR_BA_0,
37552a848eSStefano Babic VF610_PAD_DDR_CAS__DDR_CAS_B,
38552a848eSStefano Babic VF610_PAD_DDR_CKE__DDR_CKE_0,
39552a848eSStefano Babic VF610_PAD_DDR_CLK__DDR_CLK_0,
40552a848eSStefano Babic VF610_PAD_DDR_CS__DDR_CS_B_0,
41552a848eSStefano Babic VF610_PAD_DDR_D15__DDR_D_15,
42552a848eSStefano Babic VF610_PAD_DDR_D14__DDR_D_14,
43552a848eSStefano Babic VF610_PAD_DDR_D13__DDR_D_13,
44552a848eSStefano Babic VF610_PAD_DDR_D12__DDR_D_12,
45552a848eSStefano Babic VF610_PAD_DDR_D11__DDR_D_11,
46552a848eSStefano Babic VF610_PAD_DDR_D10__DDR_D_10,
47552a848eSStefano Babic VF610_PAD_DDR_D9__DDR_D_9,
48552a848eSStefano Babic VF610_PAD_DDR_D8__DDR_D_8,
49552a848eSStefano Babic VF610_PAD_DDR_D7__DDR_D_7,
50552a848eSStefano Babic VF610_PAD_DDR_D6__DDR_D_6,
51552a848eSStefano Babic VF610_PAD_DDR_D5__DDR_D_5,
52552a848eSStefano Babic VF610_PAD_DDR_D4__DDR_D_4,
53552a848eSStefano Babic VF610_PAD_DDR_D3__DDR_D_3,
54552a848eSStefano Babic VF610_PAD_DDR_D2__DDR_D_2,
55552a848eSStefano Babic VF610_PAD_DDR_D1__DDR_D_1,
56552a848eSStefano Babic VF610_PAD_DDR_D0__DDR_D_0,
57552a848eSStefano Babic VF610_PAD_DDR_DQM1__DDR_DQM_1,
58552a848eSStefano Babic VF610_PAD_DDR_DQM0__DDR_DQM_0,
59552a848eSStefano Babic VF610_PAD_DDR_DQS1__DDR_DQS_1,
60552a848eSStefano Babic VF610_PAD_DDR_DQS0__DDR_DQS_0,
61552a848eSStefano Babic VF610_PAD_DDR_RAS__DDR_RAS_B,
62552a848eSStefano Babic VF610_PAD_DDR_WE__DDR_WE_B,
63552a848eSStefano Babic VF610_PAD_DDR_ODT1__DDR_ODT_0,
64552a848eSStefano Babic VF610_PAD_DDR_ODT0__DDR_ODT_1,
65a95d4440SStefan Agner VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
66a95d4440SStefan Agner VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
67552a848eSStefano Babic VF610_PAD_DDR_RESETB,
68552a848eSStefano Babic };
69552a848eSStefano Babic
70552a848eSStefano Babic if ((pads == NULL) || (pads_count == 0)) {
71552a848eSStefano Babic pads = default_pads;
72552a848eSStefano Babic pads_count = ARRAY_SIZE(default_pads);
73552a848eSStefano Babic }
74552a848eSStefano Babic
75552a848eSStefano Babic imx_iomux_v3_setup_multiple_pads(pads, pads_count);
76552a848eSStefano Babic }
77552a848eSStefano Babic
78552a848eSStefano Babic static struct ddrmc_phy_setting default_phy_settings[] = {
79552a848eSStefano Babic { DDRMC_PHY_DQ_TIMING, 0 },
80552a848eSStefano Babic { DDRMC_PHY_DQ_TIMING, 16 },
81552a848eSStefano Babic { DDRMC_PHY_DQ_TIMING, 32 },
82552a848eSStefano Babic
83552a848eSStefano Babic { DDRMC_PHY_DQS_TIMING, 1 },
84552a848eSStefano Babic { DDRMC_PHY_DQS_TIMING, 17 },
85552a848eSStefano Babic
86552a848eSStefano Babic { DDRMC_PHY_CTRL, 2 },
87552a848eSStefano Babic { DDRMC_PHY_CTRL, 18 },
88552a848eSStefano Babic { DDRMC_PHY_CTRL, 34 },
89552a848eSStefano Babic
90552a848eSStefano Babic { DDRMC_PHY_MASTER_CTRL, 3 },
91552a848eSStefano Babic { DDRMC_PHY_MASTER_CTRL, 19 },
92552a848eSStefano Babic { DDRMC_PHY_MASTER_CTRL, 35 },
93552a848eSStefano Babic
94552a848eSStefano Babic { DDRMC_PHY_SLAVE_CTRL, 4 },
95552a848eSStefano Babic { DDRMC_PHY_SLAVE_CTRL, 20 },
96552a848eSStefano Babic { DDRMC_PHY_SLAVE_CTRL, 36 },
97552a848eSStefano Babic
98552a848eSStefano Babic /* LPDDR2 only parameter */
99552a848eSStefano Babic { DDRMC_PHY_OFF, 49 },
100552a848eSStefano Babic
101552a848eSStefano Babic { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
102552a848eSStefano Babic
103552a848eSStefano Babic /* Processor Pad ODT settings */
104552a848eSStefano Babic { DDRMC_PHY_PROC_PAD_ODT, 52 },
105552a848eSStefano Babic
106552a848eSStefano Babic /* end marker */
107552a848eSStefano Babic { 0, -1 }
108552a848eSStefano Babic };
109552a848eSStefano Babic
ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const * timings,struct ddrmc_cr_setting * board_cr_settings,struct ddrmc_phy_setting * board_phy_settings,int col_diff,int row_diff)110552a848eSStefano Babic void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
111552a848eSStefano Babic struct ddrmc_cr_setting *board_cr_settings,
112552a848eSStefano Babic struct ddrmc_phy_setting *board_phy_settings,
113552a848eSStefano Babic int col_diff, int row_diff)
114552a848eSStefano Babic {
115552a848eSStefano Babic struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
116552a848eSStefano Babic struct ddrmc_cr_setting *cr_setting;
117552a848eSStefano Babic struct ddrmc_phy_setting *phy_setting;
118552a848eSStefano Babic
119552a848eSStefano Babic writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
120552a848eSStefano Babic writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
121552a848eSStefano Babic writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
122552a848eSStefano Babic
123552a848eSStefano Babic writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
124552a848eSStefano Babic writel(DDRMC_CR12_WRLAT(timings->wrlat) |
125552a848eSStefano Babic DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
126552a848eSStefano Babic writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
127552a848eSStefano Babic DDRMC_CR13_TCCD(timings->tccd) |
128552a848eSStefano Babic DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
129552a848eSStefano Babic &ddrmr->cr[13]);
130552a848eSStefano Babic writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
131552a848eSStefano Babic DDRMC_CR14_TWTR(timings->twtr) |
132552a848eSStefano Babic DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
133552a848eSStefano Babic writel(DDRMC_CR16_TMRD(timings->tmrd) |
134552a848eSStefano Babic DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
135552a848eSStefano Babic writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
136552a848eSStefano Babic DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
137552a848eSStefano Babic writel(DDRMC_CR18_TCKESR(timings->tckesr) |
138552a848eSStefano Babic DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
139552a848eSStefano Babic
140552a848eSStefano Babic writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
141552a848eSStefano Babic writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
142552a848eSStefano Babic DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
143552a848eSStefano Babic &ddrmr->cr[21]);
144552a848eSStefano Babic
145552a848eSStefano Babic writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
146552a848eSStefano Babic writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
147552a848eSStefano Babic DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
148552a848eSStefano Babic writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
149552a848eSStefano Babic
150552a848eSStefano Babic writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
151552a848eSStefano Babic writel(DDRMC_CR26_TREF(timings->tref) |
152552a848eSStefano Babic DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
153552a848eSStefano Babic writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
154552a848eSStefano Babic writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
155552a848eSStefano Babic
156552a848eSStefano Babic writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
157552a848eSStefano Babic writel(DDRMC_CR31_TXSNR(timings->txsnr) |
158552a848eSStefano Babic DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
159552a848eSStefano Babic writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
160552a848eSStefano Babic writel(DDRMC_CR34_CKSRX(timings->cksrx) |
161552a848eSStefano Babic DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
162552a848eSStefano Babic
163552a848eSStefano Babic writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
164552a848eSStefano Babic writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
165552a848eSStefano Babic DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
166552a848eSStefano Babic
167552a848eSStefano Babic writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
168552a848eSStefano Babic writel(DDRMC_CR48_MR1_DA_0(70) |
169552a848eSStefano Babic DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
170552a848eSStefano Babic
171552a848eSStefano Babic writel(DDRMC_CR66_ZQCL(timings->zqcl) |
172552a848eSStefano Babic DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
173552a848eSStefano Babic writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
174552a848eSStefano Babic writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
175552a848eSStefano Babic
176552a848eSStefano Babic writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
177552a848eSStefano Babic writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
178552a848eSStefano Babic
179552a848eSStefano Babic writel(DDRMC_CR73_APREBIT(timings->aprebit) |
180552a848eSStefano Babic DDRMC_CR73_COL_DIFF(col_diff) |
181552a848eSStefano Babic DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
182552a848eSStefano Babic writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
183552a848eSStefano Babic DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
184552a848eSStefano Babic DDRMC_CR74_AGE_CNT(timings->age_cnt),
185552a848eSStefano Babic &ddrmr->cr[74]);
186552a848eSStefano Babic writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
187552a848eSStefano Babic DDRMC_CR75_PLEN, &ddrmr->cr[75]);
188552a848eSStefano Babic writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
189552a848eSStefano Babic DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
190552a848eSStefano Babic writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
191552a848eSStefano Babic DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
192552a848eSStefano Babic writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
193552a848eSStefano Babic DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
194552a848eSStefano Babic
195552a848eSStefano Babic writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
196552a848eSStefano Babic
197552a848eSStefano Babic writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
198552a848eSStefano Babic DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
199552a848eSStefano Babic &ddrmr->cr[87]);
200552a848eSStefano Babic writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
201552a848eSStefano Babic writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
202552a848eSStefano Babic
203552a848eSStefano Babic writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
204552a848eSStefano Babic writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
205552a848eSStefano Babic DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
206552a848eSStefano Babic
207552a848eSStefano Babic /* execute custom CR setting sequence (may be NULL) */
208552a848eSStefano Babic cr_setting = board_cr_settings;
209552a848eSStefano Babic if (cr_setting != NULL)
210552a848eSStefano Babic while (cr_setting->cr_rnum >= 0) {
211552a848eSStefano Babic writel(cr_setting->setting,
212552a848eSStefano Babic &ddrmr->cr[cr_setting->cr_rnum]);
213552a848eSStefano Babic cr_setting++;
214552a848eSStefano Babic }
215552a848eSStefano Babic
216552a848eSStefano Babic /* perform default PHY settings (may be overridden by custom settings */
217552a848eSStefano Babic phy_setting = default_phy_settings;
218552a848eSStefano Babic while (phy_setting->phy_rnum >= 0) {
219552a848eSStefano Babic writel(phy_setting->setting,
220552a848eSStefano Babic &ddrmr->phy[phy_setting->phy_rnum]);
221552a848eSStefano Babic phy_setting++;
222552a848eSStefano Babic }
223552a848eSStefano Babic
224552a848eSStefano Babic /* execute custom PHY setting sequence (may be NULL) */
225552a848eSStefano Babic phy_setting = board_phy_settings;
226552a848eSStefano Babic if (phy_setting != NULL)
227552a848eSStefano Babic while (phy_setting->phy_rnum >= 0) {
228552a848eSStefano Babic writel(phy_setting->setting,
229552a848eSStefano Babic &ddrmr->phy[phy_setting->phy_rnum]);
230552a848eSStefano Babic phy_setting++;
231552a848eSStefano Babic }
232552a848eSStefano Babic
233552a848eSStefano Babic /* all inits done, start the DDR controller */
234552a848eSStefano Babic writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
235552a848eSStefano Babic
23652c2c97eSStefan Agner while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
237552a848eSStefano Babic udelay(10);
23852c2c97eSStefan Agner writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
239*dc619924SLukasz Majewski
240*dc619924SLukasz Majewski #ifdef CONFIG_DDRMC_VF610_CALIBRATION
241*dc619924SLukasz Majewski ddrmc_calibration(ddrmr);
242*dc619924SLukasz Majewski #endif
243552a848eSStefano Babic }
244