22  * so we have to setup the DDR timings ourself on both banks.
24 void get_board_mem_timings(struct board_sdrc_timings *timings)  in get_board_mem_timings()  argument
26 	timings->mr = MICRON_V_MR_165;  in get_board_mem_timings()
29 		timings->mcfg = MICRON_V_MCFG_165(256 << 20);  in get_board_mem_timings()
30 		timings->ctrla = MICRON_V_ACTIMA_165;  in get_board_mem_timings()
31 		timings->ctrlb = MICRON_V_ACTIMB_165;  in get_board_mem_timings()
32 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;  in get_board_mem_timings()
36 		timings->mcfg = MICRON_V_MCFG_200(256 << 20);  in get_board_mem_timings()
37 		timings->ctrla = MICRON_V_ACTIMA_200;  in get_board_mem_timings()
38 		timings->ctrlb = MICRON_V_ACTIMB_200;  in get_board_mem_timings()
39 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;  in get_board_mem_timings()
42 		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);  in get_board_mem_timings()
43 		timings->ctrla = HYNIX_V_ACTIMA_200;  in get_board_mem_timings()
44 		timings->ctrlb = HYNIX_V_ACTIMB_200;  in get_board_mem_timings()
45 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;  in get_board_mem_timings()
48 		timings->mcfg = MCFG(512 << 20, 15);  in get_board_mem_timings()
49 		timings->ctrla = MICRON_V_ACTIMA_200;  in get_board_mem_timings()
50 		timings->ctrlb = MICRON_V_ACTIMB_200;  in get_board_mem_timings()
51 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;  in get_board_mem_timings()
54 		timings->mcfg = MICRON_V_MCFG_165(128 << 20);  in get_board_mem_timings()
55 		timings->ctrla = MICRON_V_ACTIMA_165;  in get_board_mem_timings()
56 		timings->ctrlb = MICRON_V_ACTIMB_165;  in get_board_mem_timings()
57 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;  in get_board_mem_timings()