Searched +full:timer +full:- +full:dsp (Results 1 – 25 of 37) sorted by relevance
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4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/11 #include <dt-bindings/gpio/gpio.h>12 #include <dt-bindings/interrupt-controller/irq.h>13 #include <dt-bindings/pinctrl/omap.h>17 interrupt-parent = <&intc>;18 #address-cells = <1>;19 #size-cells = <1>;32 #address-cells = <1>;33 #size-cells = <0>;36 compatible = "arm,cortex-a8";[all …]
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/pinctrl/dra.h>16 #address-cells = <2>;17 #size-cells = <2>;20 interrupt-parent = <&crossbar_mpu>;46 timer {47 compatible = "arm,armv7-timer";52 interrupt-parent = <&gic>;55 gic: interrupt-controller@48211000 {[all …]
10 #include <dt-bindings/interrupt-controller/irq.h>13 #address-cells = <1>;14 #size-cells = <1>;24 #address-cells = <1>;25 #size-cells = <1>;27 intc: interrupt-controller@fffee000 {28 compatible = "ti,cp-intc";29 interrupt-controller;30 #interrupt-cells = <1>;31 ti,intc-size = <101>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+77 "Watchdog timer test",79 "This test checks the watchdog timer.",216 "DSP test",217 "dsp",218 "This test checks any connected DSP(s).",
1 Arm Musca boards (``musca-a``, ``musca-b1``)5 of a system using the SSE-200 Subsystem for Embedded. They are6 dual Cortex-M33 systems.12 - SPI13 - |I2C|14 - |I2S|15 - PWM16 - QSPI17 - Timer18 - SCC[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.13 * ARC architecture has additional address space - auxiliary registers.22 * is 0 this means given HW block is absent - this is especially useful because54 /* Timer related auxiliary registers */55 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */56 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */57 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */59 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */60 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */[all …]
13 * as well-behaved operating systems will not try to use them.266 uint32_t dsp; member304 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */334 return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE); in lsi_irq_on_rsl()341 QTAILQ_FOREACH(p, &s->queue, next) { in get_pending_req()342 if (p->pending) { in get_pending_req()352 s->carry = 0; in lsi_soft_reset()354 s->msg_action = LSI_MSG_ACTION_COMMAND; in lsi_soft_reset()355 s->msg_len = 0; in lsi_soft_reset()356 s->waiting = LSI_NOWAIT; in lsi_soft_reset()[all …]
3 # scsi-bus.c184 esp_mem_writeb(uint32_t saddr, uint8_t reg, uint32_t val) "reg[%d]: 0x%2.2x -> 0x%2.2x"203 # esp-pci.c209 esp_pci_dma_write(uint32_t saddr, uint32_t reg, uint32_t val) "reg[%d]: 0x%8.8x -> 0x%8.8x"215 esp_pci_sbac_write(uint32_t reg, uint32_t val) "sbac: 0x%8.8x -> 0x%8.8x"223 spapr_vscsi_fetch_desc_dma_read_error(int rc) "spapr_vio_dma_read -> %d reading ext_desc"229 spapr_vscsi_srp_indirect_data_rw(int writing, int rc) "spapr_vio_dma_r/w(%d) -> %d"251 lsi_bad_phase_jump(uint32_t dsp) "Data phase mismatch jump to 0x%"PRIX32280 lsi_execute_script(uint32_t dsp, uint32_t insn, uint32_t addr) "SCRIPTS dsp=0x%"PRIx32" opcode 0x%"…306 lsi_scripts_timer_triggered(void) "SCRIPTS timer triggered"[all …]
1 # -*- mode: python -*-4 # Copyright (C) 2015-2019 Zoltán Kővágó <DirtY.iCE.hu@gmail.com>7 # See the COPYING file in the top-level directory.21 # @mixing-engine: use QEMU's mixing engine to mix all streams inside23 # backend. When set to off, fixed-settings must be also off26 # @fixed-settings: use fixed settings for host input/output. When40 # @buffer-length: the buffer length in microseconds46 '*mixing-engine': 'bool',47 '*fixed-settings': 'bool',52 '*buffer-length': 'uint32' } }[all …]
5 * See the COPYING file in the top-level directory.13 #include "tcg/tcg-internal.h"53 * The Count register acts as a timer, incrementing at a constant rate,106 TLBRET_XI = -6,107 TLBRET_RI = -5,108 TLBRET_DIRTY = -4,109 TLBRET_INVALID = -3,110 TLBRET_NOMATCH = -2,111 TLBRET_BADADDR = -1,167 return (env->CP0_Status & (1 << CP0St_IE)) && in cpu_mips_hw_interrupts_enabled()[all …]
4 #include "cpu-qom.h"5 #include "exec/cpu-common.h"6 #include "exec/cpu-defs.h"7 #include "exec/cpu-interrupt.h"11 #include "fpu/softfloat-types.h"13 #include "mips-defs.h"32 uint64_t d; /* binary double fixed-point */33 uint32_t w[2]; /* binary single fixed-point */34 /* FPU/MSA register mapping is not tested on big-endian hosts. */143 * ---------- ---------- ---------- ----------[all …]
2 * ARM SSE (Subsystems for Embedded): IoTKit, SSE-20014 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and15 * SSE-200. Currently we model:16 * - the Arm IoT Kit which is documented in18 * - the SSE-200 which is documented in22 * a Cortex-M3329 * space are secure and non-secure aliases of each other30 * The SSE-200 additionally contains:31 * a second Cortex-M3337 * per-CPU identity and control register blocks[all …]
4 * Copyright (c) 2003-2005 Vassili Karpov (malc)30 #include "hw/qdev-properties.h"32 #include "qemu/timer.h"33 #include "qemu/host-utils.h"153 return -1; in irq_of_magic()158 static void log_dsp (SB16State *dsp)161 dsp->fmt_stereo ? "Stereo" : "Mono",162 dsp->fmt_signed ? "Signed" : "Unsigned",163 dsp->fmt_bits,164 dsp->dma_auto ? "Auto" : "Single",[all …]
4 * Copyright (c) 2006-2007 CodeSourcery.16 #include "hw/qdev-properties.h"17 #include "hw/qdev-clock.h"20 #include "qemu/error-report.h"25 #include "target/arm/cpu-features.h"26 #include "target/arm/cpu-qom.h"34 return s->base | (offset & 0x1ffffff) >> 5; in bitband_addr()49 addr = bitband_addr(s, offset) & (-size); in bitband_read()50 res = address_space_read(&s->source_as, addr, attrs, buf, size); in bitband_read()55 bitpos = (offset >> 2) & ((size * 8) - 1); in bitband_read()[all …]
2 * Arm Musca-B1 test chip board emulation14 * the SSE-200 subsystem for embedded:15 …https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musc…16 …https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musc…23 #include "qemu/error-report.h"25 #include "system/address-spaces.h"31 #include "hw/core/split-irq.h"32 #include "hw/misc/tz-mpc.h"33 #include "hw/misc/tz-ppc.h"36 #include "hw/qdev-clock.h"[all …]
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>22 #include "qemu/error-report.h"23 #include "qemu/main-loop.h"26 #include "system/address-spaces.h"29 #include "hw/qdev-properties.h"44 #include "target/arm/cpu-qom.h"49 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()113 QEMUTimer *timer; member125 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) in omap_timer_read() argument127 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; in omap_timer_read()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */8 /* ---9 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board10 * Date: 2004-03-2914 * general u-boot-1.x.x/README file15 * ---18 /* ---19 * board/config.h - configuration options, board specific20 * ---26 /* ---[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649736 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)51 writel((value), ((a)->hw_addr + E1000_##reg))53 readl((a)->hw_addr + E1000_##reg)55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))349 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */[all …]
2 * MIPS emulation for QEMU - main translation routines4 * Copyright (c) 2004-2005 Jocelyn Mayer8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)9 * Copyright (c) 2020 Philippe Mathieu-Daudé28 #include "exec/helper-proto.h"29 #include "exec/translation-block.h"36 #include "exec/helper-info.c.inc"41 * Many system-only helpers are not reachable for user-only.153 /* PC-relative address computation / loads */157 /* PC-relative address computation / loads */[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */5 * Copyright 2007-2012 Freescale Semiconductor, Inc.47 /* Local-Access Registers & ECM Registers */123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];247 u32 gas_timr; /* PCIX Gasket Timer */298 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */300 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */365 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */419 u32 tr64; /* TX & RX 64-byte Frame Counter */420 u32 tr127; /* TX & RX 65-127 byte Frame Counter */[all …]
19 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */70 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */87 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */181 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */182 #define DCWR_COPY 0 /* Copy-back */183 #define DCWR_WRITE 1 /* Write-through */211 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */212 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */213 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */[all …]
1 // SPDX-License-Identifier: GPL-2.025 #include <dm/uclass-internal.h>69 ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc, in broadwell_pch_early_init()119 /* PCH-LP has 39 redirection entries */ in pch_enable_ioapic()142 * Enable GPIO SMI events - it would be good to put this in the GPIO driver155 return -EINVAL; in enable_alt_smi()159 setio_32(regs->alt_gpi_smi_en, mask); in enable_alt_smi()194 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), in pch_power_options()195 "intel,gpe0-en", enable, ARRAY_SIZE(enable)); in pch_power_options()197 return -EINVAL; in pch_power_options()[all …]
1 # SPDX-License-Identifier: GPL-2.0+3 # (C) Copyright 2000 - 20139 This directory contains the source code for U-Boot, a boot loader for15 The development of U-Boot is closely related to Linux: some parts of37 scattered throughout the U-Boot source identifying the people or41 actual U-Boot source tree; however, it can be created dynamically51 U-Boot, you should send a message to the U-Boot mailing list at52 <u-boot@lists.denx.de>. There is also an archive of previous traffic53 on the mailing list - please search the archive before asking FAQ's.54 Please see http://lists.denx.de/pipermail/u-boot and[all …]
23 #include "kvm-consts.h"24 #include "qemu/cpu-float.h"26 #include "cpu-qom.h"27 #include "exec/cpu-common.h"28 #include "exec/cpu-defs.h"29 #include "exec/cpu-interrupt.h"31 #include "exec/page-protection.h"32 #include "qapi/qapi-types-common.h"35 #include "target/arm/cpu-sysregs.h"79 /* ARM-specific interrupt pending bits. */[all …]
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