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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dstericsson,db8500-prcmu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/stericsson,db8500-prcmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit
10 - Linus Walleij <linus.walleij@linaro.org>
13 The DB8500 Power Reset and Control Management Unit is an XP70 8-bit
14 microprocessor that is embedded in the always-on power domain of the
20 pattern: '^prcmu@[0-9a-f]+$'
23 description: The device is compatible both to the device-specific
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/openbmc/linux/drivers/remoteproc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 Support for remote processors (such as DSP coprocessors). These
38 tristate "i.MX DSP remoteproc support"
43 Say y here to support iMX's DSP remote processors via the remote
54 This can be either built-in or a loadable module.
75 and DSP on OMAP4) via the remote processor framework.
80 use-cases to run on your platform (multimedia codecs are
81 offloaded to remote DSP processors using this framework).
87 bool "OMAP remoteproc watchdog timer"
91 Say Y here to enable watchdog timer for remote processors.
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H A Domap_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * Ohad Ben-Cohen <ohad@wizery.com>
12 * Suman Anna <s-anna@ti.com>
13 * Hari Kanigeri <h-kanigeri2@ti.com>
27 #include <linux/dma-mapping.h>
31 #include <linux/omap-iommu.h>
32 #include <linux/omap-mailbox.h>
36 #include <clocksource/timer-ti-dm.h>
38 #include <linux/platform_data/dmtimer-omap.h>
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <0>;
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H A Domap3.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
33 #address-cells = <1>;
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H A Domap5-l4-abe.dtsi2 compatible = "ti,omap5-l4-abe", "simple-pm-bus";
5 reg-names = "la", "ap";
6 power-domains = <&prm_abe>;
7 /* OMAP5_L4_ABE_CLKCTRL is read-only */
8 #address-cells = <1>;
9 #size-cells = <1>;
13 compatible = "simple-pm-bus";
14 #address-cells = <1>;
15 #size-cells = <1>;
89 target-module@22000 { /* 0x40122000, ap 2 02.0 */
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H A Domap4-l4-abe.dtsi2 compatible = "ti,omap4-l4-abe", "simple-pm-bus";
5 reg-names = "la", "ap";
6 power-domains = <&prm_abe>;
7 /* OMAP4_L4_ABE_CLKCTRL is read-only */
8 #address-cells = <1>;
9 #size-cells = <1>;
13 compatible = "simple-pm-bus";
14 #address-cells = <1>;
15 #size-cells = <1>;
89 target-module@22000 { /* 0x40122000, ap 2 02.0 */
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
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/openbmc/linux/sound/pci/pcxhr/
H A Dpcxhr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 /* transfer granularity of pipes and the dsp time (MBOX4) */
76 unsigned int dsp_loaded; /* bit flags of loaded dsp indices */
96 int timer_toggle; /* timer interrupt toggles between the two values 0x200 and 0x300 */
97 int dsp_time_last; /* the last dsp time (read by interrupt) */
98 int dsp_time_err; /* dsp time errors */
99 unsigned int src_it_dsp; /* dsp interrupt source */
132 …u_int64_t timer_abs_periods; /* timer: samples elapsed since TRIGGER_START (multiple of period_siz…
133 …u_int32_t timer_period_frag; /* timer: samples elapsed since last call to snd_pcm_period_elapsed (…
135 int timer_is_synced; /* if(0) : timer needs to be resynced with real hardware pointer */
H A Dpcxhr_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 /* registers used on the DSP (port 2) */
59 #define PCXHR_INPB(mgr,x) inb((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
60 #define PCXHR_INPL(mgr,x) inl((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
61 #define PCXHR_OUTPB(mgr,x,data) outb((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
62 #define PCXHR_OUTPL(mgr,x,data) outl((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
105 * pcxhr_check_reg_bit - wait for the specified bit is set/reset on a register
109 * @time: time-out of loop in msec
123 dev_dbg(&mgr->pci->dev, in pcxhr_check_reg_bit()
130 dev_err(&mgr->pci->dev, in pcxhr_check_reg_bit()
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/openbmc/linux/sound/pci/echoaudio/
H A Dmidi.c3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
39 dev_dbg(chip->card->dev, "enable_midi_input(%d)\n", enable); in enable_midi_input()
42 return -EIO; in enable_midi_input()
45 chip->mtc_state = MIDI_IN_STATE_NORMAL; in enable_midi_input()
46 chip->comm_page->flags |= in enable_midi_input()
49 chip->comm_page->flags &= in enable_midi_input()
58 /* Send a buffer full of MIDI data to the DSP
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/openbmc/linux/drivers/isdn/mISDN/
H A Ddsp_core.c12 * Real-time tone generation
14 * Real-time cross-connection and conferrence
23 * The dsp module provides layer 2 for b-channels (64kbit). It provides
26 * - (1) generation of tones
27 * - (2) detection of dtmf tones
28 * - (3) crossconnecting and conferences (clocking)
29 * - (4) echo generation for delay test
30 * - (5) volume control
31 * - (6) disable receive data
32 * - (7) pipeline
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H A Ddsp.h30 #include <linux/timer.h>
41 extern u32 dsp_poll_diff; /* calculated fix-comma corrected poll value */
68 #define MAX_POLL 256 /* maximum number of send-chunks */
72 #define CMX_BUFF_MASK 0x7fff /* CMX_BUFF_SIZE - 1 */
91 /* all members within a conference (this is linked 1:1 with the dsp) */
92 struct dsp;
95 struct dsp *dsp; member
118 #define ECHOCAN_BUFF_MASK 0x3ff /* -1 */
170 struct dsp { struct
210 int tx_data; /* enables tx-data of CMX to upper layer */
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H A Ddsp_tones.c15 #include "dsp.h"
367 * pattern - the type of the pattern
368 * count - the sample from the beginning of the pattern (phase)
369 * len - the number of bytes
371 * return - the sk_buff with the sample
373 * if tones has finished (e.g. knocking tone), dsp->tones is turned off
375 void dsp_tone_copy(struct dsp *dsp, u8 *data, int len) in dsp_tone_copy() argument
379 struct dsp_tone *tone = &dsp->tone; in dsp_tone_copy()
382 if (!tone->tone) { in dsp_tone_copy()
388 pat = (struct pattern *)tone->pattern; in dsp_tone_copy()
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/openbmc/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
128 -Caches: New Prog Model, Region Flush
129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
132 bool "ARC-HS"
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/openbmc/u-boot/arch/arm/dts/
H A Domap3.dtsi4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,cortex-a8";
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/openbmc/u-boot/post/
H A Dtests.c1 // SPDX-License-Identifier: GPL-2.0+
77 "Watchdog timer test",
79 "This test checks the watchdog timer.",
216 "DSP test",
217 "dsp",
218 "This test checks any connected DSP(s).",
/openbmc/linux/drivers/char/mwave/
H A D3780i.h3 * 3780i.h -- declarations for 3780i.c
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
54 /* DSP I/O port offsets and definitions */
62 #define DSP_MsaDataDSISHigh 0x0008 /* MSA data register: d-store word or high byte of i-stor…
63 #define DSP_MsaDataISLow 0x000A /* MSA data register: low word of i-store */
76 unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
80 unsigned short IsaPacingTimer:12; /* R: ISA access pacing timer: count of core cycles stolen */
84 /* DSP register indexes used with the configuration register address (index) register */
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H A Dtp3780i.h3 * tp3780i.h -- declarations for tp3780i.c
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
56 /* DSP abilities constants for 3780i based Thinkpads */
60 #define TP_ABILITIES_MWAVEOS_NAME "mwaveos0700.dsp"
61 #define TP_ABILITIES_BIOSTASK_NAME "mwbio701.dsp"
64 /* DSP configuration values for 3780i based Thinkpads */
67 #define TP_CFG_MEMCS16 0 /* Disabled, 16-bit memory assumed */
68 #define TP_CFG_IsaMemCmdWidth 3 /* 295 nsec (16-bit) */
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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/openbmc/linux/arch/arm/mach-omap1/
H A Dpm.c2 * linux/arch/arm/mach-omap1/pm.c
55 #include <linux/soc/ti/omap1-io.h>
57 #include <linux/omap-dma.h>
58 #include <clocksource/timer-ti-dm.h>
91 return -EINVAL; in idle_store()
129 * tests above as soon as drivers, timer and DMA code have been fixed. in omap1_pm_idle()
163 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, in omap_pm_wakeup_setup()
263 /* (Step 3 removed - we now allow deep sleep by default) */ in omap1_pm_suspend()
266 * Step 4: OMAP DSP Shutdown in omap1_pm_suspend()
269 /* stop DSP */ in omap1_pm_suspend()
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/openbmc/linux/arch/arc/kernel/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
31 #include <asm/dsp-impl.h>
38 /* Part of U-boot ABI: see head.S */
100 if (info->arcver < 0x34) in arcompact_mumbojumbo()
105 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s (%s ISA) %s%s%s\n", in arcompact_mumbojumbo()
108 IS_AVAIL1(be, "[Big-Endian]")); in arcompact_mumbojumbo()
114 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", in arcompact_mumbojumbo()
120 bpu_cache = 256 << (bpu.ent - 1); in arcompact_mumbojumbo()
121 bpu_pred = 256 << (bpu.ent - 1); in arcompact_mumbojumbo()
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/openbmc/u-boot/arch/arc/include/asm/
H A Darcregs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
13 * ARC architecture has additional address space - auxiliary registers.
22 * is 0 this means given HW block is absent - this is especially useful because
54 /* Timer related auxiliary registers */
55 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
56 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
57 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
59 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
60 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
20 tifs-sram@1f0000 {
24 l3cache-sram@200000 {
29 gic500: interrupt-controller@1800000 {
30 compatible = "arm,gic-v3";
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/openbmc/linux/sound/soc/sof/intel/
H A Dcnl.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
15 * Hardware interface for audio DSP on Cannonlake.
21 #include "../ipc4-priv.h"
24 #include "hda-ipc.h"
25 #include "../sof-audio.h"
30 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
47 /* DSP received the message */ in cnl_ipc4_irq_thread()
58 /* Message from DSP (reply or notification) */ in cnl_ipc4_irq_thread()
66 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) { in cnl_ipc4_irq_thread()
67 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data; in cnl_ipc4_irq_thread()
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