183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2288aaacfSAlexey Brodkin /* 3288aaacfSAlexey Brodkin * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 4288aaacfSAlexey Brodkin */ 5288aaacfSAlexey Brodkin 6288aaacfSAlexey Brodkin #ifndef _ASM_ARC_ARCREGS_H 7288aaacfSAlexey Brodkin #define _ASM_ARC_ARCREGS_H 8288aaacfSAlexey Brodkin 9812980bdSAlexey Brodkin #include <asm/cache.h> 105e0c68edSEugeniy Paltsev #include <config.h> 11812980bdSAlexey Brodkin 12288aaacfSAlexey Brodkin /* 13288aaacfSAlexey Brodkin * ARC architecture has additional address space - auxiliary registers. 14288aaacfSAlexey Brodkin * These registers are mostly used for configuration purposes. 15288aaacfSAlexey Brodkin * These registers are not memory mapped and special commands are used for 16288aaacfSAlexey Brodkin * access: "lr"/"sr". 17288aaacfSAlexey Brodkin */ 18288aaacfSAlexey Brodkin 19*85e529fdSAlexey Brodkin /* 20*85e529fdSAlexey Brodkin * Typically 8 least significant bits of Build Configuration Register (BCR) 21*85e529fdSAlexey Brodkin * describe version of the HW block in question. Moreover if decoded version 22*85e529fdSAlexey Brodkin * is 0 this means given HW block is absent - this is especially useful because 23*85e529fdSAlexey Brodkin * we may safely read BRC regardless HW block existence while an attempt to 24*85e529fdSAlexey Brodkin * access any other AUX regs associated with this HW block lead to imediate 25*85e529fdSAlexey Brodkin * "instruction error" exception. 26*85e529fdSAlexey Brodkin * 27*85e529fdSAlexey Brodkin * I.e. before using any cofigurable HW block it's required to make sure it 28*85e529fdSAlexey Brodkin * exists at all, and for that we introduce a special macro below. 29*85e529fdSAlexey Brodkin */ 30*85e529fdSAlexey Brodkin #define ARC_BCR_VERSION_MASK GENMASK(7, 0) 31*85e529fdSAlexey Brodkin #define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK) 32*85e529fdSAlexey Brodkin 33288aaacfSAlexey Brodkin #define ARC_AUX_IDENTITY 0x04 34288aaacfSAlexey Brodkin #define ARC_AUX_STATUS32 0x0a 35288aaacfSAlexey Brodkin 368f590063SAlexey Brodkin /* STATUS32 Bits Positions */ 378f590063SAlexey Brodkin #define STATUS_AD_BIT 19 /* Enable unaligned access */ 388f590063SAlexey Brodkin 39288aaacfSAlexey Brodkin /* Instruction cache related auxiliary registers */ 40288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIC 0x10 41288aaacfSAlexey Brodkin #define ARC_AUX_IC_CTRL 0x11 42288aaacfSAlexey Brodkin #define ARC_AUX_IC_IVIL 0x19 435ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 44288aaacfSAlexey Brodkin #define ARC_AUX_IC_PTAG 0x1E 45288aaacfSAlexey Brodkin #endif 46f8cf3d1eSIgor Guryanov #define ARC_BCR_IC_BUILD 0x77 4764f47426SEugeniy Paltsev #define AUX_AUX_CACHE_LIMIT 0x5D 4864f47426SEugeniy Paltsev #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E 4964f47426SEugeniy Paltsev 5064f47426SEugeniy Paltsev /* ICCM and DCCM auxiliary registers */ 5164f47426SEugeniy Paltsev #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ 5264f47426SEugeniy Paltsev #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ 53288aaacfSAlexey Brodkin 54288aaacfSAlexey Brodkin /* Timer related auxiliary registers */ 55288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 56288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 57288aaacfSAlexey Brodkin #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 58288aaacfSAlexey Brodkin 59ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 60ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 61ad9b5f77SVlad Zakharov #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 62ad9b5f77SVlad Zakharov 63288aaacfSAlexey Brodkin #define ARC_AUX_INTR_VEC_BASE 0x25 64288aaacfSAlexey Brodkin 65288aaacfSAlexey Brodkin /* Data cache related auxiliary registers */ 66288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDC 0x47 67288aaacfSAlexey Brodkin #define ARC_AUX_DC_CTRL 0x48 68288aaacfSAlexey Brodkin 69288aaacfSAlexey Brodkin #define ARC_AUX_DC_IVDL 0x4A 70288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLSH 0x4B 71288aaacfSAlexey Brodkin #define ARC_AUX_DC_FLDL 0x4C 725ff40f3dSAlexey Brodkin #if (CONFIG_ARC_MMU_VER == 3) 73288aaacfSAlexey Brodkin #define ARC_AUX_DC_PTAG 0x5C 74288aaacfSAlexey Brodkin #endif 75f8cf3d1eSIgor Guryanov #define ARC_BCR_DC_BUILD 0x72 766eb15e50SAlexey Brodkin #define ARC_BCR_SLC 0xce 77ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CONFIG 0x901 78ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_CTRL 0x903 796eb15e50SAlexey Brodkin #define ARC_AUX_SLC_FLUSH 0x904 806eb15e50SAlexey Brodkin #define ARC_AUX_SLC_INVALIDATE 0x905 81ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_IVDL 0x910 82ef639e6fSAlexey Brodkin #define ARC_AUX_SLC_FLDL 0x912 8341cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_START 0x914 8441cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_START1 0x915 8541cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_END 0x916 8641cada4dSEugeniy Paltsev #define ARC_AUX_SLC_RGN_END1 0x917 87db6ce231SAlexey Brodkin #define ARC_BCR_CLUSTER 0xcf 88db6ce231SAlexey Brodkin 8941cada4dSEugeniy Paltsev /* MMU Management regs */ 90*85e529fdSAlexey Brodkin #define ARC_AUX_MMU_BCR 0x6f 9141cada4dSEugeniy Paltsev 92db6ce231SAlexey Brodkin /* IO coherency related auxiliary registers */ 93db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_ENABLE 0x500 94db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_PARTIAL 0x501 95db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_BASE 0x508 96db6ce231SAlexey Brodkin #define ARC_AUX_IO_COH_AP0_SIZE 0x509 97288aaacfSAlexey Brodkin 98*85e529fdSAlexey Brodkin /* XY-memory related */ 99*85e529fdSAlexey Brodkin #define ARC_AUX_XY_BUILD 0x79 100*85e529fdSAlexey Brodkin 101*85e529fdSAlexey Brodkin /* DSP-extensions related auxiliary registers */ 102*85e529fdSAlexey Brodkin #define ARC_AUX_DSP_BUILD 0x7A 103*85e529fdSAlexey Brodkin 104*85e529fdSAlexey Brodkin /* ARC Subsystems related auxiliary registers */ 105*85e529fdSAlexey Brodkin #define ARC_AUX_SUBSYS_BUILD 0xF0 106*85e529fdSAlexey Brodkin 107288aaacfSAlexey Brodkin #ifndef __ASSEMBLY__ 108288aaacfSAlexey Brodkin /* Accessors for auxiliary registers */ 109288aaacfSAlexey Brodkin #define read_aux_reg(reg) __builtin_arc_lr(reg) 110288aaacfSAlexey Brodkin 111288aaacfSAlexey Brodkin /* gcc builtin sr needs reg param to be long immediate */ 112288aaacfSAlexey Brodkin #define write_aux_reg(reg_immed, val) \ 113288aaacfSAlexey Brodkin __builtin_arc_sr((unsigned int)val, reg_immed) 114e59c3797SEugeniy Paltsev 115e59c3797SEugeniy Paltsev /* ARCNUM [15:8] - field to identify each core in a multi-core system */ 116e59c3797SEugeniy Paltsev #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) 1175e0c68edSEugeniy Paltsev is_isa_arcv2(void)1185e0c68edSEugeniy Paltsevstatic const inline int is_isa_arcv2(void) 1195e0c68edSEugeniy Paltsev { 1205e0c68edSEugeniy Paltsev return IS_ENABLED(CONFIG_ISA_ARCV2); 1215e0c68edSEugeniy Paltsev } 1225e0c68edSEugeniy Paltsev is_isa_arcompact(void)1235e0c68edSEugeniy Paltsevstatic const inline int is_isa_arcompact(void) 1245e0c68edSEugeniy Paltsev { 1255e0c68edSEugeniy Paltsev return IS_ENABLED(CONFIG_ISA_ARCOMPACT); 1265e0c68edSEugeniy Paltsev } 127288aaacfSAlexey Brodkin #endif /* __ASSEMBLY__ */ 128288aaacfSAlexey Brodkin 129288aaacfSAlexey Brodkin #endif /* _ASM_ARC_ARCREGS_H */ 130