183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese /* 3a47a12beSStefan Roese * MPC85xx Internal Memory Map 4a47a12beSStefan Roese * 519a8dbdcSPrabhakar Kushwaha * Copyright 2007-2012 Freescale Semiconductor, Inc. 6a47a12beSStefan Roese * 7a47a12beSStefan Roese * Copyright(c) 2002,2003 Motorola Inc. 8a47a12beSStefan Roese * Xianghua Xiao (x.xiao@motorola.com) 9a47a12beSStefan Roese */ 10a47a12beSStefan Roese 11a47a12beSStefan Roese #ifndef __IMMAP_85xx__ 12a47a12beSStefan Roese #define __IMMAP_85xx__ 13a47a12beSStefan Roese 14a47a12beSStefan Roese #include <asm/types.h> 15a47a12beSStefan Roese #include <asm/fsl_dma.h> 16a47a12beSStefan Roese #include <asm/fsl_i2c.h> 170b66513bSYork Sun #include <fsl_ifc.h> 1848ef0d2aSRuchika Gupta #include <fsl_sec.h> 19a2e225e6Sgaurav rana #include <fsl_sfp.h> 20a47a12beSStefan Roese #include <asm/fsl_lbc.h> 218225b2fdSShaohui Xie #include <fsl_fman.h> 229a17eb5bSYork Sun #include <fsl_immap.h> 23a47a12beSStefan Roese 24a47a12beSStefan Roese typedef struct ccsr_local { 25a47a12beSStefan Roese u32 ccsrbarh; /* CCSR Base Addr High */ 26a47a12beSStefan Roese u32 ccsrbarl; /* CCSR Base Addr Low */ 27a47a12beSStefan Roese u32 ccsrar; /* CCSR Attr */ 28a47a12beSStefan Roese #define CCSRAR_C 0x80000000 /* Commit */ 29a47a12beSStefan Roese u8 res1[4]; 30a47a12beSStefan Roese u32 altcbarh; /* Alternate Configuration Base Addr High */ 31a47a12beSStefan Roese u32 altcbarl; /* Alternate Configuration Base Addr Low */ 32a47a12beSStefan Roese u32 altcar; /* Alternate Configuration Attr */ 33a47a12beSStefan Roese u8 res2[4]; 34a47a12beSStefan Roese u32 bstrh; /* Boot space translation high */ 35a47a12beSStefan Roese u32 bstrl; /* Boot space translation Low */ 36a47a12beSStefan Roese u32 bstrar; /* Boot space translation attributes */ 37a47a12beSStefan Roese u8 res3[0xbd4]; 38a47a12beSStefan Roese struct { 39a47a12beSStefan Roese u32 lawbarh; /* LAWn base addr high */ 40a47a12beSStefan Roese u32 lawbarl; /* LAWn base addr low */ 41a47a12beSStefan Roese u32 lawar; /* LAWn attributes */ 42a47a12beSStefan Roese u8 res4[4]; 43a47a12beSStefan Roese } law[32]; 44a47a12beSStefan Roese u8 res35[0x204]; 45a47a12beSStefan Roese } ccsr_local_t; 46a47a12beSStefan Roese 47a47a12beSStefan Roese /* Local-Access Registers & ECM Registers */ 48a47a12beSStefan Roese typedef struct ccsr_local_ecm { 49a47a12beSStefan Roese u32 ccsrbar; /* CCSR Base Addr */ 50a47a12beSStefan Roese u8 res1[4]; 51a47a12beSStefan Roese u32 altcbar; /* Alternate Configuration Base Addr */ 52a47a12beSStefan Roese u8 res2[4]; 53a47a12beSStefan Roese u32 altcar; /* Alternate Configuration Attr */ 54a47a12beSStefan Roese u8 res3[12]; 55a47a12beSStefan Roese u32 bptr; /* Boot Page Translation */ 56a47a12beSStefan Roese u8 res4[3044]; 57a47a12beSStefan Roese u32 lawbar0; /* Local Access Window 0 Base Addr */ 58a47a12beSStefan Roese u8 res5[4]; 59a47a12beSStefan Roese u32 lawar0; /* Local Access Window 0 Attrs */ 60a47a12beSStefan Roese u8 res6[20]; 61a47a12beSStefan Roese u32 lawbar1; /* Local Access Window 1 Base Addr */ 62a47a12beSStefan Roese u8 res7[4]; 63a47a12beSStefan Roese u32 lawar1; /* Local Access Window 1 Attrs */ 64a47a12beSStefan Roese u8 res8[20]; 65a47a12beSStefan Roese u32 lawbar2; /* Local Access Window 2 Base Addr */ 66a47a12beSStefan Roese u8 res9[4]; 67a47a12beSStefan Roese u32 lawar2; /* Local Access Window 2 Attrs */ 68a47a12beSStefan Roese u8 res10[20]; 69a47a12beSStefan Roese u32 lawbar3; /* Local Access Window 3 Base Addr */ 70a47a12beSStefan Roese u8 res11[4]; 71a47a12beSStefan Roese u32 lawar3; /* Local Access Window 3 Attrs */ 72a47a12beSStefan Roese u8 res12[20]; 73a47a12beSStefan Roese u32 lawbar4; /* Local Access Window 4 Base Addr */ 74a47a12beSStefan Roese u8 res13[4]; 75a47a12beSStefan Roese u32 lawar4; /* Local Access Window 4 Attrs */ 76a47a12beSStefan Roese u8 res14[20]; 77a47a12beSStefan Roese u32 lawbar5; /* Local Access Window 5 Base Addr */ 78a47a12beSStefan Roese u8 res15[4]; 79a47a12beSStefan Roese u32 lawar5; /* Local Access Window 5 Attrs */ 80a47a12beSStefan Roese u8 res16[20]; 81a47a12beSStefan Roese u32 lawbar6; /* Local Access Window 6 Base Addr */ 82a47a12beSStefan Roese u8 res17[4]; 83a47a12beSStefan Roese u32 lawar6; /* Local Access Window 6 Attrs */ 84a47a12beSStefan Roese u8 res18[20]; 85a47a12beSStefan Roese u32 lawbar7; /* Local Access Window 7 Base Addr */ 86a47a12beSStefan Roese u8 res19[4]; 87a47a12beSStefan Roese u32 lawar7; /* Local Access Window 7 Attrs */ 88a47a12beSStefan Roese u8 res19_8a[20]; 89a47a12beSStefan Roese u32 lawbar8; /* Local Access Window 8 Base Addr */ 90a47a12beSStefan Roese u8 res19_8b[4]; 91a47a12beSStefan Roese u32 lawar8; /* Local Access Window 8 Attrs */ 92a47a12beSStefan Roese u8 res19_9a[20]; 93a47a12beSStefan Roese u32 lawbar9; /* Local Access Window 9 Base Addr */ 94a47a12beSStefan Roese u8 res19_9b[4]; 95a47a12beSStefan Roese u32 lawar9; /* Local Access Window 9 Attrs */ 96a47a12beSStefan Roese u8 res19_10a[20]; 97a47a12beSStefan Roese u32 lawbar10; /* Local Access Window 10 Base Addr */ 98a47a12beSStefan Roese u8 res19_10b[4]; 99a47a12beSStefan Roese u32 lawar10; /* Local Access Window 10 Attrs */ 100a47a12beSStefan Roese u8 res19_11a[20]; 101a47a12beSStefan Roese u32 lawbar11; /* Local Access Window 11 Base Addr */ 102a47a12beSStefan Roese u8 res19_11b[4]; 103a47a12beSStefan Roese u32 lawar11; /* Local Access Window 11 Attrs */ 104a47a12beSStefan Roese u8 res20[652]; 105a47a12beSStefan Roese u32 eebacr; /* ECM CCB Addr Configuration */ 106a47a12beSStefan Roese u8 res21[12]; 107a47a12beSStefan Roese u32 eebpcr; /* ECM CCB Port Configuration */ 108a47a12beSStefan Roese u8 res22[3564]; 109a47a12beSStefan Roese u32 eedr; /* ECM Error Detect */ 110a47a12beSStefan Roese u8 res23[4]; 111a47a12beSStefan Roese u32 eeer; /* ECM Error Enable */ 112a47a12beSStefan Roese u32 eeatr; /* ECM Error Attrs Capture */ 113a47a12beSStefan Roese u32 eeadr; /* ECM Error Addr Capture */ 114a47a12beSStefan Roese u8 res24[492]; 115a47a12beSStefan Roese } ccsr_local_ecm_t; 116a47a12beSStefan Roese 1179ab87d04SKumar Gala #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ 1189ab87d04SKumar Gala #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ 1199ab87d04SKumar Gala 120a47a12beSStefan Roese /* I2C Registers */ 121a47a12beSStefan Roese typedef struct ccsr_i2c { 122ec2c81c5Smario.six@gdsys.cc struct fsl_i2c_base i2c[1]; 123ec2c81c5Smario.six@gdsys.cc u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)]; 124a47a12beSStefan Roese } ccsr_i2c_t; 125a47a12beSStefan Roese 1267f825218SYork Sun #if defined(CONFIG_ARCH_MPC8540) || \ 1273aff3082SYork Sun defined(CONFIG_ARCH_MPC8541) || \ 128281ed4c7SYork Sun defined(CONFIG_ARCH_MPC8548) || \ 1293c3d8ab5SYork Sun defined(CONFIG_ARCH_MPC8555) 130a47a12beSStefan Roese /* DUART Registers */ 131a47a12beSStefan Roese typedef struct ccsr_duart { 132a47a12beSStefan Roese u8 res1[1280]; 133a47a12beSStefan Roese /* URBR1, UTHR1, UDLB1 with the same addr */ 134a47a12beSStefan Roese u8 urbr1_uthr1_udlb1; 135a47a12beSStefan Roese /* UIER1, UDMB1 with the same addr01 */ 136a47a12beSStefan Roese u8 uier1_udmb1; 137a47a12beSStefan Roese /* UIIR1, UFCR1, UAFR1 with the same addr */ 138a47a12beSStefan Roese u8 uiir1_ufcr1_uafr1; 139a47a12beSStefan Roese u8 ulcr1; /* UART1 Line Control */ 140a47a12beSStefan Roese u8 umcr1; /* UART1 Modem Control */ 141a47a12beSStefan Roese u8 ulsr1; /* UART1 Line Status */ 142a47a12beSStefan Roese u8 umsr1; /* UART1 Modem Status */ 143a47a12beSStefan Roese u8 uscr1; /* UART1 Scratch */ 144a47a12beSStefan Roese u8 res2[8]; 145a47a12beSStefan Roese u8 udsr1; /* UART1 DMA Status */ 146a47a12beSStefan Roese u8 res3[239]; 147a47a12beSStefan Roese /* URBR2, UTHR2, UDLB2 with the same addr */ 148a47a12beSStefan Roese u8 urbr2_uthr2_udlb2; 149a47a12beSStefan Roese /* UIER2, UDMB2 with the same addr */ 150a47a12beSStefan Roese u8 uier2_udmb2; 151a47a12beSStefan Roese /* UIIR2, UFCR2, UAFR2 with the same addr */ 152a47a12beSStefan Roese u8 uiir2_ufcr2_uafr2; 153a47a12beSStefan Roese u8 ulcr2; /* UART2 Line Control */ 154a47a12beSStefan Roese u8 umcr2; /* UART2 Modem Control */ 155a47a12beSStefan Roese u8 ulsr2; /* UART2 Line Status */ 156a47a12beSStefan Roese u8 umsr2; /* UART2 Modem Status */ 157a47a12beSStefan Roese u8 uscr2; /* UART2 Scratch */ 158a47a12beSStefan Roese u8 res4[8]; 159a47a12beSStefan Roese u8 udsr2; /* UART2 DMA Status */ 160a47a12beSStefan Roese u8 res5[2543]; 161a47a12beSStefan Roese } ccsr_duart_t; 162a47a12beSStefan Roese #else /* MPC8560 uses UART on its CPM */ 163a47a12beSStefan Roese typedef struct ccsr_duart { 164a47a12beSStefan Roese u8 res[4096]; 165a47a12beSStefan Roese } ccsr_duart_t; 166a47a12beSStefan Roese #endif 167a47a12beSStefan Roese 168a47a12beSStefan Roese /* eSPI Registers */ 169a47a12beSStefan Roese typedef struct ccsr_espi { 170a47a12beSStefan Roese u32 mode; /* eSPI mode */ 171a47a12beSStefan Roese u32 event; /* eSPI event */ 172a47a12beSStefan Roese u32 mask; /* eSPI mask */ 173a47a12beSStefan Roese u32 com; /* eSPI command */ 174a47a12beSStefan Roese u32 tx; /* eSPI transmit FIFO access */ 175a47a12beSStefan Roese u32 rx; /* eSPI receive FIFO access */ 176a47a12beSStefan Roese u8 res1[8]; /* reserved */ 177a47a12beSStefan Roese u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ 178a47a12beSStefan Roese u8 res2[4048]; /* fill up to 0x1000 */ 179a47a12beSStefan Roese } ccsr_espi_t; 180a47a12beSStefan Roese 181a47a12beSStefan Roese /* PCI Registers */ 182a47a12beSStefan Roese typedef struct ccsr_pcix { 183a47a12beSStefan Roese u32 cfg_addr; /* PCIX Configuration Addr */ 184a47a12beSStefan Roese u32 cfg_data; /* PCIX Configuration Data */ 185a47a12beSStefan Roese u32 int_ack; /* PCIX IRQ Acknowledge */ 186e389a377SLaurentiu Tudor u8 res000c[52]; 187e389a377SLaurentiu Tudor u32 liodn_base; /* PCIX LIODN base register */ 1888f9fe660SLaurentiu TUDOR u8 res0044[2996]; 1898f9fe660SLaurentiu TUDOR u32 ipver1; /* PCIX IP block revision register 1 */ 1908f9fe660SLaurentiu TUDOR u32 ipver2; /* PCIX IP block revision register 2 */ 191a47a12beSStefan Roese u32 potar0; /* PCIX Outbound Transaction Addr 0 */ 192a47a12beSStefan Roese u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ 193a47a12beSStefan Roese u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ 194a47a12beSStefan Roese u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ 195a47a12beSStefan Roese u32 powar0; /* PCIX Outbound Window Attrs 0 */ 196a47a12beSStefan Roese u8 res2[12]; 197a47a12beSStefan Roese u32 potar1; /* PCIX Outbound Transaction Addr 1 */ 198a47a12beSStefan Roese u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ 199a47a12beSStefan Roese u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ 200a47a12beSStefan Roese u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ 201a47a12beSStefan Roese u32 powar1; /* PCIX Outbound Window Attrs 1 */ 202a47a12beSStefan Roese u8 res3[12]; 203a47a12beSStefan Roese u32 potar2; /* PCIX Outbound Transaction Addr 2 */ 204a47a12beSStefan Roese u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ 205a47a12beSStefan Roese u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ 206a47a12beSStefan Roese u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ 207a47a12beSStefan Roese u32 powar2; /* PCIX Outbound Window Attrs 2 */ 208a47a12beSStefan Roese u8 res4[12]; 209a47a12beSStefan Roese u32 potar3; /* PCIX Outbound Transaction Addr 3 */ 210a47a12beSStefan Roese u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ 211a47a12beSStefan Roese u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ 212a47a12beSStefan Roese u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ 213a47a12beSStefan Roese u32 powar3; /* PCIX Outbound Window Attrs 3 */ 214a47a12beSStefan Roese u8 res5[12]; 215a47a12beSStefan Roese u32 potar4; /* PCIX Outbound Transaction Addr 4 */ 216a47a12beSStefan Roese u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ 217a47a12beSStefan Roese u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ 218a47a12beSStefan Roese u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ 219a47a12beSStefan Roese u32 powar4; /* PCIX Outbound Window Attrs 4 */ 220a47a12beSStefan Roese u8 res6[268]; 221a47a12beSStefan Roese u32 pitar3; /* PCIX Inbound Translation Addr 3 */ 222a47a12beSStefan Roese u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ 223a47a12beSStefan Roese u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ 224a47a12beSStefan Roese u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ 225a47a12beSStefan Roese u32 piwar3; /* PCIX Inbound Window Attrs 3 */ 226a47a12beSStefan Roese u8 res7[12]; 227a47a12beSStefan Roese u32 pitar2; /* PCIX Inbound Translation Addr 2 */ 228a47a12beSStefan Roese u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ 229a47a12beSStefan Roese u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ 230a47a12beSStefan Roese u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ 231a47a12beSStefan Roese u32 piwar2; /* PCIX Inbound Window Attrs 2 */ 232a47a12beSStefan Roese u8 res8[12]; 233a47a12beSStefan Roese u32 pitar1; /* PCIX Inbound Translation Addr 1 */ 234a47a12beSStefan Roese u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ 235a47a12beSStefan Roese u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ 236a47a12beSStefan Roese u8 res9[4]; 237a47a12beSStefan Roese u32 piwar1; /* PCIX Inbound Window Attrs 1 */ 238a47a12beSStefan Roese u8 res10[12]; 239a47a12beSStefan Roese u32 pedr; /* PCIX Error Detect */ 240a47a12beSStefan Roese u32 pecdr; /* PCIX Error Capture Disable */ 241a47a12beSStefan Roese u32 peer; /* PCIX Error Enable */ 242a47a12beSStefan Roese u32 peattrcr; /* PCIX Error Attrs Capture */ 243a47a12beSStefan Roese u32 peaddrcr; /* PCIX Error Addr Capture */ 244a47a12beSStefan Roese u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ 245a47a12beSStefan Roese u32 pedlcr; /* PCIX Error Data Low Capture */ 246a47a12beSStefan Roese u32 pedhcr; /* PCIX Error Error Data High Capture */ 247a47a12beSStefan Roese u32 gas_timr; /* PCIX Gasket Timer */ 248a47a12beSStefan Roese u8 res11[476]; 249a47a12beSStefan Roese } ccsr_pcix_t; 250a47a12beSStefan Roese 251a47a12beSStefan Roese #define PCIX_COMMAND 0x62 252a47a12beSStefan Roese #define POWAR_EN 0x80000000 253a47a12beSStefan Roese #define POWAR_IO_READ 0x00080000 254a47a12beSStefan Roese #define POWAR_MEM_READ 0x00040000 255a47a12beSStefan Roese #define POWAR_IO_WRITE 0x00008000 256a47a12beSStefan Roese #define POWAR_MEM_WRITE 0x00004000 257a47a12beSStefan Roese #define POWAR_MEM_512M 0x0000001c 258a47a12beSStefan Roese #define POWAR_IO_1M 0x00000013 259a47a12beSStefan Roese 260a47a12beSStefan Roese #define PIWAR_EN 0x80000000 261a47a12beSStefan Roese #define PIWAR_PF 0x20000000 262a47a12beSStefan Roese #define PIWAR_LOCAL 0x00f00000 263a47a12beSStefan Roese #define PIWAR_READ_SNOOP 0x00050000 264a47a12beSStefan Roese #define PIWAR_WRITE_SNOOP 0x00005000 265a47a12beSStefan Roese #define PIWAR_MEM_2G 0x0000001e 266a47a12beSStefan Roese 26707d31f8fSmario.six@gdsys.cc #ifndef CONFIG_MPC85XX_GPIO 268a47a12beSStefan Roese typedef struct ccsr_gpio { 269a47a12beSStefan Roese u32 gpdir; 270a47a12beSStefan Roese u32 gpodr; 271a47a12beSStefan Roese u32 gpdat; 272a47a12beSStefan Roese u32 gpier; 273a47a12beSStefan Roese u32 gpimr; 274a47a12beSStefan Roese u32 gpicr; 275a47a12beSStefan Roese } ccsr_gpio_t; 27607d31f8fSmario.six@gdsys.cc #endif 277a47a12beSStefan Roese 278a47a12beSStefan Roese /* L2 Cache Registers */ 279a47a12beSStefan Roese typedef struct ccsr_l2cache { 280a47a12beSStefan Roese u32 l2ctl; /* L2 configuration 0 */ 281a47a12beSStefan Roese u8 res1[12]; 282a47a12beSStefan Roese u32 l2cewar0; /* L2 cache external write addr 0 */ 283a47a12beSStefan Roese u8 res2[4]; 284a47a12beSStefan Roese u32 l2cewcr0; /* L2 cache external write control 0 */ 285a47a12beSStefan Roese u8 res3[4]; 286a47a12beSStefan Roese u32 l2cewar1; /* L2 cache external write addr 1 */ 287a47a12beSStefan Roese u8 res4[4]; 288a47a12beSStefan Roese u32 l2cewcr1; /* L2 cache external write control 1 */ 289a47a12beSStefan Roese u8 res5[4]; 290a47a12beSStefan Roese u32 l2cewar2; /* L2 cache external write addr 2 */ 291a47a12beSStefan Roese u8 res6[4]; 292a47a12beSStefan Roese u32 l2cewcr2; /* L2 cache external write control 2 */ 293a47a12beSStefan Roese u8 res7[4]; 294a47a12beSStefan Roese u32 l2cewar3; /* L2 cache external write addr 3 */ 295a47a12beSStefan Roese u8 res8[4]; 296a47a12beSStefan Roese u32 l2cewcr3; /* L2 cache external write control 3 */ 297a47a12beSStefan Roese u8 res9[180]; 298a47a12beSStefan Roese u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ 299a47a12beSStefan Roese u8 res10[4]; 300a47a12beSStefan Roese u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ 301a47a12beSStefan Roese u8 res11[3316]; 302a47a12beSStefan Roese u32 l2errinjhi; /* L2 error injection mask high */ 303a47a12beSStefan Roese u32 l2errinjlo; /* L2 error injection mask low */ 304a47a12beSStefan Roese u32 l2errinjctl; /* L2 error injection tag/ECC control */ 305a47a12beSStefan Roese u8 res12[20]; 306a47a12beSStefan Roese u32 l2captdatahi; /* L2 error data high capture */ 307a47a12beSStefan Roese u32 l2captdatalo; /* L2 error data low capture */ 308a47a12beSStefan Roese u32 l2captecc; /* L2 error ECC capture */ 309a47a12beSStefan Roese u8 res13[20]; 310a47a12beSStefan Roese u32 l2errdet; /* L2 error detect */ 311a47a12beSStefan Roese u32 l2errdis; /* L2 error disable */ 312a47a12beSStefan Roese u32 l2errinten; /* L2 error interrupt enable */ 313a47a12beSStefan Roese u32 l2errattr; /* L2 error attributes capture */ 314a47a12beSStefan Roese u32 l2erraddr; /* L2 error addr capture */ 315a47a12beSStefan Roese u8 res14[4]; 316a47a12beSStefan Roese u32 l2errctl; /* L2 error control */ 317a47a12beSStefan Roese u8 res15[420]; 318a47a12beSStefan Roese } ccsr_l2cache_t; 319a47a12beSStefan Roese 320a47a12beSStefan Roese #define MPC85xx_L2CTL_L2E 0x80000000 321a47a12beSStefan Roese #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 322a47a12beSStefan Roese #define MPC85xx_L2ERRDIS_MBECC 0x00000008 323a47a12beSStefan Roese #define MPC85xx_L2ERRDIS_SBECC 0x00000004 324a47a12beSStefan Roese 325a47a12beSStefan Roese /* DMA Registers */ 326a47a12beSStefan Roese typedef struct ccsr_dma { 327a47a12beSStefan Roese u8 res1[256]; 328a47a12beSStefan Roese struct fsl_dma dma[4]; 329a47a12beSStefan Roese u32 dgsr; /* DMA General Status */ 330a47a12beSStefan Roese u8 res2[11516]; 331a47a12beSStefan Roese } ccsr_dma_t; 332a47a12beSStefan Roese 333a47a12beSStefan Roese /* tsec */ 334a47a12beSStefan Roese typedef struct ccsr_tsec { 335a47a12beSStefan Roese u8 res1[16]; 336a47a12beSStefan Roese u32 ievent; /* IRQ Event */ 337a47a12beSStefan Roese u32 imask; /* IRQ Mask */ 338a47a12beSStefan Roese u32 edis; /* Error Disabled */ 339a47a12beSStefan Roese u8 res2[4]; 340a47a12beSStefan Roese u32 ecntrl; /* Ethernet Control */ 341a47a12beSStefan Roese u32 minflr; /* Minimum Frame Len */ 342a47a12beSStefan Roese u32 ptv; /* Pause Time Value */ 343a47a12beSStefan Roese u32 dmactrl; /* DMA Control */ 344a47a12beSStefan Roese u32 tbipa; /* TBI PHY Addr */ 345a47a12beSStefan Roese u8 res3[88]; 346a47a12beSStefan Roese u32 fifo_tx_thr; /* FIFO transmit threshold */ 347a47a12beSStefan Roese u8 res4[8]; 348a47a12beSStefan Roese u32 fifo_tx_starve; /* FIFO transmit starve */ 349a47a12beSStefan Roese u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ 350a47a12beSStefan Roese u8 res5[96]; 351a47a12beSStefan Roese u32 tctrl; /* TX Control */ 352a47a12beSStefan Roese u32 tstat; /* TX Status */ 353a47a12beSStefan Roese u8 res6[4]; 354a47a12beSStefan Roese u32 tbdlen; /* TX Buffer Desc Data Len */ 355a47a12beSStefan Roese u8 res7[16]; 356a47a12beSStefan Roese u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ 357a47a12beSStefan Roese u32 ctbptr; /* Current TX Buffer Desc Ptr */ 358a47a12beSStefan Roese u8 res8[88]; 359a47a12beSStefan Roese u32 tbptrh; /* TX Buffer Desc Ptr High */ 360a47a12beSStefan Roese u32 tbptr; /* TX Buffer Desc Ptr Low */ 361a47a12beSStefan Roese u8 res9[120]; 362a47a12beSStefan Roese u32 tbaseh; /* TX Desc Base Addr High */ 363a47a12beSStefan Roese u32 tbase; /* TX Desc Base Addr */ 364a47a12beSStefan Roese u8 res10[168]; 365a47a12beSStefan Roese u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ 366a47a12beSStefan Roese u32 ostbdp; /* OOS TX Data Buffer Ptr */ 367a47a12beSStefan Roese u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ 368a47a12beSStefan Roese u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ 369a47a12beSStefan Roese u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ 370a47a12beSStefan Roese u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ 371a47a12beSStefan Roese u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ 372a47a12beSStefan Roese u8 res11[52]; 373a47a12beSStefan Roese u32 rctrl; /* RX Control */ 374a47a12beSStefan Roese u32 rstat; /* RX Status */ 375a47a12beSStefan Roese u8 res12[4]; 376a47a12beSStefan Roese u32 rbdlen; /* RxBD Data Len */ 377a47a12beSStefan Roese u8 res13[16]; 378a47a12beSStefan Roese u32 crbptrh; /* Current RX Buffer Desc Ptr High */ 379a47a12beSStefan Roese u32 crbptr; /* Current RX Buffer Desc Ptr */ 380a47a12beSStefan Roese u8 res14[24]; 381a47a12beSStefan Roese u32 mrblr; /* Maximum RX Buffer Len */ 382a47a12beSStefan Roese u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ 383a47a12beSStefan Roese u8 res15[56]; 384a47a12beSStefan Roese u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ 385a47a12beSStefan Roese u32 rbptr; /* RX Buffer Desc Ptr */ 386a47a12beSStefan Roese u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ 387a47a12beSStefan Roese u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ 388a47a12beSStefan Roese u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ 389a47a12beSStefan Roese u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ 390a47a12beSStefan Roese u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ 391a47a12beSStefan Roese u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ 392a47a12beSStefan Roese u8 res16[96]; 393a47a12beSStefan Roese u32 rbaseh; /* RX Desc Base Addr High 0 */ 394a47a12beSStefan Roese u32 rbase; /* RX Desc Base Addr */ 395a47a12beSStefan Roese u32 rbaseh1; /* RX Desc Base Addr High 1 */ 396a47a12beSStefan Roese u32 rbasel1; /* RX Desc Base Addr Low 1 */ 397a47a12beSStefan Roese u32 rbaseh2; /* RX Desc Base Addr High 2 */ 398a47a12beSStefan Roese u32 rbasel2; /* RX Desc Base Addr Low 2 */ 399a47a12beSStefan Roese u32 rbaseh3; /* RX Desc Base Addr High 3 */ 400a47a12beSStefan Roese u32 rbasel3; /* RX Desc Base Addr Low 3 */ 401a47a12beSStefan Roese u8 res17[224]; 402a47a12beSStefan Roese u32 maccfg1; /* MAC Configuration 1 */ 403a47a12beSStefan Roese u32 maccfg2; /* MAC Configuration 2 */ 404a47a12beSStefan Roese u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 405a47a12beSStefan Roese u32 hafdup; /* Half Duplex */ 406a47a12beSStefan Roese u32 maxfrm; /* Maximum Frame Len */ 407a47a12beSStefan Roese u8 res18[12]; 408a47a12beSStefan Roese u32 miimcfg; /* MII Management Configuration */ 409a47a12beSStefan Roese u32 miimcom; /* MII Management Cmd */ 410a47a12beSStefan Roese u32 miimadd; /* MII Management Addr */ 411a47a12beSStefan Roese u32 miimcon; /* MII Management Control */ 412a47a12beSStefan Roese u32 miimstat; /* MII Management Status */ 413a47a12beSStefan Roese u32 miimind; /* MII Management Indicator */ 414a47a12beSStefan Roese u8 res19[4]; 415a47a12beSStefan Roese u32 ifstat; /* Interface Status */ 416a47a12beSStefan Roese u32 macstnaddr1; /* Station Addr Part 1 */ 417a47a12beSStefan Roese u32 macstnaddr2; /* Station Addr Part 2 */ 418a47a12beSStefan Roese u8 res20[312]; 419a47a12beSStefan Roese u32 tr64; /* TX & RX 64-byte Frame Counter */ 420a47a12beSStefan Roese u32 tr127; /* TX & RX 65-127 byte Frame Counter */ 421a47a12beSStefan Roese u32 tr255; /* TX & RX 128-255 byte Frame Counter */ 422a47a12beSStefan Roese u32 tr511; /* TX & RX 256-511 byte Frame Counter */ 423a47a12beSStefan Roese u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ 424a47a12beSStefan Roese u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ 425a47a12beSStefan Roese u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ 426a47a12beSStefan Roese u32 rbyt; /* RX Byte Counter */ 427a47a12beSStefan Roese u32 rpkt; /* RX Packet Counter */ 428a47a12beSStefan Roese u32 rfcs; /* RX FCS Error Counter */ 429a47a12beSStefan Roese u32 rmca; /* RX Multicast Packet Counter */ 430a47a12beSStefan Roese u32 rbca; /* RX Broadcast Packet Counter */ 431a47a12beSStefan Roese u32 rxcf; /* RX Control Frame Packet Counter */ 432a47a12beSStefan Roese u32 rxpf; /* RX Pause Frame Packet Counter */ 433a47a12beSStefan Roese u32 rxuo; /* RX Unknown OP Code Counter */ 434a47a12beSStefan Roese u32 raln; /* RX Alignment Error Counter */ 435a47a12beSStefan Roese u32 rflr; /* RX Frame Len Error Counter */ 436a47a12beSStefan Roese u32 rcde; /* RX Code Error Counter */ 437a47a12beSStefan Roese u32 rcse; /* RX Carrier Sense Error Counter */ 438a47a12beSStefan Roese u32 rund; /* RX Undersize Packet Counter */ 439a47a12beSStefan Roese u32 rovr; /* RX Oversize Packet Counter */ 440a47a12beSStefan Roese u32 rfrg; /* RX Fragments Counter */ 441a47a12beSStefan Roese u32 rjbr; /* RX Jabber Counter */ 442a47a12beSStefan Roese u32 rdrp; /* RX Drop Counter */ 443a47a12beSStefan Roese u32 tbyt; /* TX Byte Counter Counter */ 444a47a12beSStefan Roese u32 tpkt; /* TX Packet Counter */ 445a47a12beSStefan Roese u32 tmca; /* TX Multicast Packet Counter */ 446a47a12beSStefan Roese u32 tbca; /* TX Broadcast Packet Counter */ 447a47a12beSStefan Roese u32 txpf; /* TX Pause Control Frame Counter */ 448a47a12beSStefan Roese u32 tdfr; /* TX Deferral Packet Counter */ 449a47a12beSStefan Roese u32 tedf; /* TX Excessive Deferral Packet Counter */ 450a47a12beSStefan Roese u32 tscl; /* TX Single Collision Packet Counter */ 451a47a12beSStefan Roese u32 tmcl; /* TX Multiple Collision Packet Counter */ 452a47a12beSStefan Roese u32 tlcl; /* TX Late Collision Packet Counter */ 453a47a12beSStefan Roese u32 txcl; /* TX Excessive Collision Packet Counter */ 454a47a12beSStefan Roese u32 tncl; /* TX Total Collision Counter */ 455a47a12beSStefan Roese u8 res21[4]; 456a47a12beSStefan Roese u32 tdrp; /* TX Drop Frame Counter */ 457a47a12beSStefan Roese u32 tjbr; /* TX Jabber Frame Counter */ 458a47a12beSStefan Roese u32 tfcs; /* TX FCS Error Counter */ 459a47a12beSStefan Roese u32 txcf; /* TX Control Frame Counter */ 460a47a12beSStefan Roese u32 tovr; /* TX Oversize Frame Counter */ 461a47a12beSStefan Roese u32 tund; /* TX Undersize Frame Counter */ 462a47a12beSStefan Roese u32 tfrg; /* TX Fragments Frame Counter */ 463a47a12beSStefan Roese u32 car1; /* Carry One */ 464a47a12beSStefan Roese u32 car2; /* Carry Two */ 465a47a12beSStefan Roese u32 cam1; /* Carry Mask One */ 466a47a12beSStefan Roese u32 cam2; /* Carry Mask Two */ 467a47a12beSStefan Roese u8 res22[192]; 468a47a12beSStefan Roese u32 iaddr0; /* Indivdual addr 0 */ 469a47a12beSStefan Roese u32 iaddr1; /* Indivdual addr 1 */ 470a47a12beSStefan Roese u32 iaddr2; /* Indivdual addr 2 */ 471a47a12beSStefan Roese u32 iaddr3; /* Indivdual addr 3 */ 472a47a12beSStefan Roese u32 iaddr4; /* Indivdual addr 4 */ 473a47a12beSStefan Roese u32 iaddr5; /* Indivdual addr 5 */ 474a47a12beSStefan Roese u32 iaddr6; /* Indivdual addr 6 */ 475a47a12beSStefan Roese u32 iaddr7; /* Indivdual addr 7 */ 476a47a12beSStefan Roese u8 res23[96]; 477a47a12beSStefan Roese u32 gaddr0; /* Global addr 0 */ 478a47a12beSStefan Roese u32 gaddr1; /* Global addr 1 */ 479a47a12beSStefan Roese u32 gaddr2; /* Global addr 2 */ 480a47a12beSStefan Roese u32 gaddr3; /* Global addr 3 */ 481a47a12beSStefan Roese u32 gaddr4; /* Global addr 4 */ 482a47a12beSStefan Roese u32 gaddr5; /* Global addr 5 */ 483a47a12beSStefan Roese u32 gaddr6; /* Global addr 6 */ 484a47a12beSStefan Roese u32 gaddr7; /* Global addr 7 */ 485a47a12beSStefan Roese u8 res24[96]; 486a47a12beSStefan Roese u32 pmd0; /* Pattern Match Data */ 487a47a12beSStefan Roese u8 res25[4]; 488a47a12beSStefan Roese u32 pmask0; /* Pattern Mask */ 489a47a12beSStefan Roese u8 res26[4]; 490a47a12beSStefan Roese u32 pcntrl0; /* Pattern Match Control */ 491a47a12beSStefan Roese u8 res27[4]; 492a47a12beSStefan Roese u32 pattrb0; /* Pattern Match Attrs */ 493a47a12beSStefan Roese u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ 494a47a12beSStefan Roese u32 pmd1; /* Pattern Match Data */ 495a47a12beSStefan Roese u8 res28[4]; 496a47a12beSStefan Roese u32 pmask1; /* Pattern Mask */ 497a47a12beSStefan Roese u8 res29[4]; 498a47a12beSStefan Roese u32 pcntrl1; /* Pattern Match Control */ 499a47a12beSStefan Roese u8 res30[4]; 500a47a12beSStefan Roese u32 pattrb1; /* Pattern Match Attrs */ 501a47a12beSStefan Roese u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ 502a47a12beSStefan Roese u32 pmd2; /* Pattern Match Data */ 503a47a12beSStefan Roese u8 res31[4]; 504a47a12beSStefan Roese u32 pmask2; /* Pattern Mask */ 505a47a12beSStefan Roese u8 res32[4]; 506a47a12beSStefan Roese u32 pcntrl2; /* Pattern Match Control */ 507a47a12beSStefan Roese u8 res33[4]; 508a47a12beSStefan Roese u32 pattrb2; /* Pattern Match Attrs */ 509a47a12beSStefan Roese u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ 510a47a12beSStefan Roese u32 pmd3; /* Pattern Match Data */ 511a47a12beSStefan Roese u8 res34[4]; 512a47a12beSStefan Roese u32 pmask3; /* Pattern Mask */ 513a47a12beSStefan Roese u8 res35[4]; 514a47a12beSStefan Roese u32 pcntrl3; /* Pattern Match Control */ 515a47a12beSStefan Roese u8 res36[4]; 516a47a12beSStefan Roese u32 pattrb3; /* Pattern Match Attrs */ 517a47a12beSStefan Roese u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ 518a47a12beSStefan Roese u32 pmd4; /* Pattern Match Data */ 519a47a12beSStefan Roese u8 res37[4]; 520a47a12beSStefan Roese u32 pmask4; /* Pattern Mask */ 521a47a12beSStefan Roese u8 res38[4]; 522a47a12beSStefan Roese u32 pcntrl4; /* Pattern Match Control */ 523a47a12beSStefan Roese u8 res39[4]; 524a47a12beSStefan Roese u32 pattrb4; /* Pattern Match Attrs */ 525a47a12beSStefan Roese u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ 526a47a12beSStefan Roese u32 pmd5; /* Pattern Match Data */ 527a47a12beSStefan Roese u8 res40[4]; 528a47a12beSStefan Roese u32 pmask5; /* Pattern Mask */ 529a47a12beSStefan Roese u8 res41[4]; 530a47a12beSStefan Roese u32 pcntrl5; /* Pattern Match Control */ 531a47a12beSStefan Roese u8 res42[4]; 532a47a12beSStefan Roese u32 pattrb5; /* Pattern Match Attrs */ 533a47a12beSStefan Roese u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ 534a47a12beSStefan Roese u32 pmd6; /* Pattern Match Data */ 535a47a12beSStefan Roese u8 res43[4]; 536a47a12beSStefan Roese u32 pmask6; /* Pattern Mask */ 537a47a12beSStefan Roese u8 res44[4]; 538a47a12beSStefan Roese u32 pcntrl6; /* Pattern Match Control */ 539a47a12beSStefan Roese u8 res45[4]; 540a47a12beSStefan Roese u32 pattrb6; /* Pattern Match Attrs */ 541a47a12beSStefan Roese u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ 542a47a12beSStefan Roese u32 pmd7; /* Pattern Match Data */ 543a47a12beSStefan Roese u8 res46[4]; 544a47a12beSStefan Roese u32 pmask7; /* Pattern Mask */ 545a47a12beSStefan Roese u8 res47[4]; 546a47a12beSStefan Roese u32 pcntrl7; /* Pattern Match Control */ 547a47a12beSStefan Roese u8 res48[4]; 548a47a12beSStefan Roese u32 pattrb7; /* Pattern Match Attrs */ 549a47a12beSStefan Roese u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ 550a47a12beSStefan Roese u32 pmd8; /* Pattern Match Data */ 551a47a12beSStefan Roese u8 res49[4]; 552a47a12beSStefan Roese u32 pmask8; /* Pattern Mask */ 553a47a12beSStefan Roese u8 res50[4]; 554a47a12beSStefan Roese u32 pcntrl8; /* Pattern Match Control */ 555a47a12beSStefan Roese u8 res51[4]; 556a47a12beSStefan Roese u32 pattrb8; /* Pattern Match Attrs */ 557a47a12beSStefan Roese u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ 558a47a12beSStefan Roese u32 pmd9; /* Pattern Match Data */ 559a47a12beSStefan Roese u8 res52[4]; 560a47a12beSStefan Roese u32 pmask9; /* Pattern Mask */ 561a47a12beSStefan Roese u8 res53[4]; 562a47a12beSStefan Roese u32 pcntrl9; /* Pattern Match Control */ 563a47a12beSStefan Roese u8 res54[4]; 564a47a12beSStefan Roese u32 pattrb9; /* Pattern Match Attrs */ 565a47a12beSStefan Roese u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ 566a47a12beSStefan Roese u32 pmd10; /* Pattern Match Data */ 567a47a12beSStefan Roese u8 res55[4]; 568a47a12beSStefan Roese u32 pmask10; /* Pattern Mask */ 569a47a12beSStefan Roese u8 res56[4]; 570a47a12beSStefan Roese u32 pcntrl10; /* Pattern Match Control */ 571a47a12beSStefan Roese u8 res57[4]; 572a47a12beSStefan Roese u32 pattrb10; /* Pattern Match Attrs */ 573a47a12beSStefan Roese u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ 574a47a12beSStefan Roese u32 pmd11; /* Pattern Match Data */ 575a47a12beSStefan Roese u8 res58[4]; 576a47a12beSStefan Roese u32 pmask11; /* Pattern Mask */ 577a47a12beSStefan Roese u8 res59[4]; 578a47a12beSStefan Roese u32 pcntrl11; /* Pattern Match Control */ 579a47a12beSStefan Roese u8 res60[4]; 580a47a12beSStefan Roese u32 pattrb11; /* Pattern Match Attrs */ 581a47a12beSStefan Roese u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ 582a47a12beSStefan Roese u32 pmd12; /* Pattern Match Data */ 583a47a12beSStefan Roese u8 res61[4]; 584a47a12beSStefan Roese u32 pmask12; /* Pattern Mask */ 585a47a12beSStefan Roese u8 res62[4]; 586a47a12beSStefan Roese u32 pcntrl12; /* Pattern Match Control */ 587a47a12beSStefan Roese u8 res63[4]; 588a47a12beSStefan Roese u32 pattrb12; /* Pattern Match Attrs */ 589a47a12beSStefan Roese u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ 590a47a12beSStefan Roese u32 pmd13; /* Pattern Match Data */ 591a47a12beSStefan Roese u8 res64[4]; 592a47a12beSStefan Roese u32 pmask13; /* Pattern Mask */ 593a47a12beSStefan Roese u8 res65[4]; 594a47a12beSStefan Roese u32 pcntrl13; /* Pattern Match Control */ 595a47a12beSStefan Roese u8 res66[4]; 596a47a12beSStefan Roese u32 pattrb13; /* Pattern Match Attrs */ 597a47a12beSStefan Roese u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ 598a47a12beSStefan Roese u32 pmd14; /* Pattern Match Data */ 599a47a12beSStefan Roese u8 res67[4]; 600a47a12beSStefan Roese u32 pmask14; /* Pattern Mask */ 601a47a12beSStefan Roese u8 res68[4]; 602a47a12beSStefan Roese u32 pcntrl14; /* Pattern Match Control */ 603a47a12beSStefan Roese u8 res69[4]; 604a47a12beSStefan Roese u32 pattrb14; /* Pattern Match Attrs */ 605a47a12beSStefan Roese u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ 606a47a12beSStefan Roese u32 pmd15; /* Pattern Match Data */ 607a47a12beSStefan Roese u8 res70[4]; 608a47a12beSStefan Roese u32 pmask15; /* Pattern Mask */ 609a47a12beSStefan Roese u8 res71[4]; 610a47a12beSStefan Roese u32 pcntrl15; /* Pattern Match Control */ 611a47a12beSStefan Roese u8 res72[4]; 612a47a12beSStefan Roese u32 pattrb15; /* Pattern Match Attrs */ 613a47a12beSStefan Roese u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ 614a47a12beSStefan Roese u8 res73[248]; 615a47a12beSStefan Roese u32 attr; /* Attrs */ 616a47a12beSStefan Roese u32 attreli; /* Attrs Extract Len & Idx */ 617a47a12beSStefan Roese u8 res74[1024]; 618a47a12beSStefan Roese } ccsr_tsec_t; 619a47a12beSStefan Roese 620a47a12beSStefan Roese /* PIC Registers */ 621a47a12beSStefan Roese typedef struct ccsr_pic { 622a47a12beSStefan Roese u8 res1[64]; 623a47a12beSStefan Roese u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ 624a47a12beSStefan Roese u8 res2[12]; 625a47a12beSStefan Roese u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ 626a47a12beSStefan Roese u8 res3[12]; 627a47a12beSStefan Roese u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ 628a47a12beSStefan Roese u8 res4[12]; 629a47a12beSStefan Roese u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ 630a47a12beSStefan Roese u8 res5[12]; 631a47a12beSStefan Roese u32 ctpr; /* Current Task Priority */ 632a47a12beSStefan Roese u8 res6[12]; 633a47a12beSStefan Roese u32 whoami; /* Who Am I */ 634a47a12beSStefan Roese u8 res7[12]; 635a47a12beSStefan Roese u32 iack; /* IRQ Acknowledge */ 636a47a12beSStefan Roese u8 res8[12]; 637a47a12beSStefan Roese u32 eoi; /* End Of IRQ */ 638a47a12beSStefan Roese u8 res9[3916]; 639a47a12beSStefan Roese u32 frr; /* Feature Reporting */ 640a47a12beSStefan Roese u8 res10[28]; 641a47a12beSStefan Roese u32 gcr; /* Global Configuration */ 642a47a12beSStefan Roese #define MPC85xx_PICGCR_RST 0x80000000 643a47a12beSStefan Roese #define MPC85xx_PICGCR_M 0x20000000 644a47a12beSStefan Roese u8 res11[92]; 645a47a12beSStefan Roese u32 vir; /* Vendor Identification */ 646a47a12beSStefan Roese u8 res12[12]; 647a47a12beSStefan Roese u32 pir; /* Processor Initialization */ 648a47a12beSStefan Roese u8 res13[12]; 649a47a12beSStefan Roese u32 ipivpr0; /* IPI Vector/Priority 0 */ 650a47a12beSStefan Roese u8 res14[12]; 651a47a12beSStefan Roese u32 ipivpr1; /* IPI Vector/Priority 1 */ 652a47a12beSStefan Roese u8 res15[12]; 653a47a12beSStefan Roese u32 ipivpr2; /* IPI Vector/Priority 2 */ 654a47a12beSStefan Roese u8 res16[12]; 655a47a12beSStefan Roese u32 ipivpr3; /* IPI Vector/Priority 3 */ 656a47a12beSStefan Roese u8 res17[12]; 657a47a12beSStefan Roese u32 svr; /* Spurious Vector */ 658a47a12beSStefan Roese u8 res18[12]; 659a47a12beSStefan Roese u32 tfrr; /* Timer Frequency Reporting */ 660a47a12beSStefan Roese u8 res19[12]; 661a47a12beSStefan Roese u32 gtccr0; /* Global Timer Current Count 0 */ 662a47a12beSStefan Roese u8 res20[12]; 663a47a12beSStefan Roese u32 gtbcr0; /* Global Timer Base Count 0 */ 664a47a12beSStefan Roese u8 res21[12]; 665a47a12beSStefan Roese u32 gtvpr0; /* Global Timer Vector/Priority 0 */ 666a47a12beSStefan Roese u8 res22[12]; 667a47a12beSStefan Roese u32 gtdr0; /* Global Timer Destination 0 */ 668a47a12beSStefan Roese u8 res23[12]; 669a47a12beSStefan Roese u32 gtccr1; /* Global Timer Current Count 1 */ 670a47a12beSStefan Roese u8 res24[12]; 671a47a12beSStefan Roese u32 gtbcr1; /* Global Timer Base Count 1 */ 672a47a12beSStefan Roese u8 res25[12]; 673a47a12beSStefan Roese u32 gtvpr1; /* Global Timer Vector/Priority 1 */ 674a47a12beSStefan Roese u8 res26[12]; 675a47a12beSStefan Roese u32 gtdr1; /* Global Timer Destination 1 */ 676a47a12beSStefan Roese u8 res27[12]; 677a47a12beSStefan Roese u32 gtccr2; /* Global Timer Current Count 2 */ 678a47a12beSStefan Roese u8 res28[12]; 679a47a12beSStefan Roese u32 gtbcr2; /* Global Timer Base Count 2 */ 680a47a12beSStefan Roese u8 res29[12]; 681a47a12beSStefan Roese u32 gtvpr2; /* Global Timer Vector/Priority 2 */ 682a47a12beSStefan Roese u8 res30[12]; 683a47a12beSStefan Roese u32 gtdr2; /* Global Timer Destination 2 */ 684a47a12beSStefan Roese u8 res31[12]; 685a47a12beSStefan Roese u32 gtccr3; /* Global Timer Current Count 3 */ 686a47a12beSStefan Roese u8 res32[12]; 687a47a12beSStefan Roese u32 gtbcr3; /* Global Timer Base Count 3 */ 688a47a12beSStefan Roese u8 res33[12]; 689a47a12beSStefan Roese u32 gtvpr3; /* Global Timer Vector/Priority 3 */ 690a47a12beSStefan Roese u8 res34[12]; 691a47a12beSStefan Roese u32 gtdr3; /* Global Timer Destination 3 */ 692a47a12beSStefan Roese u8 res35[268]; 693a47a12beSStefan Roese u32 tcr; /* Timer Control */ 694a47a12beSStefan Roese u8 res36[12]; 695a47a12beSStefan Roese u32 irqsr0; /* IRQ_OUT Summary 0 */ 696a47a12beSStefan Roese u8 res37[12]; 697a47a12beSStefan Roese u32 irqsr1; /* IRQ_OUT Summary 1 */ 698a47a12beSStefan Roese u8 res38[12]; 699a47a12beSStefan Roese u32 cisr0; /* Critical IRQ Summary 0 */ 700a47a12beSStefan Roese u8 res39[12]; 701a47a12beSStefan Roese u32 cisr1; /* Critical IRQ Summary 1 */ 702a47a12beSStefan Roese u8 res40[188]; 703a47a12beSStefan Roese u32 msgr0; /* Message 0 */ 704a47a12beSStefan Roese u8 res41[12]; 705a47a12beSStefan Roese u32 msgr1; /* Message 1 */ 706a47a12beSStefan Roese u8 res42[12]; 707a47a12beSStefan Roese u32 msgr2; /* Message 2 */ 708a47a12beSStefan Roese u8 res43[12]; 709a47a12beSStefan Roese u32 msgr3; /* Message 3 */ 710a47a12beSStefan Roese u8 res44[204]; 711a47a12beSStefan Roese u32 mer; /* Message Enable */ 712a47a12beSStefan Roese u8 res45[12]; 713a47a12beSStefan Roese u32 msr; /* Message Status */ 714a47a12beSStefan Roese u8 res46[60140]; 715a47a12beSStefan Roese u32 eivpr0; /* External IRQ Vector/Priority 0 */ 716a47a12beSStefan Roese u8 res47[12]; 717a47a12beSStefan Roese u32 eidr0; /* External IRQ Destination 0 */ 718a47a12beSStefan Roese u8 res48[12]; 719a47a12beSStefan Roese u32 eivpr1; /* External IRQ Vector/Priority 1 */ 720a47a12beSStefan Roese u8 res49[12]; 721a47a12beSStefan Roese u32 eidr1; /* External IRQ Destination 1 */ 722a47a12beSStefan Roese u8 res50[12]; 723a47a12beSStefan Roese u32 eivpr2; /* External IRQ Vector/Priority 2 */ 724a47a12beSStefan Roese u8 res51[12]; 725a47a12beSStefan Roese u32 eidr2; /* External IRQ Destination 2 */ 726a47a12beSStefan Roese u8 res52[12]; 727a47a12beSStefan Roese u32 eivpr3; /* External IRQ Vector/Priority 3 */ 728a47a12beSStefan Roese u8 res53[12]; 729a47a12beSStefan Roese u32 eidr3; /* External IRQ Destination 3 */ 730a47a12beSStefan Roese u8 res54[12]; 731a47a12beSStefan Roese u32 eivpr4; /* External IRQ Vector/Priority 4 */ 732a47a12beSStefan Roese u8 res55[12]; 733a47a12beSStefan Roese u32 eidr4; /* External IRQ Destination 4 */ 734a47a12beSStefan Roese u8 res56[12]; 735a47a12beSStefan Roese u32 eivpr5; /* External IRQ Vector/Priority 5 */ 736a47a12beSStefan Roese u8 res57[12]; 737a47a12beSStefan Roese u32 eidr5; /* External IRQ Destination 5 */ 738a47a12beSStefan Roese u8 res58[12]; 739a47a12beSStefan Roese u32 eivpr6; /* External IRQ Vector/Priority 6 */ 740a47a12beSStefan Roese u8 res59[12]; 741a47a12beSStefan Roese u32 eidr6; /* External IRQ Destination 6 */ 742a47a12beSStefan Roese u8 res60[12]; 743a47a12beSStefan Roese u32 eivpr7; /* External IRQ Vector/Priority 7 */ 744a47a12beSStefan Roese u8 res61[12]; 745a47a12beSStefan Roese u32 eidr7; /* External IRQ Destination 7 */ 746a47a12beSStefan Roese u8 res62[12]; 747a47a12beSStefan Roese u32 eivpr8; /* External IRQ Vector/Priority 8 */ 748a47a12beSStefan Roese u8 res63[12]; 749a47a12beSStefan Roese u32 eidr8; /* External IRQ Destination 8 */ 750a47a12beSStefan Roese u8 res64[12]; 751a47a12beSStefan Roese u32 eivpr9; /* External IRQ Vector/Priority 9 */ 752a47a12beSStefan Roese u8 res65[12]; 753a47a12beSStefan Roese u32 eidr9; /* External IRQ Destination 9 */ 754a47a12beSStefan Roese u8 res66[12]; 755a47a12beSStefan Roese u32 eivpr10; /* External IRQ Vector/Priority 10 */ 756a47a12beSStefan Roese u8 res67[12]; 757a47a12beSStefan Roese u32 eidr10; /* External IRQ Destination 10 */ 758a47a12beSStefan Roese u8 res68[12]; 759a47a12beSStefan Roese u32 eivpr11; /* External IRQ Vector/Priority 11 */ 760a47a12beSStefan Roese u8 res69[12]; 761a47a12beSStefan Roese u32 eidr11; /* External IRQ Destination 11 */ 762a47a12beSStefan Roese u8 res70[140]; 763a47a12beSStefan Roese u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ 764a47a12beSStefan Roese u8 res71[12]; 765a47a12beSStefan Roese u32 iidr0; /* Internal IRQ Destination 0 */ 766a47a12beSStefan Roese u8 res72[12]; 767a47a12beSStefan Roese u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ 768a47a12beSStefan Roese u8 res73[12]; 769a47a12beSStefan Roese u32 iidr1; /* Internal IRQ Destination 1 */ 770a47a12beSStefan Roese u8 res74[12]; 771a47a12beSStefan Roese u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ 772a47a12beSStefan Roese u8 res75[12]; 773a47a12beSStefan Roese u32 iidr2; /* Internal IRQ Destination 2 */ 774a47a12beSStefan Roese u8 res76[12]; 775a47a12beSStefan Roese u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ 776a47a12beSStefan Roese u8 res77[12]; 777a47a12beSStefan Roese u32 iidr3; /* Internal IRQ Destination 3 */ 778a47a12beSStefan Roese u8 res78[12]; 779a47a12beSStefan Roese u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ 780a47a12beSStefan Roese u8 res79[12]; 781a47a12beSStefan Roese u32 iidr4; /* Internal IRQ Destination 4 */ 782a47a12beSStefan Roese u8 res80[12]; 783a47a12beSStefan Roese u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ 784a47a12beSStefan Roese u8 res81[12]; 785a47a12beSStefan Roese u32 iidr5; /* Internal IRQ Destination 5 */ 786a47a12beSStefan Roese u8 res82[12]; 787a47a12beSStefan Roese u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ 788a47a12beSStefan Roese u8 res83[12]; 789a47a12beSStefan Roese u32 iidr6; /* Internal IRQ Destination 6 */ 790a47a12beSStefan Roese u8 res84[12]; 791a47a12beSStefan Roese u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ 792a47a12beSStefan Roese u8 res85[12]; 793a47a12beSStefan Roese u32 iidr7; /* Internal IRQ Destination 7 */ 794a47a12beSStefan Roese u8 res86[12]; 795a47a12beSStefan Roese u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ 796a47a12beSStefan Roese u8 res87[12]; 797a47a12beSStefan Roese u32 iidr8; /* Internal IRQ Destination 8 */ 798a47a12beSStefan Roese u8 res88[12]; 799a47a12beSStefan Roese u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ 800a47a12beSStefan Roese u8 res89[12]; 801a47a12beSStefan Roese u32 iidr9; /* Internal IRQ Destination 9 */ 802a47a12beSStefan Roese u8 res90[12]; 803a47a12beSStefan Roese u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ 804a47a12beSStefan Roese u8 res91[12]; 805a47a12beSStefan Roese u32 iidr10; /* Internal IRQ Destination 10 */ 806a47a12beSStefan Roese u8 res92[12]; 807a47a12beSStefan Roese u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ 808a47a12beSStefan Roese u8 res93[12]; 809a47a12beSStefan Roese u32 iidr11; /* Internal IRQ Destination 11 */ 810a47a12beSStefan Roese u8 res94[12]; 811a47a12beSStefan Roese u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ 812a47a12beSStefan Roese u8 res95[12]; 813a47a12beSStefan Roese u32 iidr12; /* Internal IRQ Destination 12 */ 814a47a12beSStefan Roese u8 res96[12]; 815a47a12beSStefan Roese u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ 816a47a12beSStefan Roese u8 res97[12]; 817a47a12beSStefan Roese u32 iidr13; /* Internal IRQ Destination 13 */ 818a47a12beSStefan Roese u8 res98[12]; 819a47a12beSStefan Roese u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ 820a47a12beSStefan Roese u8 res99[12]; 821a47a12beSStefan Roese u32 iidr14; /* Internal IRQ Destination 14 */ 822a47a12beSStefan Roese u8 res100[12]; 823a47a12beSStefan Roese u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ 824a47a12beSStefan Roese u8 res101[12]; 825a47a12beSStefan Roese u32 iidr15; /* Internal IRQ Destination 15 */ 826a47a12beSStefan Roese u8 res102[12]; 827a47a12beSStefan Roese u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ 828a47a12beSStefan Roese u8 res103[12]; 829a47a12beSStefan Roese u32 iidr16; /* Internal IRQ Destination 16 */ 830a47a12beSStefan Roese u8 res104[12]; 831a47a12beSStefan Roese u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ 832a47a12beSStefan Roese u8 res105[12]; 833a47a12beSStefan Roese u32 iidr17; /* Internal IRQ Destination 17 */ 834a47a12beSStefan Roese u8 res106[12]; 835a47a12beSStefan Roese u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ 836a47a12beSStefan Roese u8 res107[12]; 837a47a12beSStefan Roese u32 iidr18; /* Internal IRQ Destination 18 */ 838a47a12beSStefan Roese u8 res108[12]; 839a47a12beSStefan Roese u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ 840a47a12beSStefan Roese u8 res109[12]; 841a47a12beSStefan Roese u32 iidr19; /* Internal IRQ Destination 19 */ 842a47a12beSStefan Roese u8 res110[12]; 843a47a12beSStefan Roese u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ 844a47a12beSStefan Roese u8 res111[12]; 845a47a12beSStefan Roese u32 iidr20; /* Internal IRQ Destination 20 */ 846a47a12beSStefan Roese u8 res112[12]; 847a47a12beSStefan Roese u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ 848a47a12beSStefan Roese u8 res113[12]; 849a47a12beSStefan Roese u32 iidr21; /* Internal IRQ Destination 21 */ 850a47a12beSStefan Roese u8 res114[12]; 851a47a12beSStefan Roese u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ 852a47a12beSStefan Roese u8 res115[12]; 853a47a12beSStefan Roese u32 iidr22; /* Internal IRQ Destination 22 */ 854a47a12beSStefan Roese u8 res116[12]; 855a47a12beSStefan Roese u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ 856a47a12beSStefan Roese u8 res117[12]; 857a47a12beSStefan Roese u32 iidr23; /* Internal IRQ Destination 23 */ 858a47a12beSStefan Roese u8 res118[12]; 859a47a12beSStefan Roese u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ 860a47a12beSStefan Roese u8 res119[12]; 861a47a12beSStefan Roese u32 iidr24; /* Internal IRQ Destination 24 */ 862a47a12beSStefan Roese u8 res120[12]; 863a47a12beSStefan Roese u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ 864a47a12beSStefan Roese u8 res121[12]; 865a47a12beSStefan Roese u32 iidr25; /* Internal IRQ Destination 25 */ 866a47a12beSStefan Roese u8 res122[12]; 867a47a12beSStefan Roese u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ 868a47a12beSStefan Roese u8 res123[12]; 869a47a12beSStefan Roese u32 iidr26; /* Internal IRQ Destination 26 */ 870a47a12beSStefan Roese u8 res124[12]; 871a47a12beSStefan Roese u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ 872a47a12beSStefan Roese u8 res125[12]; 873a47a12beSStefan Roese u32 iidr27; /* Internal IRQ Destination 27 */ 874a47a12beSStefan Roese u8 res126[12]; 875a47a12beSStefan Roese u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ 876a47a12beSStefan Roese u8 res127[12]; 877a47a12beSStefan Roese u32 iidr28; /* Internal IRQ Destination 28 */ 878a47a12beSStefan Roese u8 res128[12]; 879a47a12beSStefan Roese u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ 880a47a12beSStefan Roese u8 res129[12]; 881a47a12beSStefan Roese u32 iidr29; /* Internal IRQ Destination 29 */ 882a47a12beSStefan Roese u8 res130[12]; 883a47a12beSStefan Roese u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ 884a47a12beSStefan Roese u8 res131[12]; 885a47a12beSStefan Roese u32 iidr30; /* Internal IRQ Destination 30 */ 886a47a12beSStefan Roese u8 res132[12]; 887a47a12beSStefan Roese u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ 888a47a12beSStefan Roese u8 res133[12]; 889a47a12beSStefan Roese u32 iidr31; /* Internal IRQ Destination 31 */ 890a47a12beSStefan Roese u8 res134[4108]; 891a47a12beSStefan Roese u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ 892a47a12beSStefan Roese u8 res135[12]; 893a47a12beSStefan Roese u32 midr0; /* Messaging IRQ Destination 0 */ 894a47a12beSStefan Roese u8 res136[12]; 895a47a12beSStefan Roese u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ 896a47a12beSStefan Roese u8 res137[12]; 897a47a12beSStefan Roese u32 midr1; /* Messaging IRQ Destination 1 */ 898a47a12beSStefan Roese u8 res138[12]; 899a47a12beSStefan Roese u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ 900a47a12beSStefan Roese u8 res139[12]; 901a47a12beSStefan Roese u32 midr2; /* Messaging IRQ Destination 2 */ 902a47a12beSStefan Roese u8 res140[12]; 903a47a12beSStefan Roese u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ 904a47a12beSStefan Roese u8 res141[12]; 905a47a12beSStefan Roese u32 midr3; /* Messaging IRQ Destination 3 */ 906a47a12beSStefan Roese u8 res142[59852]; 907a47a12beSStefan Roese u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ 908a47a12beSStefan Roese u8 res143[12]; 909a47a12beSStefan Roese u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ 910a47a12beSStefan Roese u8 res144[12]; 911a47a12beSStefan Roese u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ 912a47a12beSStefan Roese u8 res145[12]; 913a47a12beSStefan Roese u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ 914a47a12beSStefan Roese u8 res146[12]; 915a47a12beSStefan Roese u32 ctpr0; /* Current Task Priority for Processor 0 */ 916a47a12beSStefan Roese u8 res147[12]; 917a47a12beSStefan Roese u32 whoami0; /* Who Am I for Processor 0 */ 918a47a12beSStefan Roese u8 res148[12]; 919a47a12beSStefan Roese u32 iack0; /* IRQ Acknowledge for Processor 0 */ 920a47a12beSStefan Roese u8 res149[12]; 921a47a12beSStefan Roese u32 eoi0; /* End Of IRQ for Processor 0 */ 922a47a12beSStefan Roese u8 res150[130892]; 923a47a12beSStefan Roese } ccsr_pic_t; 924a47a12beSStefan Roese 925a47a12beSStefan Roese /* CPM Block */ 926a47a12beSStefan Roese #ifndef CONFIG_CPM2 927a47a12beSStefan Roese typedef struct ccsr_cpm { 928a47a12beSStefan Roese u8 res[262144]; 929a47a12beSStefan Roese } ccsr_cpm_t; 930a47a12beSStefan Roese #else 931a47a12beSStefan Roese /* 932a47a12beSStefan Roese * DPARM 933a47a12beSStefan Roese * General SIU 934a47a12beSStefan Roese */ 935a47a12beSStefan Roese typedef struct ccsr_cpm_siu { 936a47a12beSStefan Roese u8 res1[80]; 937a47a12beSStefan Roese u32 smaer; 938a47a12beSStefan Roese u32 smser; 939a47a12beSStefan Roese u32 smevr; 940a47a12beSStefan Roese u8 res2[4]; 941a47a12beSStefan Roese u32 lmaer; 942a47a12beSStefan Roese u32 lmser; 943a47a12beSStefan Roese u32 lmevr; 944a47a12beSStefan Roese u8 res3[2964]; 945a47a12beSStefan Roese } ccsr_cpm_siu_t; 946a47a12beSStefan Roese 947a47a12beSStefan Roese /* IRQ Controller */ 948a47a12beSStefan Roese typedef struct ccsr_cpm_intctl { 949a47a12beSStefan Roese u16 sicr; 950a47a12beSStefan Roese u8 res1[2]; 951a47a12beSStefan Roese u32 sivec; 952a47a12beSStefan Roese u32 sipnrh; 953a47a12beSStefan Roese u32 sipnrl; 954a47a12beSStefan Roese u32 siprr; 955a47a12beSStefan Roese u32 scprrh; 956a47a12beSStefan Roese u32 scprrl; 957a47a12beSStefan Roese u32 simrh; 958a47a12beSStefan Roese u32 simrl; 959a47a12beSStefan Roese u32 siexr; 960a47a12beSStefan Roese u8 res2[88]; 961a47a12beSStefan Roese u32 sccr; 962a47a12beSStefan Roese u8 res3[124]; 963a47a12beSStefan Roese } ccsr_cpm_intctl_t; 964a47a12beSStefan Roese 965a47a12beSStefan Roese /* input/output port */ 966a47a12beSStefan Roese typedef struct ccsr_cpm_iop { 967a47a12beSStefan Roese u32 pdira; 968a47a12beSStefan Roese u32 ppara; 969a47a12beSStefan Roese u32 psora; 970a47a12beSStefan Roese u32 podra; 971a47a12beSStefan Roese u32 pdata; 972a47a12beSStefan Roese u8 res1[12]; 973a47a12beSStefan Roese u32 pdirb; 974a47a12beSStefan Roese u32 pparb; 975a47a12beSStefan Roese u32 psorb; 976a47a12beSStefan Roese u32 podrb; 977a47a12beSStefan Roese u32 pdatb; 978a47a12beSStefan Roese u8 res2[12]; 979a47a12beSStefan Roese u32 pdirc; 980a47a12beSStefan Roese u32 pparc; 981a47a12beSStefan Roese u32 psorc; 982a47a12beSStefan Roese u32 podrc; 983a47a12beSStefan Roese u32 pdatc; 984a47a12beSStefan Roese u8 res3[12]; 985a47a12beSStefan Roese u32 pdird; 986a47a12beSStefan Roese u32 ppard; 987a47a12beSStefan Roese u32 psord; 988a47a12beSStefan Roese u32 podrd; 989a47a12beSStefan Roese u32 pdatd; 990a47a12beSStefan Roese u8 res4[12]; 991a47a12beSStefan Roese } ccsr_cpm_iop_t; 992a47a12beSStefan Roese 993a47a12beSStefan Roese /* CPM timers */ 994a47a12beSStefan Roese typedef struct ccsr_cpm_timer { 995a47a12beSStefan Roese u8 tgcr1; 996a47a12beSStefan Roese u8 res1[3]; 997a47a12beSStefan Roese u8 tgcr2; 998a47a12beSStefan Roese u8 res2[11]; 999a47a12beSStefan Roese u16 tmr1; 1000a47a12beSStefan Roese u16 tmr2; 1001a47a12beSStefan Roese u16 trr1; 1002a47a12beSStefan Roese u16 trr2; 1003a47a12beSStefan Roese u16 tcr1; 1004a47a12beSStefan Roese u16 tcr2; 1005a47a12beSStefan Roese u16 tcn1; 1006a47a12beSStefan Roese u16 tcn2; 1007a47a12beSStefan Roese u16 tmr3; 1008a47a12beSStefan Roese u16 tmr4; 1009a47a12beSStefan Roese u16 trr3; 1010a47a12beSStefan Roese u16 trr4; 1011a47a12beSStefan Roese u16 tcr3; 1012a47a12beSStefan Roese u16 tcr4; 1013a47a12beSStefan Roese u16 tcn3; 1014a47a12beSStefan Roese u16 tcn4; 1015a47a12beSStefan Roese u16 ter1; 1016a47a12beSStefan Roese u16 ter2; 1017a47a12beSStefan Roese u16 ter3; 1018a47a12beSStefan Roese u16 ter4; 1019a47a12beSStefan Roese u8 res3[608]; 1020a47a12beSStefan Roese } ccsr_cpm_timer_t; 1021a47a12beSStefan Roese 1022a47a12beSStefan Roese /* SDMA */ 1023a47a12beSStefan Roese typedef struct ccsr_cpm_sdma { 1024a47a12beSStefan Roese u8 sdsr; 1025a47a12beSStefan Roese u8 res1[3]; 1026a47a12beSStefan Roese u8 sdmr; 1027a47a12beSStefan Roese u8 res2[739]; 1028a47a12beSStefan Roese } ccsr_cpm_sdma_t; 1029a47a12beSStefan Roese 1030a47a12beSStefan Roese /* FCC1 */ 1031a47a12beSStefan Roese typedef struct ccsr_cpm_fcc1 { 1032a47a12beSStefan Roese u32 gfmr; 1033a47a12beSStefan Roese u32 fpsmr; 1034a47a12beSStefan Roese u16 ftodr; 1035a47a12beSStefan Roese u8 res1[2]; 1036a47a12beSStefan Roese u16 fdsr; 1037a47a12beSStefan Roese u8 res2[2]; 1038a47a12beSStefan Roese u16 fcce; 1039a47a12beSStefan Roese u8 res3[2]; 1040a47a12beSStefan Roese u16 fccm; 1041a47a12beSStefan Roese u8 res4[2]; 1042a47a12beSStefan Roese u8 fccs; 1043a47a12beSStefan Roese u8 res5[3]; 1044a47a12beSStefan Roese u8 ftirr_phy[4]; 1045a47a12beSStefan Roese } ccsr_cpm_fcc1_t; 1046a47a12beSStefan Roese 1047a47a12beSStefan Roese /* FCC2 */ 1048a47a12beSStefan Roese typedef struct ccsr_cpm_fcc2 { 1049a47a12beSStefan Roese u32 gfmr; 1050a47a12beSStefan Roese u32 fpsmr; 1051a47a12beSStefan Roese u16 ftodr; 1052a47a12beSStefan Roese u8 res1[2]; 1053a47a12beSStefan Roese u16 fdsr; 1054a47a12beSStefan Roese u8 res2[2]; 1055a47a12beSStefan Roese u16 fcce; 1056a47a12beSStefan Roese u8 res3[2]; 1057a47a12beSStefan Roese u16 fccm; 1058a47a12beSStefan Roese u8 res4[2]; 1059a47a12beSStefan Roese u8 fccs; 1060a47a12beSStefan Roese u8 res5[3]; 1061a47a12beSStefan Roese u8 ftirr_phy[4]; 1062a47a12beSStefan Roese } ccsr_cpm_fcc2_t; 1063a47a12beSStefan Roese 1064a47a12beSStefan Roese /* FCC3 */ 1065a47a12beSStefan Roese typedef struct ccsr_cpm_fcc3 { 1066a47a12beSStefan Roese u32 gfmr; 1067a47a12beSStefan Roese u32 fpsmr; 1068a47a12beSStefan Roese u16 ftodr; 1069a47a12beSStefan Roese u8 res1[2]; 1070a47a12beSStefan Roese u16 fdsr; 1071a47a12beSStefan Roese u8 res2[2]; 1072a47a12beSStefan Roese u16 fcce; 1073a47a12beSStefan Roese u8 res3[2]; 1074a47a12beSStefan Roese u16 fccm; 1075a47a12beSStefan Roese u8 res4[2]; 1076a47a12beSStefan Roese u8 fccs; 1077a47a12beSStefan Roese u8 res5[3]; 1078a47a12beSStefan Roese u8 res[36]; 1079a47a12beSStefan Roese } ccsr_cpm_fcc3_t; 1080a47a12beSStefan Roese 1081a47a12beSStefan Roese /* FCC1 extended */ 1082a47a12beSStefan Roese typedef struct ccsr_cpm_fcc1_ext { 1083a47a12beSStefan Roese u32 firper; 1084a47a12beSStefan Roese u32 firer; 1085a47a12beSStefan Roese u32 firsr_h; 1086a47a12beSStefan Roese u32 firsr_l; 1087a47a12beSStefan Roese u8 gfemr; 1088a47a12beSStefan Roese u8 res[15]; 1089a47a12beSStefan Roese 1090a47a12beSStefan Roese } ccsr_cpm_fcc1_ext_t; 1091a47a12beSStefan Roese 1092a47a12beSStefan Roese /* FCC2 extended */ 1093a47a12beSStefan Roese typedef struct ccsr_cpm_fcc2_ext { 1094a47a12beSStefan Roese u32 firper; 1095a47a12beSStefan Roese u32 firer; 1096a47a12beSStefan Roese u32 firsr_h; 1097a47a12beSStefan Roese u32 firsr_l; 1098a47a12beSStefan Roese u8 gfemr; 1099a47a12beSStefan Roese u8 res[31]; 1100a47a12beSStefan Roese } ccsr_cpm_fcc2_ext_t; 1101a47a12beSStefan Roese 1102a47a12beSStefan Roese /* FCC3 extended */ 1103a47a12beSStefan Roese typedef struct ccsr_cpm_fcc3_ext { 1104a47a12beSStefan Roese u8 gfemr; 1105a47a12beSStefan Roese u8 res[47]; 1106a47a12beSStefan Roese } ccsr_cpm_fcc3_ext_t; 1107a47a12beSStefan Roese 1108a47a12beSStefan Roese /* TC layers */ 1109a47a12beSStefan Roese typedef struct ccsr_cpm_tmp1 { 1110a47a12beSStefan Roese u8 res[496]; 1111a47a12beSStefan Roese } ccsr_cpm_tmp1_t; 1112a47a12beSStefan Roese 1113a47a12beSStefan Roese /* BRGs:5,6,7,8 */ 1114a47a12beSStefan Roese typedef struct ccsr_cpm_brg2 { 1115a47a12beSStefan Roese u32 brgc5; 1116a47a12beSStefan Roese u32 brgc6; 1117a47a12beSStefan Roese u32 brgc7; 1118a47a12beSStefan Roese u32 brgc8; 1119a47a12beSStefan Roese u8 res[608]; 1120a47a12beSStefan Roese } ccsr_cpm_brg2_t; 1121a47a12beSStefan Roese 1122a47a12beSStefan Roese /* I2C */ 1123a47a12beSStefan Roese typedef struct ccsr_cpm_i2c { 1124a47a12beSStefan Roese u8 i2mod; 1125a47a12beSStefan Roese u8 res1[3]; 1126a47a12beSStefan Roese u8 i2add; 1127a47a12beSStefan Roese u8 res2[3]; 1128a47a12beSStefan Roese u8 i2brg; 1129a47a12beSStefan Roese u8 res3[3]; 1130a47a12beSStefan Roese u8 i2com; 1131a47a12beSStefan Roese u8 res4[3]; 1132a47a12beSStefan Roese u8 i2cer; 1133a47a12beSStefan Roese u8 res5[3]; 1134a47a12beSStefan Roese u8 i2cmr; 1135a47a12beSStefan Roese u8 res6[331]; 1136a47a12beSStefan Roese } ccsr_cpm_i2c_t; 1137a47a12beSStefan Roese 1138a47a12beSStefan Roese /* CPM core */ 1139a47a12beSStefan Roese typedef struct ccsr_cpm_cp { 1140a47a12beSStefan Roese u32 cpcr; 1141a47a12beSStefan Roese u32 rccr; 1142a47a12beSStefan Roese u8 res1[14]; 1143a47a12beSStefan Roese u16 rter; 1144a47a12beSStefan Roese u8 res2[2]; 1145a47a12beSStefan Roese u16 rtmr; 1146a47a12beSStefan Roese u16 rtscr; 1147a47a12beSStefan Roese u8 res3[2]; 1148a47a12beSStefan Roese u32 rtsr; 1149a47a12beSStefan Roese u8 res4[12]; 1150a47a12beSStefan Roese } ccsr_cpm_cp_t; 1151a47a12beSStefan Roese 1152a47a12beSStefan Roese /* BRGs:1,2,3,4 */ 1153a47a12beSStefan Roese typedef struct ccsr_cpm_brg1 { 1154a47a12beSStefan Roese u32 brgc1; 1155a47a12beSStefan Roese u32 brgc2; 1156a47a12beSStefan Roese u32 brgc3; 1157a47a12beSStefan Roese u32 brgc4; 1158a47a12beSStefan Roese } ccsr_cpm_brg1_t; 1159a47a12beSStefan Roese 1160a47a12beSStefan Roese /* SCC1-SCC4 */ 1161a47a12beSStefan Roese typedef struct ccsr_cpm_scc { 1162a47a12beSStefan Roese u32 gsmrl; 1163a47a12beSStefan Roese u32 gsmrh; 1164a47a12beSStefan Roese u16 psmr; 1165a47a12beSStefan Roese u8 res1[2]; 1166a47a12beSStefan Roese u16 todr; 1167a47a12beSStefan Roese u16 dsr; 1168a47a12beSStefan Roese u16 scce; 1169a47a12beSStefan Roese u8 res2[2]; 1170a47a12beSStefan Roese u16 sccm; 1171a47a12beSStefan Roese u8 res3; 1172a47a12beSStefan Roese u8 sccs; 1173a47a12beSStefan Roese u8 res4[8]; 1174a47a12beSStefan Roese } ccsr_cpm_scc_t; 1175a47a12beSStefan Roese 1176a47a12beSStefan Roese typedef struct ccsr_cpm_tmp2 { 1177a47a12beSStefan Roese u8 res[32]; 1178a47a12beSStefan Roese } ccsr_cpm_tmp2_t; 1179a47a12beSStefan Roese 1180a47a12beSStefan Roese /* SPI */ 1181a47a12beSStefan Roese typedef struct ccsr_cpm_spi { 1182a47a12beSStefan Roese u16 spmode; 1183a47a12beSStefan Roese u8 res1[4]; 1184a47a12beSStefan Roese u8 spie; 1185a47a12beSStefan Roese u8 res2[3]; 1186a47a12beSStefan Roese u8 spim; 1187a47a12beSStefan Roese u8 res3[2]; 1188a47a12beSStefan Roese u8 spcom; 1189a47a12beSStefan Roese u8 res4[82]; 1190a47a12beSStefan Roese } ccsr_cpm_spi_t; 1191a47a12beSStefan Roese 1192a47a12beSStefan Roese /* CPM MUX */ 1193a47a12beSStefan Roese typedef struct ccsr_cpm_mux { 1194a47a12beSStefan Roese u8 cmxsi1cr; 1195a47a12beSStefan Roese u8 res1; 1196a47a12beSStefan Roese u8 cmxsi2cr; 1197a47a12beSStefan Roese u8 res2; 1198a47a12beSStefan Roese u32 cmxfcr; 1199a47a12beSStefan Roese u32 cmxscr; 1200a47a12beSStefan Roese u8 res3[2]; 1201a47a12beSStefan Roese u16 cmxuar; 1202a47a12beSStefan Roese u8 res4[16]; 1203a47a12beSStefan Roese } ccsr_cpm_mux_t; 1204a47a12beSStefan Roese 1205a47a12beSStefan Roese /* SI,MCC,etc */ 1206a47a12beSStefan Roese typedef struct ccsr_cpm_tmp3 { 1207a47a12beSStefan Roese u8 res[58592]; 1208a47a12beSStefan Roese } ccsr_cpm_tmp3_t; 1209a47a12beSStefan Roese 1210a47a12beSStefan Roese typedef struct ccsr_cpm_iram { 1211a47a12beSStefan Roese u32 iram[8192]; 1212a47a12beSStefan Roese u8 res[98304]; 1213a47a12beSStefan Roese } ccsr_cpm_iram_t; 1214a47a12beSStefan Roese 1215a47a12beSStefan Roese typedef struct ccsr_cpm { 1216a47a12beSStefan Roese /* Some references are into the unique & known dpram spaces, 1217a47a12beSStefan Roese * others are from the generic base. 1218a47a12beSStefan Roese */ 1219a47a12beSStefan Roese #define im_dprambase im_dpram1 1220a47a12beSStefan Roese u8 im_dpram1[16*1024]; 1221a47a12beSStefan Roese u8 res1[16*1024]; 1222a47a12beSStefan Roese u8 im_dpram2[16*1024]; 1223a47a12beSStefan Roese u8 res2[16*1024]; 1224a47a12beSStefan Roese ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ 1225a47a12beSStefan Roese ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ 1226a47a12beSStefan Roese ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ 1227a47a12beSStefan Roese ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ 1228a47a12beSStefan Roese ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ 1229a47a12beSStefan Roese ccsr_cpm_fcc1_t im_cpm_fcc1; 1230a47a12beSStefan Roese ccsr_cpm_fcc2_t im_cpm_fcc2; 1231a47a12beSStefan Roese ccsr_cpm_fcc3_t im_cpm_fcc3; 1232a47a12beSStefan Roese ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; 1233a47a12beSStefan Roese ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; 1234a47a12beSStefan Roese ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; 1235a47a12beSStefan Roese ccsr_cpm_tmp1_t im_cpm_tmp1; 1236a47a12beSStefan Roese ccsr_cpm_brg2_t im_cpm_brg2; 1237a47a12beSStefan Roese ccsr_cpm_i2c_t im_cpm_i2c; 1238a47a12beSStefan Roese ccsr_cpm_cp_t im_cpm_cp; 1239a47a12beSStefan Roese ccsr_cpm_brg1_t im_cpm_brg1; 1240a47a12beSStefan Roese ccsr_cpm_scc_t im_cpm_scc[4]; 1241a47a12beSStefan Roese ccsr_cpm_tmp2_t im_cpm_tmp2; 1242a47a12beSStefan Roese ccsr_cpm_spi_t im_cpm_spi; 1243a47a12beSStefan Roese ccsr_cpm_mux_t im_cpm_mux; 1244a47a12beSStefan Roese ccsr_cpm_tmp3_t im_cpm_tmp3; 1245a47a12beSStefan Roese ccsr_cpm_iram_t im_cpm_iram; 1246a47a12beSStefan Roese } ccsr_cpm_t; 1247a47a12beSStefan Roese #endif 1248a47a12beSStefan Roese 12497d67ed58SLiu Gang #ifdef CONFIG_SYS_SRIO 12507d67ed58SLiu Gang /* Architectural regsiters */ 12517d67ed58SLiu Gang struct rio_arch { 12527d67ed58SLiu Gang u32 didcar; /* Device Identity CAR */ 12537d67ed58SLiu Gang u32 dicar; /* Device Information CAR */ 12547d67ed58SLiu Gang u32 aidcar; /* Assembly Identity CAR */ 12557d67ed58SLiu Gang u32 aicar; /* Assembly Information CAR */ 12567d67ed58SLiu Gang u32 pefcar; /* Processing Element Features CAR */ 12577d67ed58SLiu Gang u8 res0[4]; 12587d67ed58SLiu Gang u32 socar; /* Source Operations CAR */ 12597d67ed58SLiu Gang u32 docar; /* Destination Operations CAR */ 1260a47a12beSStefan Roese u8 res1[32]; 12617d67ed58SLiu Gang u32 mcsr; /* Mailbox CSR */ 12627d67ed58SLiu Gang u32 pwdcsr; /* Port-Write and Doorbell CSR */ 1263a47a12beSStefan Roese u8 res2[4]; 1264a47a12beSStefan Roese u32 pellccsr; /* Processing Element Logic Layer CCSR */ 1265a47a12beSStefan Roese u8 res3[12]; 12667d67ed58SLiu Gang u32 lcsbacsr; /* Local Configuration Space BACSR */ 12677d67ed58SLiu Gang u32 bdidcsr; /* Base Device ID CSR */ 1268a47a12beSStefan Roese u8 res4[4]; 12697d67ed58SLiu Gang u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ 12707d67ed58SLiu Gang u32 ctcsr; /* Component Tag CSR */ 12717d67ed58SLiu Gang }; 12727d67ed58SLiu Gang 12737d67ed58SLiu Gang /* Extended Features Space: 1x/4x LP-Serial Port registers */ 12747d67ed58SLiu Gang struct rio_lp_serial_port { 12757d67ed58SLiu Gang u32 plmreqcsr; /* Port Link Maintenance Request CSR */ 12767d67ed58SLiu Gang u32 plmrespcsr; /* Port Link Maintenance Response CS */ 12777d67ed58SLiu Gang u32 plascsr; /* Port Local Ackid Status CSR */ 12787d67ed58SLiu Gang u8 res0[12]; 12797d67ed58SLiu Gang u32 pescsr; /* Port Error and Status CSR */ 12807d67ed58SLiu Gang u32 pccsr; /* Port Control CSR */ 12817d67ed58SLiu Gang }; 12827d67ed58SLiu Gang 12837d67ed58SLiu Gang /* Extended Features Space: 1x/4x LP-Serial registers */ 12847d67ed58SLiu Gang struct rio_lp_serial { 12857d67ed58SLiu Gang u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ 12867d67ed58SLiu Gang u8 res0[28]; 12877d67ed58SLiu Gang u32 pltoccsr; /* Port Link Time-out CCSR */ 12887d67ed58SLiu Gang u32 prtoccsr; /* Port Response Time-out CCSR */ 12897d67ed58SLiu Gang u8 res1[20]; 12907d67ed58SLiu Gang u32 pgccsr; /* Port General CSR */ 12917d67ed58SLiu Gang struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 12927d67ed58SLiu Gang }; 12937d67ed58SLiu Gang 12947d67ed58SLiu Gang /* Logical error reporting registers */ 12957d67ed58SLiu Gang struct rio_logical_err { 12967d67ed58SLiu Gang u32 erbh; /* Error Reporting Block Header Register */ 12977d67ed58SLiu Gang u8 res0[4]; 12987d67ed58SLiu Gang u32 ltledcsr; /* Logical/Transport layer error DCSR */ 12997d67ed58SLiu Gang u32 ltleecsr; /* Logical/Transport layer error ECSR */ 13007d67ed58SLiu Gang u8 res1[4]; 13017d67ed58SLiu Gang u32 ltlaccsr; /* Logical/Transport layer ACCSR */ 13027d67ed58SLiu Gang u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ 13037d67ed58SLiu Gang u32 ltlcccsr; /* Logical/Transport layer control CCSR */ 13047d67ed58SLiu Gang }; 13057d67ed58SLiu Gang 13067d67ed58SLiu Gang /* Physical error reporting port registers */ 13077d67ed58SLiu Gang struct rio_phys_err_port { 13087d67ed58SLiu Gang u32 edcsr; /* Port error detect CSR */ 13097d67ed58SLiu Gang u32 erecsr; /* Port error rate enable CSR */ 13107d67ed58SLiu Gang u32 ecacsr; /* Port error capture attributes CSR */ 13117d67ed58SLiu Gang u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ 13127d67ed58SLiu Gang u32 peccsr[3]; /* Port error capture CSR */ 13137d67ed58SLiu Gang u8 res0[12]; 13147d67ed58SLiu Gang u32 ercsr; /* Port error rate CSR */ 13157d67ed58SLiu Gang u32 ertcsr; /* Port error rate threshold CSR */ 13167d67ed58SLiu Gang u8 res1[16]; 13177d67ed58SLiu Gang }; 13187d67ed58SLiu Gang 13197d67ed58SLiu Gang /* Physical error reporting registers */ 13207d67ed58SLiu Gang struct rio_phys_err { 13217d67ed58SLiu Gang struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 13227d67ed58SLiu Gang }; 13237d67ed58SLiu Gang 13247d67ed58SLiu Gang /* Implementation Space: General Port-Common */ 13257d67ed58SLiu Gang struct rio_impl_common { 13267d67ed58SLiu Gang u8 res0[4]; 13277d67ed58SLiu Gang u32 llcr; /* Logical Layer Configuration Register */ 13287d67ed58SLiu Gang u8 res1[8]; 13297d67ed58SLiu Gang u32 epwisr; /* Error / Port-Write Interrupt SR */ 13307d67ed58SLiu Gang u8 res2[12]; 13317d67ed58SLiu Gang u32 lretcr; /* Logical Retry Error Threshold CR */ 13327d67ed58SLiu Gang u8 res3[92]; 13337d67ed58SLiu Gang u32 pretcr; /* Physical Retry Erorr Threshold CR */ 13347d67ed58SLiu Gang u8 res4[124]; 13357d67ed58SLiu Gang }; 13367d67ed58SLiu Gang 13377d67ed58SLiu Gang /* Implementation Space: Port Specific */ 13387d67ed58SLiu Gang struct rio_impl_port_spec { 13397d67ed58SLiu Gang u32 adidcsr; /* Port Alt. Device ID CSR */ 13407d67ed58SLiu Gang u8 res0[28]; 13417d67ed58SLiu Gang u32 ptaacr; /* Port Pass-Through/Accept-All CR */ 13427d67ed58SLiu Gang u32 lopttlcr; 13437d67ed58SLiu Gang u8 res1[8]; 13447d67ed58SLiu Gang u32 iecsr; /* Port Implementation Error CSR */ 13457d67ed58SLiu Gang u8 res2[12]; 13467d67ed58SLiu Gang u32 pcr; /* Port Phsyical Configuration Register */ 13477d67ed58SLiu Gang u8 res3[20]; 13487d67ed58SLiu Gang u32 slcsr; /* Port Serial Link CSR */ 13497d67ed58SLiu Gang u8 res4[4]; 13507d67ed58SLiu Gang u32 sleicr; /* Port Serial Link Error Injection */ 13517d67ed58SLiu Gang u32 a0txcr; /* Port Arbitration 0 Tx CR */ 13527d67ed58SLiu Gang u32 a1txcr; /* Port Arbitration 1 Tx CR */ 13537d67ed58SLiu Gang u32 a2txcr; /* Port Arbitration 2 Tx CR */ 13547d67ed58SLiu Gang u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ 13557d67ed58SLiu Gang u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ 13567d67ed58SLiu Gang }; 13577d67ed58SLiu Gang 13587d67ed58SLiu Gang /* Implementation Space: register */ 13597d67ed58SLiu Gang struct rio_implement { 13607d67ed58SLiu Gang struct rio_impl_common com; 13617d67ed58SLiu Gang struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 13627d67ed58SLiu Gang }; 13637d67ed58SLiu Gang 13647d67ed58SLiu Gang /* Revision Control Register */ 13657d67ed58SLiu Gang struct rio_rev_ctrl { 13667d67ed58SLiu Gang u32 ipbrr[2]; /* IP Block Revision Register */ 13677d67ed58SLiu Gang }; 13687d67ed58SLiu Gang 13697d67ed58SLiu Gang struct rio_atmu_row { 13707d67ed58SLiu Gang u32 rowtar; /* RapidIO Outbound Window TAR */ 13717d67ed58SLiu Gang u32 rowtear; /* RapidIO Outbound Window TEAR */ 13727d67ed58SLiu Gang u32 rowbar; 13737d67ed58SLiu Gang u8 res0[4]; 13747d67ed58SLiu Gang u32 rowar; /* RapidIO Outbound Attributes Register */ 13757d67ed58SLiu Gang u32 rowsr[3]; /* Port RapidIO outbound window segment register */ 13767d67ed58SLiu Gang }; 13777d67ed58SLiu Gang 13787d67ed58SLiu Gang struct rio_atmu_riw { 13797d67ed58SLiu Gang u32 riwtar; /* RapidIO Inbound Window Translation AR */ 13807d67ed58SLiu Gang u8 res0[4]; 13817d67ed58SLiu Gang u32 riwbar; /* RapidIO Inbound Window Base AR */ 13827d67ed58SLiu Gang u8 res1[4]; 13837d67ed58SLiu Gang u32 riwar; /* RapidIO Inbound Attributes Register */ 13847d67ed58SLiu Gang u8 res2[12]; 13857d67ed58SLiu Gang }; 13867d67ed58SLiu Gang 13877d67ed58SLiu Gang /* ATMU window registers */ 13887d67ed58SLiu Gang struct rio_atmu_win { 13897d67ed58SLiu Gang struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; 13907d67ed58SLiu Gang u8 res0[64]; 13917d67ed58SLiu Gang struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; 13927d67ed58SLiu Gang }; 13937d67ed58SLiu Gang 13947d67ed58SLiu Gang struct rio_atmu { 13957d67ed58SLiu Gang struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 13967d67ed58SLiu Gang }; 13977d67ed58SLiu Gang 13987d67ed58SLiu Gang #ifdef CONFIG_SYS_FSL_RMU 13997d67ed58SLiu Gang struct rio_msg { 14007d67ed58SLiu Gang u32 omr; /* Outbound Mode Register */ 14017d67ed58SLiu Gang u32 osr; /* Outbound Status Register */ 14027d67ed58SLiu Gang u32 eodqdpar; /* Extended Outbound DQ DPAR */ 14037d67ed58SLiu Gang u32 odqdpar; /* Outbound Descriptor Queue DPAR */ 14047d67ed58SLiu Gang u32 eosar; /* Extended Outbound Unit Source AR */ 14057d67ed58SLiu Gang u32 osar; /* Outbound Unit Source AR */ 14067d67ed58SLiu Gang u32 odpr; /* Outbound Destination Port Register */ 14077d67ed58SLiu Gang u32 odatr; /* Outbound Destination Attributes Register */ 14087d67ed58SLiu Gang u32 odcr; /* Outbound Doubleword Count Register */ 14097d67ed58SLiu Gang u32 eodqepar; /* Extended Outbound DQ EPAR */ 14107d67ed58SLiu Gang u32 odqepar; /* Outbound Descriptor Queue EPAR */ 14117d67ed58SLiu Gang u32 oretr; /* Outbound Retry Error Threshold Register */ 14127d67ed58SLiu Gang u32 omgr; /* Outbound Multicast Group Register */ 14137d67ed58SLiu Gang u32 omlr; /* Outbound Multicast List Register */ 14147d67ed58SLiu Gang u8 res0[40]; 14157d67ed58SLiu Gang u32 imr; /* Outbound Mode Register */ 14167d67ed58SLiu Gang u32 isr; /* Inbound Status Register */ 14177d67ed58SLiu Gang u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ 14187d67ed58SLiu Gang u32 idqdpar; /* Inbound Descriptor Queue DPAR */ 14197d67ed58SLiu Gang u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ 14207d67ed58SLiu Gang u32 ifqepar; /* Inbound Frame Queue EPAR */ 14217d67ed58SLiu Gang u32 imirir; /* Inbound Maximum Interrutp RIR */ 14227d67ed58SLiu Gang u8 res1[4]; 14237d67ed58SLiu Gang u32 eihqepar; /* Extended inbound message header queue EPAR */ 14247d67ed58SLiu Gang u32 ihqepar; /* Inbound message header queue EPAR */ 14257d67ed58SLiu Gang u8 res2[120]; 14267d67ed58SLiu Gang }; 14277d67ed58SLiu Gang 14287d67ed58SLiu Gang struct rio_dbell { 14297d67ed58SLiu Gang u32 odmr; /* Outbound Doorbell Mode Register */ 14307d67ed58SLiu Gang u32 odsr; /* Outbound Doorbell Status Register */ 14317d67ed58SLiu Gang u8 res0[16]; 14327d67ed58SLiu Gang u32 oddpr; /* Outbound Doorbell Destination Port */ 14337d67ed58SLiu Gang u32 oddatr; /* Outbound Doorbell Destination AR */ 14347d67ed58SLiu Gang u8 res1[12]; 14357d67ed58SLiu Gang u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ 14367d67ed58SLiu Gang u8 res2[48]; 14377d67ed58SLiu Gang u32 idmr; /* Inbound Doorbell Mode Register */ 14387d67ed58SLiu Gang u32 idsr; /* Inbound Doorbell Status Register */ 14397d67ed58SLiu Gang u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ 14407d67ed58SLiu Gang u32 iqdpar; /* Inbound Doorbell Queue DPAR */ 14417d67ed58SLiu Gang u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ 14427d67ed58SLiu Gang u32 idqepar; /* Inbound Doorbell Queue EPAR */ 14437d67ed58SLiu Gang u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ 14447d67ed58SLiu Gang }; 14457d67ed58SLiu Gang 14467d67ed58SLiu Gang struct rio_pw { 14477d67ed58SLiu Gang u32 pwmr; /* Port-Write Mode Register */ 14487d67ed58SLiu Gang u32 pwsr; /* Port-Write Status Register */ 14497d67ed58SLiu Gang u32 epwqbar; /* Extended Port-Write Queue BAR */ 14507d67ed58SLiu Gang u32 pwqbar; /* Port-Write Queue Base Address Register */ 14517d67ed58SLiu Gang }; 14527d67ed58SLiu Gang #endif 14537d67ed58SLiu Gang 1454b3831020SLiu Gang #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1455b3831020SLiu Gang struct rio_liodn { 1456b3831020SLiu Gang u32 plbr; 1457b3831020SLiu Gang u8 res0[28]; 1458b3831020SLiu Gang u32 plaor; 1459b3831020SLiu Gang u8 res1[12]; 1460b3831020SLiu Gang u32 pludr; 1461b3831020SLiu Gang u32 plldr; 1462b3831020SLiu Gang u8 res2[456]; 1463b3831020SLiu Gang }; 1464b3831020SLiu Gang #endif 1465b3831020SLiu Gang 14667d67ed58SLiu Gang /* RapidIO Registers */ 14677d67ed58SLiu Gang struct ccsr_rio { 14687d67ed58SLiu Gang struct rio_arch arch; 14697d67ed58SLiu Gang u8 res0[144]; 14707d67ed58SLiu Gang struct rio_lp_serial lp_serial; 14717d67ed58SLiu Gang u8 res1[1152]; 14727d67ed58SLiu Gang struct rio_logical_err logical_err; 14737d67ed58SLiu Gang u8 res2[32]; 14747d67ed58SLiu Gang struct rio_phys_err phys_err; 14757d67ed58SLiu Gang u8 res3[63808]; 14767d67ed58SLiu Gang struct rio_implement impl; 14777d67ed58SLiu Gang u8 res4[2552]; 14787d67ed58SLiu Gang struct rio_rev_ctrl rev; 14797d67ed58SLiu Gang struct rio_atmu atmu; 14807d67ed58SLiu Gang #ifdef CONFIG_SYS_FSL_RMU 14817d67ed58SLiu Gang u8 res5[8192]; 14827d67ed58SLiu Gang struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; 14837d67ed58SLiu Gang u8 res6[512]; 14847d67ed58SLiu Gang struct rio_dbell dbell; 14857d67ed58SLiu Gang u8 res7[100]; 14867d67ed58SLiu Gang struct rio_pw pw; 14877d67ed58SLiu Gang #endif 1488b3831020SLiu Gang #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1489b3831020SLiu Gang u8 res5[8192]; 1490b3831020SLiu Gang struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1491b3831020SLiu Gang #endif 14927d67ed58SLiu Gang }; 14937d67ed58SLiu Gang #endif 1494a47a12beSStefan Roese 1495a47a12beSStefan Roese /* Quick Engine Block Pin Muxing Registers */ 1496a47a12beSStefan Roese typedef struct par_io { 1497a47a12beSStefan Roese u32 cpodr; 1498a47a12beSStefan Roese u32 cpdat; 1499a47a12beSStefan Roese u32 cpdir1; 1500a47a12beSStefan Roese u32 cpdir2; 1501a47a12beSStefan Roese u32 cppar1; 1502a47a12beSStefan Roese u32 cppar2; 1503a47a12beSStefan Roese u8 res[8]; 1504a47a12beSStefan Roese } par_io_t; 1505a47a12beSStefan Roese 1506a47a12beSStefan Roese #ifdef CONFIG_SYS_FSL_CPC 1507a47a12beSStefan Roese /* 1508a47a12beSStefan Roese * Define a single offset that is the start of all the CPC register 1509a47a12beSStefan Roese * blocks - if there is more than one CPC, we expect these to be 1510a47a12beSStefan Roese * contiguous 4k regions 1511a47a12beSStefan Roese */ 1512a47a12beSStefan Roese 1513a47a12beSStefan Roese typedef struct cpc_corenet { 1514a47a12beSStefan Roese u32 cpccsr0; /* Config/status reg */ 1515a47a12beSStefan Roese u32 res1; 1516a47a12beSStefan Roese u32 cpccfg0; /* Configuration register */ 1517a47a12beSStefan Roese u32 res2; 1518a47a12beSStefan Roese u32 cpcewcr0; /* External Write reg 0 */ 1519a47a12beSStefan Roese u32 cpcewabr0; /* External write base reg 0 */ 1520a47a12beSStefan Roese u32 res3[2]; 1521a47a12beSStefan Roese u32 cpcewcr1; /* External Write reg 1 */ 1522a47a12beSStefan Roese u32 cpcewabr1; /* External write base reg 1 */ 1523a47a12beSStefan Roese u32 res4[54]; 1524a47a12beSStefan Roese u32 cpcsrcr1; /* SRAM control reg 1 */ 1525a47a12beSStefan Roese u32 cpcsrcr0; /* SRAM control reg 0 */ 1526a47a12beSStefan Roese u32 res5[62]; 1527a47a12beSStefan Roese struct { 1528a47a12beSStefan Roese u32 id; /* partition ID */ 1529a47a12beSStefan Roese u32 res; 1530a47a12beSStefan Roese u32 alloc; /* partition allocation */ 1531a47a12beSStefan Roese u32 way; /* partition way */ 1532a47a12beSStefan Roese } partition_regs[16]; 1533a47a12beSStefan Roese u32 res6[704]; 1534a47a12beSStefan Roese u32 cpcerrinjhi; /* Error injection high */ 1535a47a12beSStefan Roese u32 cpcerrinjlo; /* Error injection lo */ 1536a47a12beSStefan Roese u32 cpcerrinjctl; /* Error injection control */ 1537a47a12beSStefan Roese u32 res7[5]; 1538a47a12beSStefan Roese u32 cpccaptdatahi; /* capture data high */ 1539a47a12beSStefan Roese u32 cpccaptdatalo; /* capture data low */ 1540a47a12beSStefan Roese u32 cpcaptecc; /* capture ECC */ 1541a47a12beSStefan Roese u32 res8[5]; 1542a47a12beSStefan Roese u32 cpcerrdet; /* error detect */ 1543a47a12beSStefan Roese u32 cpcerrdis; /* error disable */ 1544a47a12beSStefan Roese u32 cpcerrinten; /* errir interrupt enable */ 1545a47a12beSStefan Roese u32 cpcerrattr; /* error attribute */ 1546a47a12beSStefan Roese u32 cpcerreaddr; /* error extended address */ 1547a47a12beSStefan Roese u32 cpcerraddr; /* error address */ 1548a47a12beSStefan Roese u32 cpcerrctl; /* error control */ 15493c6a22b9SKumar Gala u32 res9[41]; /* pad out to 4k */ 15503c6a22b9SKumar Gala u32 cpchdbcr0; /* hardware debug control register 0 */ 15513c6a22b9SKumar Gala u32 res10[63]; /* pad out to 4k */ 1552a47a12beSStefan Roese } cpc_corenet_t; 1553a47a12beSStefan Roese 1554a47a12beSStefan Roese #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ 1555a47a12beSStefan Roese #define CPC_CSR0_PE 0x40000000 /* Enable ECC */ 1556a47a12beSStefan Roese #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ 1557a47a12beSStefan Roese #define CPC_CSR0_WT 0x00080000 /* Write-through mode */ 1558a47a12beSStefan Roese #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ 1559a47a12beSStefan Roese #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ 1560a47a12beSStefan Roese #define CPC_CFG0_SZ_MASK 0x00003fff 1561a47a12beSStefan Roese #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) 1562a47a12beSStefan Roese #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) 1563a47a12beSStefan Roese #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) 1564a47a12beSStefan Roese #define CPC_SRCR1_SRBARU_MASK 0x0000ffff 1565a47a12beSStefan Roese #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ 1566a47a12beSStefan Roese & CPC_SRCR1_SRBARU_MASK) 1567a47a12beSStefan Roese #define CPC_SRCR0_SRBARL_MASK 0xffff8000 1568a47a12beSStefan Roese #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) 1569a47a12beSStefan Roese #define CPC_SRCR0_INTLVEN 0x00000100 1570a47a12beSStefan Roese #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 1571a47a12beSStefan Roese #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 1572a47a12beSStefan Roese #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 1573a47a12beSStefan Roese #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 1574a47a12beSStefan Roese #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 1575a47a12beSStefan Roese #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a 1576a47a12beSStefan Roese #define CPC_SRCR0_SRAMEN 0x00000001 1577a47a12beSStefan Roese #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ 15783c6a22b9SKumar Gala #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 15791d2c2a62SKumar Gala #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 1580868da593SKumar Gala #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 1581f3dbf1f0SYork Sun #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000 1582a47a12beSStefan Roese #endif /* CONFIG_SYS_FSL_CPC */ 1583a47a12beSStefan Roese 1584a47a12beSStefan Roese /* Global Utilities Block */ 1585a47a12beSStefan Roese #ifdef CONFIG_FSL_CORENET 1586a47a12beSStefan Roese typedef struct ccsr_gur { 158745c18853SYork Sun u32 porsr1; /* POR status 1 */ 158845c18853SYork Sun u32 porsr2; /* POR status 2 */ 15890c12a159Svijay rai #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 15900c12a159Svijay rai #define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15 15910c12a159Svijay rai #define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1 15920c12a159Svijay rai #define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1 15930c12a159Svijay rai #define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0 15940c12a159Svijay rai #endif 159545c18853SYork Sun u8 res_008[0x20-0x8]; 1596a47a12beSStefan Roese u32 gpporcr1; /* General-purpose POR configuration */ 159745c18853SYork Sun u32 gpporcr2; /* General-purpose POR configuration 2 */ 159845c18853SYork Sun u32 dcfg_fusesr; /* Fuse status register */ 159945c18853SYork Sun #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25 160045c18853SYork Sun #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F 160145c18853SYork Sun #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20 160245c18853SYork Sun #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F 160345c18853SYork Sun u8 res_02c[0x70-0x2c]; 1604a47a12beSStefan Roese u32 devdisr; /* Device disable control */ 16059e758758SYork Sun u32 devdisr2; /* Device disable control 2 */ 16069e758758SYork Sun u32 devdisr3; /* Device disable control 3 */ 16079e758758SYork Sun u32 devdisr4; /* Device disable control 4 */ 16089e758758SYork Sun #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 16099e758758SYork Sun u32 devdisr5; /* Device disable control 5 */ 16109e758758SYork Sun #define FSL_CORENET_DEVDISR_PBL 0x80000000 16119e758758SYork Sun #define FSL_CORENET_DEVDISR_PMAN 0x40000000 16129e758758SYork Sun #define FSL_CORENET_DEVDISR_ESDHC 0x20000000 16139e758758SYork Sun #define FSL_CORENET_DEVDISR_DMA1 0x00800000 16149e758758SYork Sun #define FSL_CORENET_DEVDISR_DMA2 0x00400000 16159e758758SYork Sun #define FSL_CORENET_DEVDISR_USB1 0x00080000 16169e758758SYork Sun #define FSL_CORENET_DEVDISR_USB2 0x00040000 16179e758758SYork Sun #define FSL_CORENET_DEVDISR_SATA1 0x00008000 16189e758758SYork Sun #define FSL_CORENET_DEVDISR_SATA2 0x00004000 16199e758758SYork Sun #define FSL_CORENET_DEVDISR_PME 0x00000800 16209e758758SYork Sun #define FSL_CORENET_DEVDISR_SEC 0x00000200 16219e758758SYork Sun #define FSL_CORENET_DEVDISR_RMU 0x00000080 16229e758758SYork Sun #define FSL_CORENET_DEVDISR_DCE 0x00000040 16239e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000 16249e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000 16259e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000 16269e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000 16279e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000 16289e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 16299e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 16309e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 1631cc19c25eSShengzhou Liu #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 1632cc19c25eSShengzhou Liu #define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000 1633cc19c25eSShengzhou Liu #define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000 1634cc19c25eSShengzhou Liu #else 16359e758758SYork Sun #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 16369e758758SYork Sun #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 163782a55c1eSShengzhou Liu #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 163882a55c1eSShengzhou Liu #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 1639cc19c25eSShengzhou Liu #endif 16409e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 16419e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 16429e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 16439e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000 16449e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000 16459e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000 16469e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800 16479e758758SYork Sun #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400 16489e758758SYork Sun #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800 16499e758758SYork Sun #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 16509e758758SYork Sun #define FSL_CORENET_DEVDISR2_FM1 0x00000080 16519e758758SYork Sun #define FSL_CORENET_DEVDISR2_FM2 0x00000040 1652d2404141SYork Sun #define FSL_CORENET_DEVDISR2_CPRI 0x00000008 16539e758758SYork Sun #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 16549e758758SYork Sun #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 16559e758758SYork Sun #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 16569e758758SYork Sun #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000 16579e758758SYork Sun #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000 16589e758758SYork Sun #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000 16599e758758SYork Sun #define FSL_CORENET_DEVDISR3_QMAN 0x00080000 16609e758758SYork Sun #define FSL_CORENET_DEVDISR3_BMAN 0x00040000 16619e758758SYork Sun #define FSL_CORENET_DEVDISR3_LA1 0x00008000 1662d2404141SYork Sun #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800 1663d2404141SYork Sun #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400 1664d2404141SYork Sun #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200 16659e758758SYork Sun #define FSL_CORENET_DEVDISR4_I2C1 0x80000000 16669e758758SYork Sun #define FSL_CORENET_DEVDISR4_I2C2 0x40000000 16679e758758SYork Sun #define FSL_CORENET_DEVDISR4_DUART1 0x20000000 16689e758758SYork Sun #define FSL_CORENET_DEVDISR4_DUART2 0x10000000 16699e758758SYork Sun #define FSL_CORENET_DEVDISR4_ESPI 0x08000000 16709e758758SYork Sun #define FSL_CORENET_DEVDISR5_DDR1 0x80000000 16719e758758SYork Sun #define FSL_CORENET_DEVDISR5_DDR2 0x40000000 16729e758758SYork Sun #define FSL_CORENET_DEVDISR5_DDR3 0x20000000 16739e758758SYork Sun #define FSL_CORENET_DEVDISR5_CPC1 0x08000000 16749e758758SYork Sun #define FSL_CORENET_DEVDISR5_CPC2 0x04000000 16759e758758SYork Sun #define FSL_CORENET_DEVDISR5_CPC3 0x02000000 16769e758758SYork Sun #define FSL_CORENET_DEVDISR5_IFC 0x00800000 16779e758758SYork Sun #define FSL_CORENET_DEVDISR5_GPIO 0x00400000 16789e758758SYork Sun #define FSL_CORENET_DEVDISR5_DBG 0x00200000 16799e758758SYork Sun #define FSL_CORENET_DEVDISR5_NAL 0x00100000 1680d2404141SYork Sun #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000 16819e758758SYork Sun #define FSL_CORENET_NUM_DEVDISR 5 16829e758758SYork Sun #else 1683a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 1684a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 1685a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 16869ab87d04SKumar Gala #define FSL_CORENET_DEVDISR_PCIE4 0x10000000 1687a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_RMU 0x08000000 1688a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 1689a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 1690a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_DMA1 0x00400000 1691a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_DMA2 0x00200000 1692a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_DDR1 0x00100000 1693a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_DDR2 0x00080000 1694a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_DBG 0x00010000 1695a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_NAL 0x00008000 16969ab87d04SKumar Gala #define FSL_CORENET_DEVDISR_SATA1 0x00004000 16979ab87d04SKumar Gala #define FSL_CORENET_DEVDISR_SATA2 0x00002000 1698a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_ELBC 0x00001000 1699a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_USB1 0x00000800 1700a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_USB2 0x00000400 1701a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_ESDHC 0x00000100 1702a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_GPIO 0x00000080 1703a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_ESPI 0x00000040 1704a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_I2C1 0x00000020 1705a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_I2C2 0x00000010 1706a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_DUART1 0x00000002 1707a47a12beSStefan Roese #define FSL_CORENET_DEVDISR_DUART2 0x00000001 17081231c498SKumar Gala #define FSL_CORENET_DEVDISR2_PME 0x80000000 17091231c498SKumar Gala #define FSL_CORENET_DEVDISR2_SEC 0x40000000 17101231c498SKumar Gala #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 17111231c498SKumar Gala #define FSL_CORENET_DEVDISR2_FM1 0x02000000 17121231c498SKumar Gala #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000 17131231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000 17141231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 17151231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 17161231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 17179ab87d04SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000 17181231c498SKumar Gala #define FSL_CORENET_DEVDISR2_FM2 0x00020000 17191231c498SKumar Gala #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 17201231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 17211231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 17221231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 17231231c498SKumar Gala #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 172499abf7deSTimur Tabi #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 17259ab87d04SKumar Gala #define FSL_CORENET_NUM_DEVDISR 2 1726a47a12beSStefan Roese u32 powmgtcsr; /* Power management status & control */ 17279e758758SYork Sun #endif 1728a47a12beSStefan Roese u8 res8[12]; 1729a47a12beSStefan Roese u32 coredisru; /* uppper portion for support of 64 cores */ 1730a47a12beSStefan Roese u32 coredisrl; /* lower portion for support of 64 cores */ 1731a47a12beSStefan Roese u8 res9[8]; 1732a47a12beSStefan Roese u32 pvr; /* Processor version */ 1733a47a12beSStefan Roese u32 svr; /* System version */ 1734a47a12beSStefan Roese u8 res10[8]; 1735a47a12beSStefan Roese u32 rstcr; /* Reset control */ 1736a47a12beSStefan Roese u32 rstrqpblsr; /* Reset request preboot loader status */ 1737a47a12beSStefan Roese u8 res11[8]; 1738a47a12beSStefan Roese u32 rstrqmr1; /* Reset request mask */ 1739fb07c0a1SShaveta Leekha #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1740fb07c0a1SShaveta Leekha #define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800 1741fb07c0a1SShaveta Leekha #endif 1742a47a12beSStefan Roese u8 res12[4]; 1743a47a12beSStefan Roese u32 rstrqsr1; /* Reset request status */ 1744a47a12beSStefan Roese u8 res13[4]; 1745a47a12beSStefan Roese u8 res14[4]; 1746a47a12beSStefan Roese u32 rstrqwdtmrl; /* Reset request WDT mask */ 1747a47a12beSStefan Roese u8 res15[4]; 1748a47a12beSStefan Roese u32 rstrqwdtsrl; /* Reset request WDT status */ 1749a47a12beSStefan Roese u8 res16[4]; 1750a47a12beSStefan Roese u32 brrl; /* Boot release */ 1751a47a12beSStefan Roese u8 res17[24]; 1752a47a12beSStefan Roese u32 rcwsr[16]; /* Reset control word status */ 17530a6b2714SAneesh Bansal #define RCW_SB_EN_REG_INDEX 7 17540a6b2714SAneesh Bansal #define RCW_SB_EN_MASK 0x00200000 1755fd3cebd0SYork Sun 1756fd3cebd0SYork Sun #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1757f77329cfSYork Sun #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 1758c3678b09SYork Sun /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ 1759c3678b09SYork Sun #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 1760f77329cfSYork Sun #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f 1761cdb72c52SYork Sun #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 1762fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 1763fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 1764fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 1765fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 1766fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800 1767fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 1768fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 1769fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 177069fdf900SLiu Gang #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1771b41f192bSYork Sun #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 1772d2404141SYork Sun #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 1773d2404141SYork Sun #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 1774d2404141SYork Sun #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1775d2404141SYork Sun #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 17765870fe44SLiu Gang #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 177708a37fd1SYork Sun #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) 17785f208d11SYork Sun #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 17795f208d11SYork Sun #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 17805f208d11SYork Sun #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 17815f208d11SYork Sun #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 17825b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ 17835b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 17845b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 17855b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 17865b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ 17875b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 1788*db148f2aSBin Meng #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000 17895b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 17905b7672fcSPrabhakar Kushwaha #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 1791c00d0012SBin Meng #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 1792bf4699dbSPriyanka Jain #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 1793bf4699dbSPriyanka Jain #define PXCKEN_MASK 0x80000000 1794bf4699dbSPriyanka Jain #define PXCK_MASK 0x00FF0000 1795bf4699dbSPriyanka Jain #define PXCK_BITS_START 16 179608a37fd1SYork Sun #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 1797f6050790SShengzhou Liu #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 1798f6050790SShengzhou Liu #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 1799f6050790SShengzhou Liu #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1800f6050790SShengzhou Liu #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ 1801f6050790SShengzhou Liu #define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000 1802f6050790SShengzhou Liu #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 1803f6050790SShengzhou Liu #define FSL_CORENET_RCWSR13_EC2 0x0c000000 1804f6050790SShengzhou Liu #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 1805f6050790SShengzhou Liu #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 18065818643bSShengzhou Liu #define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 1807f6050790SShengzhou Liu #define PXCKEN_MASK 0x80000000 1808f6050790SShengzhou Liu #define PXCK_MASK 0x00FF0000 1809f6050790SShengzhou Liu #define PXCK_BITS_START 16 18100f3d80e9SYork Sun #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 1811629d6b32SShengzhou Liu #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 1812629d6b32SShengzhou Liu #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 1813629d6b32SShengzhou Liu #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1814629d6b32SShengzhou Liu #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 1815629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 18169e758758SYork Sun #endif 1817fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 1818fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 1819fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000 1820fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000 1821fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000 1822fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 1823fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 1824fd3cebd0SYork Sun #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 1825b135991aSPriyanka Jain #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 1826b135991aSPriyanka Jain #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 1827b135991aSPriyanka Jain #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 1828fd3cebd0SYork Sun 1829fd3cebd0SYork Sun #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1830fd3cebd0SYork Sun #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 1831fd3cebd0SYork Sun #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f 1832a47a12beSStefan Roese #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 1833ab48ca1aSSrikanth Srinivasan #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 1834ab48ca1aSSrikanth Srinivasan #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 18351231c498SKumar Gala #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 18364905443fSTimur Tabi #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000 183781fa73baSLiu Gang #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 18389ab87d04SKumar Gala #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ 18399ab87d04SKumar Gala #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ 1840fd3cebd0SYork Sun #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1841fd3cebd0SYork Sun 1842a47a12beSStefan Roese #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 1843a47a12beSStefan Roese #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 1844a47a12beSStefan Roese #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 18459ab87d04SKumar Gala #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ 1846e71372cbSYork Sun #ifdef CONFIG_ARCH_P4080 18479ab87d04SKumar Gala #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 18489ab87d04SKumar Gala #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 18499ab87d04SKumar Gala #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ 18509ab87d04SKumar Gala #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 18519ab87d04SKumar Gala #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 18529ab87d04SKumar Gala #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 1853c916d7c9SKumar Gala #endif 18545e5fdd2dSYork Sun #if defined(CONFIG_ARCH_P2041) || \ 1855cefe11cdSYork Sun defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020) 1856c916d7c9SKumar Gala #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 1857c916d7c9SKumar Gala #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 1858c916d7c9SKumar Gala #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 1859c916d7c9SKumar Gala #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1860c916d7c9SKumar Gala #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000 1861c916d7c9SKumar Gala #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 1862c916d7c9SKumar Gala #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 1863c916d7c9SKumar Gala #endif 186495390360SYork Sun #if defined(CONFIG_ARCH_P5040) 18654905443fSTimur Tabi #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 18664905443fSTimur Tabi #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 18674905443fSTimur Tabi #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 18684905443fSTimur Tabi #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 18694905443fSTimur Tabi #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000 18704905443fSTimur Tabi #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 18714905443fSTimur Tabi #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 18724905443fSTimur Tabi #endif 1873cdb72c52SYork Sun #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 18749e758758SYork Sun #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 18759e758758SYork Sun #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 18769e758758SYork Sun #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 18779e758758SYork Sun #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 18789e758758SYork Sun #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 18799e758758SYork Sun #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 18809e758758SYork Sun #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 18819e758758SYork Sun #endif 18820f3d80e9SYork Sun #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 1883629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 1884629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 1885629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 1886629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 1887629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 1888629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 1889629d6b32SShengzhou Liu #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 1890629d6b32SShengzhou Liu #endif 1891a47a12beSStefan Roese u8 res18[192]; 1892a47a12beSStefan Roese u32 scratchrw[4]; /* Scratch Read/Write */ 1893a47a12beSStefan Roese u8 res19[240]; 1894a47a12beSStefan Roese u32 scratchw1r[4]; /* Scratch Read (Write once) */ 1895a47a12beSStefan Roese u8 res20[240]; 1896a47a12beSStefan Roese u32 scrtsr[8]; /* Core reset status */ 1897a47a12beSStefan Roese u8 res21[224]; 1898a47a12beSStefan Roese u32 pex1liodnr; /* PCI Express 1 LIODN */ 1899a47a12beSStefan Roese u32 pex2liodnr; /* PCI Express 2 LIODN */ 1900a47a12beSStefan Roese u32 pex3liodnr; /* PCI Express 3 LIODN */ 1901a47a12beSStefan Roese u32 pex4liodnr; /* PCI Express 4 LIODN */ 1902a47a12beSStefan Roese u32 rio1liodnr; /* RIO 1 LIODN */ 1903a47a12beSStefan Roese u32 rio2liodnr; /* RIO 2 LIODN */ 1904a47a12beSStefan Roese u32 rio3liodnr; /* RIO 3 LIODN */ 1905a47a12beSStefan Roese u32 rio4liodnr; /* RIO 4 LIODN */ 1906a47a12beSStefan Roese u32 usb1liodnr; /* USB 1 LIODN */ 1907a47a12beSStefan Roese u32 usb2liodnr; /* USB 2 LIODN */ 1908a47a12beSStefan Roese u32 usb3liodnr; /* USB 3 LIODN */ 1909a47a12beSStefan Roese u32 usb4liodnr; /* USB 4 LIODN */ 1910a47a12beSStefan Roese u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ 1911a47a12beSStefan Roese u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ 1912a47a12beSStefan Roese u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ 1913a47a12beSStefan Roese u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ 19149ab87d04SKumar Gala u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */ 19159ab87d04SKumar Gala u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */ 19169ab87d04SKumar Gala u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */ 19179ab87d04SKumar Gala u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */ 19189ab87d04SKumar Gala u32 sata1liodnr; /* SATA 1 LIODN */ 19199ab87d04SKumar Gala u32 sata2liodnr; /* SATA 2 LIODN */ 19209ab87d04SKumar Gala u32 sata3liodnr; /* SATA 3 LIODN */ 19219ab87d04SKumar Gala u32 sata4liodnr; /* SATA 4 LIODN */ 1922377ffcfaSSandeep Singh u8 res22[20]; 1923377ffcfaSSandeep Singh u32 tdmliodnr; /* TDM LIODN */ 19242a44efebSZhao Qiang u32 qeliodnr; /* QE LIODN */ 19252a44efebSZhao Qiang u8 res_57c[4]; 1926a47a12beSStefan Roese u32 dma1liodnr; /* DMA 1 LIODN */ 1927a47a12beSStefan Roese u32 dma2liodnr; /* DMA 2 LIODN */ 1928a47a12beSStefan Roese u32 dma3liodnr; /* DMA 3 LIODN */ 1929a47a12beSStefan Roese u32 dma4liodnr; /* DMA 4 LIODN */ 1930a47a12beSStefan Roese u8 res23[48]; 1931a47a12beSStefan Roese u8 res24[64]; 1932a47a12beSStefan Roese u32 pblsr; /* Preboot loader status */ 1933a47a12beSStefan Roese u32 pamubypenr; /* PAMU bypass enable */ 1934a47a12beSStefan Roese u32 dmacr1; /* DMA control */ 1935a47a12beSStefan Roese u8 res25[4]; 1936a47a12beSStefan Roese u32 gensr1; /* General status */ 1937a47a12beSStefan Roese u8 res26[12]; 1938a47a12beSStefan Roese u32 gencr1; /* General control */ 1939a47a12beSStefan Roese u8 res27[12]; 1940a47a12beSStefan Roese u8 res28[4]; 1941a47a12beSStefan Roese u32 cgensrl; /* Core general status */ 1942a47a12beSStefan Roese u8 res29[8]; 1943a47a12beSStefan Roese u8 res30[4]; 1944a47a12beSStefan Roese u32 cgencrl; /* Core general control */ 1945a47a12beSStefan Roese u8 res31[184]; 1946a47a12beSStefan Roese u32 sriopstecr; /* SRIO prescaler timer enable control */ 1947f110fe94SStephen George u32 dcsrcr; /* DCSR Control register */ 19481ca8690dSYork Sun u8 res31a[56]; 19491ca8690dSYork Sun u32 tp_ityp[64]; /* Topology Initiator Type Register */ 19501ca8690dSYork Sun struct { 19511ca8690dSYork Sun u32 upper; 19521ca8690dSYork Sun u32 lower; 19531ca8690dSYork Sun } tp_cluster[16]; /* Core Cluster n Topology Register */ 19541ca8690dSYork Sun u8 res32[1344]; 195517d90f31SDave Liu u32 pmuxcr; /* Pin multiplexing control */ 195617d90f31SDave Liu u8 res33[60]; 195717d90f31SDave Liu u32 iovselsr; /* I/O voltage selection status */ 195817d90f31SDave Liu u8 res34[28]; 195917d90f31SDave Liu u32 ddrclkdr; /* DDR clock disable */ 196017d90f31SDave Liu u8 res35; 196117d90f31SDave Liu u32 elbcclkdr; /* eLBC clock disable */ 196217d90f31SDave Liu u8 res36[20]; 196317d90f31SDave Liu u32 sdhcpcr; /* eSDHC polarity configuration */ 196417d90f31SDave Liu u8 res37[380]; 1965a47a12beSStefan Roese } ccsr_gur_t; 1966a47a12beSStefan Roese 19671ca8690dSYork Sun #define TP_ITYP_AV 0x00000001 /* Initiator available */ 19681ca8690dSYork Sun #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 19691ca8690dSYork Sun #define TP_ITYP_TYPE_OTHER 0x0 19701ca8690dSYork Sun #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 19711ca8690dSYork Sun #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */ 19721ca8690dSYork Sun #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 19731ca8690dSYork Sun #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 19741ca8690dSYork Sun #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 19751ca8690dSYork Sun 19761ca8690dSYork Sun #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 19771ca8690dSYork Sun #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 1978f6981439SYork Sun #define TP_INIT_PER_CLUSTER 4 19791ca8690dSYork Sun 1980f110fe94SStephen George #define FSL_CORENET_DCSR_SZ_MASK 0x00000003 1981f110fe94SStephen George #define FSL_CORENET_DCSR_SZ_4M 0x0 1982f110fe94SStephen George #define FSL_CORENET_DCSR_SZ_1G 0x3 1983f110fe94SStephen George 19849ab87d04SKumar Gala /* 19859ab87d04SKumar Gala * On p4080 we have an LIODN for msg unit (rmu) but not maintenance 19869ab87d04SKumar Gala * everything after has RMan thus msg unit LIODN is used for maintenance 19879ab87d04SKumar Gala */ 19889ab87d04SKumar Gala #define rmuliodnr rio1maintliodnr 19899ab87d04SKumar Gala 1990a47a12beSStefan Roese typedef struct ccsr_clk { 1991f6981439SYork Sun struct { 1992f6981439SYork Sun u32 clkcncsr; /* core cluster n clock control status */ 1993f6981439SYork Sun u8 res_004[0x0c]; 1994f6981439SYork Sun u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ 1995f6981439SYork Sun u8 res_014[0x0c]; 1996ce746fe0SPrabhakar Kushwaha } clkcsr[12]; 1997ce746fe0SPrabhakar Kushwaha u8 res_100[0x680]; /* 0x100 */ 1998ce746fe0SPrabhakar Kushwaha struct { 1999ce746fe0SPrabhakar Kushwaha u32 pllcngsr; 2000a47a12beSStefan Roese u8 res10[0x1c]; 2001ce746fe0SPrabhakar Kushwaha } pllcgsr[12]; 2002ce746fe0SPrabhakar Kushwaha u8 res21[0x280]; 20039a653a98SYork Sun u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 20049a653a98SYork Sun u8 res16[0x1c]; 20059a653a98SYork Sun u32 plldgsr; /* 0xc20 DDR PLL General Status */ 20069a653a98SYork Sun u8 res17[0x3dc]; 2007a47a12beSStefan Roese } ccsr_clk_t; 2008a47a12beSStefan Roese 20091ca8690dSYork Sun #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 20101ca8690dSYork Sun typedef struct ccsr_rcpm { 20111ca8690dSYork Sun u8 res_00[12]; 20121ca8690dSYork Sun u32 tph10sr0; /* Thread PH10 Status Register */ 20131ca8690dSYork Sun u8 res_10[12]; 20141ca8690dSYork Sun u32 tph10setr0; /* Thread PH10 Set Control Register */ 20151ca8690dSYork Sun u8 res_20[12]; 20161ca8690dSYork Sun u32 tph10clrr0; /* Thread PH10 Clear Control Register */ 20171ca8690dSYork Sun u8 res_30[12]; 20181ca8690dSYork Sun u32 tph10psr0; /* Thread PH10 Previous Status Register */ 20191ca8690dSYork Sun u8 res_40[12]; 20201ca8690dSYork Sun u32 twaitsr0; /* Thread Wait Status Register */ 20211ca8690dSYork Sun u8 res_50[96]; 20221ca8690dSYork Sun u32 pcph15sr; /* Physical Core PH15 Status Register */ 20231ca8690dSYork Sun u32 pcph15setr; /* Physical Core PH15 Set Control Register */ 20241ca8690dSYork Sun u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ 20251ca8690dSYork Sun u32 pcph15psr; /* Physical Core PH15 Prev Status Register */ 20261ca8690dSYork Sun u8 res_c0[16]; 20271ca8690dSYork Sun u32 pcph20sr; /* Physical Core PH20 Status Register */ 20281ca8690dSYork Sun u32 pcph20setr; /* Physical Core PH20 Set Control Register */ 20291ca8690dSYork Sun u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ 20301ca8690dSYork Sun u32 pcph20psr; /* Physical Core PH20 Prev Status Register */ 20311ca8690dSYork Sun u32 pcpw20sr; /* Physical Core PW20 Status Register */ 20321ca8690dSYork Sun u8 res_e0[12]; 20331ca8690dSYork Sun u32 pcph30sr; /* Physical Core PH30 Status Register */ 20341ca8690dSYork Sun u32 pcph30setr; /* Physical Core PH30 Set Control Register */ 20351ca8690dSYork Sun u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ 20361ca8690dSYork Sun u32 pcph30psr; /* Physical Core PH30 Prev Status Register */ 20371ca8690dSYork Sun u8 res_100[32]; 20381ca8690dSYork Sun u32 ippwrgatecr; /* IP Power Gating Control Register */ 20391ca8690dSYork Sun u8 res_124[12]; 20401ca8690dSYork Sun u32 powmgtcsr; /* Power Management Control & Status Reg */ 20411ca8690dSYork Sun u8 res_134[12]; 20421ca8690dSYork Sun u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ 20431ca8690dSYork Sun u8 res_150[12]; 20441ca8690dSYork Sun u32 tpmimr0; /* Thread PM Interrupt Mask Reg */ 20451ca8690dSYork Sun u8 res_160[12]; 20461ca8690dSYork Sun u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ 20471ca8690dSYork Sun u8 res_170[12]; 20481ca8690dSYork Sun u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ 20491ca8690dSYork Sun u8 res_180[12]; 20501ca8690dSYork Sun u32 tpmnmimr0; /* Thread PM NMI Mask Reg */ 20511ca8690dSYork Sun u8 res_190[12]; 20521ca8690dSYork Sun u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ 20531ca8690dSYork Sun u32 pctbenr; /* Physical Core Time Base Enable Reg */ 20541ca8690dSYork Sun u32 pctbclkselr; /* Physical Core Time Base Clock Select */ 20551ca8690dSYork Sun u32 tbclkdivr; /* Time Base Clock Divider Register */ 20561ca8690dSYork Sun u8 res_1ac[4]; 20571ca8690dSYork Sun u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ 20581ca8690dSYork Sun u32 clpcl10sr; /* Cluster PCL10 Status Register */ 20591ca8690dSYork Sun u32 clpcl10setr; /* Cluster PCL30 Set Control Register */ 20601ca8690dSYork Sun u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ 20611ca8690dSYork Sun u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ 20621ca8690dSYork Sun u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ 20631ca8690dSYork Sun u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ 20641ca8690dSYork Sun u32 cdpwroksetr; /* Core Domain Power OK Set Register */ 20651ca8690dSYork Sun u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ 20661ca8690dSYork Sun u32 cdpwrensr; /* Core Domain Power Enable Status Register */ 20671ca8690dSYork Sun u32 cddslsr; /* Core Domain Deep Sleep Status Register */ 20681ca8690dSYork Sun u8 res_1e8[8]; 20691ca8690dSYork Sun u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ 20701ca8690dSYork Sun u8 res_300[3568]; 20711ca8690dSYork Sun } ccsr_rcpm_t; 20721ca8690dSYork Sun 20731ca8690dSYork Sun #define ctbenrl pctbenr 20741ca8690dSYork Sun 20751ca8690dSYork Sun #else 2076a47a12beSStefan Roese typedef struct ccsr_rcpm { 2077a47a12beSStefan Roese u8 res1[4]; 2078a47a12beSStefan Roese u32 cdozsrl; /* Core Doze Status */ 2079a47a12beSStefan Roese u8 res2[4]; 2080a47a12beSStefan Roese u32 cdozcrl; /* Core Doze Control */ 2081a47a12beSStefan Roese u8 res3[4]; 2082a47a12beSStefan Roese u32 cnapsrl; /* Core Nap Status */ 2083a47a12beSStefan Roese u8 res4[4]; 2084a47a12beSStefan Roese u32 cnapcrl; /* Core Nap Control */ 2085a47a12beSStefan Roese u8 res5[4]; 2086a47a12beSStefan Roese u32 cdozpsrl; /* Core Doze Previous Status */ 2087a47a12beSStefan Roese u8 res6[4]; 2088a47a12beSStefan Roese u32 cdozpcrl; /* Core Doze Previous Control */ 2089a47a12beSStefan Roese u8 res7[4]; 2090a47a12beSStefan Roese u32 cwaitsrl; /* Core Wait Status */ 2091a47a12beSStefan Roese u8 res8[8]; 2092a47a12beSStefan Roese u32 powmgtcsr; /* Power Mangement Control & Status */ 2093a47a12beSStefan Roese u8 res9[12]; 2094a47a12beSStefan Roese u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ 2095a47a12beSStefan Roese u8 res10[12]; 2096a47a12beSStefan Roese u8 res11[4]; 2097a47a12beSStefan Roese u32 cpmimrl; /* Core PM IRQ Masking */ 2098a47a12beSStefan Roese u8 res12[4]; 2099a47a12beSStefan Roese u32 cpmcimrl; /* Core PM Critical IRQ Masking */ 2100a47a12beSStefan Roese u8 res13[4]; 2101a47a12beSStefan Roese u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ 2102a47a12beSStefan Roese u8 res14[4]; 2103a47a12beSStefan Roese u32 cpmnmimrl; /* Core PM NMI Masking */ 2104a47a12beSStefan Roese u8 res15[4]; 2105a47a12beSStefan Roese u32 ctbenrl; /* Core Time Base Enable */ 2106a47a12beSStefan Roese u8 res16[4]; 2107a47a12beSStefan Roese u32 ctbclkselrl; /* Core Time Base Clock Select */ 2108a47a12beSStefan Roese u8 res17[4]; 2109a47a12beSStefan Roese u32 ctbhltcrl; /* Core Time Base Halt Control */ 2110a47a12beSStefan Roese u8 res18[0xf68]; 2111a47a12beSStefan Roese } ccsr_rcpm_t; 21121ca8690dSYork Sun #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2113a47a12beSStefan Roese 2114a47a12beSStefan Roese #else 2115a47a12beSStefan Roese typedef struct ccsr_gur { 2116a47a12beSStefan Roese u32 porpllsr; /* POR PLL ratio status */ 211724ad75aeSYork Sun #ifdef CONFIG_ARCH_MPC8536 2118a47a12beSStefan Roese #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 2119a47a12beSStefan Roese #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 21204fd64746SYork Sun #elif defined(CONFIG_ARCH_C29X) 21213b75e982SMingkai Hu #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 21223b75e982SMingkai Hu #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ 21233b75e982SMingkai Hu & MPC85xx_PORDEVSR2_DDR_SPD_0) \ 21243b75e982SMingkai Hu >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) 2125a47a12beSStefan Roese #else 2126115d60c0SYork Sun #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) 212719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 212819a8dbdcSPrabhakar Kushwaha #else 2129a47a12beSStefan Roese #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 213019a8dbdcSPrabhakar Kushwaha #endif 2131a47a12beSStefan Roese #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 2132a47a12beSStefan Roese #endif 2133a47a12beSStefan Roese #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 2134a47a12beSStefan Roese #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 2135a47a12beSStefan Roese #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e 2136a47a12beSStefan Roese #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 2137a47a12beSStefan Roese u32 porbmsr; /* POR boot mode status */ 2138a47a12beSStefan Roese #define MPC85xx_PORBMSR_HA 0x00070000 2139a47a12beSStefan Roese #define MPC85xx_PORBMSR_HA_SHIFT 16 21408bd00c94SAndy Fleming #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24 214135fe948eSPrabhakar Kushwaha #define PORBMSR_ROMLOC_SPI 0x6 214235fe948eSPrabhakar Kushwaha #define PORBMSR_ROMLOC_SDHC 0x7 214335fe948eSPrabhakar Kushwaha #define PORBMSR_ROMLOC_NAND_2K 0x9 214435fe948eSPrabhakar Kushwaha #define PORBMSR_ROMLOC_NOR 0xf 2145a47a12beSStefan Roese u32 porimpscr; /* POR I/O impedance status & control */ 2146a47a12beSStefan Roese u32 pordevsr; /* POR I/O device status regsiter */ 214741c7b7b1SYork Sun #if defined(CONFIG_ARCH_P1023) 214867a719daSRoy Zang #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 214967a719daSRoy Zang #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 2150c916d7c9SKumar Gala #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 215167a719daSRoy Zang #else 2152a47a12beSStefan Roese #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 2153a47a12beSStefan Roese #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 215467a719daSRoy Zang #endif 2155a47a12beSStefan Roese #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 2156a47a12beSStefan Roese #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 2157a47a12beSStefan Roese #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 2158a47a12beSStefan Roese #define MPC85xx_PORDEVSR_PCI1 0x00800000 21592f8b8126SYork Sun #if defined(CONFIG_ARCH_P1022) 21600c955dafSDave Liu #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 21610c955dafSDave Liu #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 216241c7b7b1SYork Sun #elif defined(CONFIG_ARCH_P1023) 216367a719daSRoy Zang #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 216467a719daSRoy Zang #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 21650c955dafSDave Liu #else 21667d5f9f84SYork Sun #if defined(CONFIG_ARCH_P1010) 216728747f9bSPrabhakar Kushwaha #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 216828747f9bSPrabhakar Kushwaha #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2169115d60c0SYork Sun #elif defined(CONFIG_ARCH_BSC9132) 217035fe948eSPrabhakar Kushwaha #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 217135fe948eSPrabhakar Kushwaha #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 21724fd64746SYork Sun #elif defined(CONFIG_ARCH_C29X) 21733b75e982SMingkai Hu #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 21743b75e982SMingkai Hu #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 217528747f9bSPrabhakar Kushwaha #else 2176a47a12beSStefan Roese #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 2177a47a12beSStefan Roese #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 21787d5f9f84SYork Sun #endif /* if defined(CONFIG_ARCH_P1010) */ 21790c955dafSDave Liu #endif 2180a47a12beSStefan Roese #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 2181a47a12beSStefan Roese #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 2182a47a12beSStefan Roese #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 2183a47a12beSStefan Roese #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 2184a47a12beSStefan Roese #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 2185a47a12beSStefan Roese #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 2186a47a12beSStefan Roese #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 2187a47a12beSStefan Roese #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 2188a47a12beSStefan Roese u32 pordbgmsr; /* POR debug mode status */ 2189a47a12beSStefan Roese u32 pordevsr2; /* POR I/O device status 2 */ 21904fd64746SYork Sun #if defined(CONFIG_ARCH_C29X) 21913b75e982SMingkai Hu #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 21923b75e982SMingkai Hu #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 21933b75e982SMingkai Hu #endif 21940a6b2714SAneesh Bansal #define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000 2195a47a12beSStefan Roese /* The 8544 RM says this is bit 26, but it's really bit 24 */ 2196a47a12beSStefan Roese #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 2197a47a12beSStefan Roese u8 res1[8]; 2198a47a12beSStefan Roese u32 gpporcr; /* General-purpose POR configuration */ 2199a47a12beSStefan Roese u8 res2[12]; 220024ad75aeSYork Sun #if defined(CONFIG_ARCH_MPC8536) 2201ae2044d8SXie Xiaobo u32 gencfgr; /* General Configuration Register */ 2202ae2044d8SXie Xiaobo #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 2203ae2044d8SXie Xiaobo #else 2204a47a12beSStefan Roese u32 gpiocr; /* GPIO control */ 2205ae2044d8SXie Xiaobo #endif 2206a47a12beSStefan Roese u8 res3[12]; 220723b36a7dSYork Sun #if defined(CONFIG_ARCH_MPC8569) 2208a47a12beSStefan Roese u32 plppar1; /* Platform port pin assignment 1 */ 2209a47a12beSStefan Roese u32 plppar2; /* Platform port pin assignment 2 */ 2210a47a12beSStefan Roese u32 plpdir1; /* Platform port pin direction 1 */ 2211a47a12beSStefan Roese u32 plpdir2; /* Platform port pin direction 2 */ 2212a47a12beSStefan Roese #else 2213a47a12beSStefan Roese u32 gpoutdr; /* General-purpose output data */ 2214a47a12beSStefan Roese u8 res4[12]; 2215a47a12beSStefan Roese #endif 2216a47a12beSStefan Roese u32 gpindr; /* General-purpose input data */ 2217a47a12beSStefan Roese u8 res5[12]; 2218a47a12beSStefan Roese u32 pmuxcr; /* Alt. function signal multiplex control */ 221946d9fc0bSYork Sun #if defined(CONFIG_ARCH_P1010) 22204b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 22214b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 22224b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 22234b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 22244b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 22254b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 22264b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 22274b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 22284b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 22294b77047cSDipen Dudhat #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 22304b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 22314b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 22324b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 22334b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 22344b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 22354b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 22364b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 22374b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 22384b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 22394b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 22404b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 22414b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 22424b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 22434b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 22444b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 22454b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 22464b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 22474b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 22484b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 22494b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 22504b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 22514b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 22524b77047cSDipen Dudhat #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 22534b77047cSDipen Dudhat #define MPC85xx_PMUXCR_LCLK_RES 0x00000040 22544b77047cSDipen Dudhat #define MPC85xx_PMUXCR_LCLK_USB 0x00000080 22554b77047cSDipen Dudhat #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 22564b77047cSDipen Dudhat #define MPC85xx_PMUXCR_SPI_RES 0x00000030 22574b77047cSDipen Dudhat #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 22584b77047cSDipen Dudhat #define MPC85xx_PMUXCR_CAN1_UART 0x00000004 22594b77047cSDipen Dudhat #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 22604b77047cSDipen Dudhat #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C 22614b77047cSDipen Dudhat #define MPC85xx_PMUXCR_CAN2_UART 0x00000001 22624b77047cSDipen Dudhat #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 22634b77047cSDipen Dudhat #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 22644b77047cSDipen Dudhat #endif 226541c7b7b1SYork Sun #if defined(CONFIG_ARCH_P1023) 2266fe1a1da0SRoy Zang #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 2267fe1a1da0SRoy Zang #else 2268a47a12beSStefan Roese #define MPC85xx_PMUXCR_SD_DATA 0x80000000 2269a47a12beSStefan Roese #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 2270a47a12beSStefan Roese #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 22712bad42a0SRamneek Mehresh #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 22724aa8405cSZhao Chenhui #define MPC85xx_PMUXCR_TDM_ENA 0x00800000 2273a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE0 0x00008000 2274a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE1 0x00004000 2275a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE2 0x00002000 2276a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE3 0x00001000 2277a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE4 0x00000800 2278a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE5 0x00000400 2279a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE6 0x00000200 2280a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE7 0x00000100 2281a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE8 0x00000080 2282a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE9 0x00000040 2283a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE10 0x00000020 2284a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE11 0x00000010 2285a52d2f81SHaiying Wang #define MPC85xx_PMUXCR_QE12 0x00000008 2286fe1a1da0SRoy Zang #endif 22872f8b8126SYork Sun #if defined(CONFIG_ARCH_P1022) 2288b93f81a4SJiang Yutang #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 2289b93f81a4SJiang Yutang #define MPC85xx_PMUXCR_TDM 0x00014800 2290b93f81a4SJiang Yutang #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 2291b93f81a4SJiang Yutang #define MPC85xx_PMUXCR_SPI 0x00000000 2292b93f81a4SJiang Yutang #endif 2293115d60c0SYork Sun #if defined(CONFIG_ARCH_BSC9131) 229419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 229519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 229619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 229719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 229819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 229919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 230019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 230119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 230219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 230319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 230419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 230519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 230619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 230719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 230819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 230919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 231019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 231119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 231219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 231319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 231419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 231519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 231619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 231719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 231819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 231919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 232019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 232119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 232219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 232319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 232419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 232519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 232619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 232719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 232819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 232919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 233019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 233119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 233219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C 233319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 233419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 233519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 233619a8dbdcSPrabhakar Kushwaha #endif 2337115d60c0SYork Sun #ifdef CONFIG_ARCH_BSC9132 233835fe948eSPrabhakar Kushwaha #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 233935fe948eSPrabhakar Kushwaha #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 234035fe948eSPrabhakar Kushwaha #endif 23414fd64746SYork Sun #if defined(CONFIG_ARCH_C29X) 23423b75e982SMingkai Hu #define MPC85xx_PMUXCR_SPI_MASK 0x00000300 23433b75e982SMingkai Hu #define MPC85xx_PMUXCR_SPI 0x00000000 23443b75e982SMingkai Hu #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 23453b75e982SMingkai Hu #endif 23466e37a044STimur Tabi u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ 234746d9fc0bSYork Sun #if defined(CONFIG_ARCH_P1010) 23484b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 23494b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 23504b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 23514b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 23524b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 23534b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 23544b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 23554b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 23564b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 23574b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 23584b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 23594b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 23604b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 23614b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 23624b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 23634b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 23644b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 23654b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 23664b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 23674b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 23684b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 23694b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 23704b77047cSDipen Dudhat #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 23714b77047cSDipen Dudhat #endif 23722f8b8126SYork Sun #if defined(CONFIG_ARCH_P1022) 2373aeb6716aSFelix Radensky #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 2374b93f81a4SJiang Yutang #define MPC85xx_PMUXCR2_USB 0x00150000 2375b93f81a4SJiang Yutang #endif 2376115d60c0SYork Sun #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) 2377115d60c0SYork Sun #if defined(CONFIG_ARCH_BSC9131) 237819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 237919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 238019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 238119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 238219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 238319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 238419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 238519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 238619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 238719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 238819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 238919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 239019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 239119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 239219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 239319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 239419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 239519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 239619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 239719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 239819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 239919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 240019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 240119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 240219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 240319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 240419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 240519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 240619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 240719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 240819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 240919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 241019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 241119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 241219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 241319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 241419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 241519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 241619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 241719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 241819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 241919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 242035fe948eSPrabhakar Kushwaha #endif 242119a8dbdcSPrabhakar Kushwaha u32 pmuxcr3; 2422115d60c0SYork Sun #if defined(CONFIG_ARCH_BSC9131) 242319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 242419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 242519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 242619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 242719a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 242819a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 242919a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 243019a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 243119a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 243219a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 243319a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 243419a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 243519a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 243619a8dbdcSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 243735fe948eSPrabhakar Kushwaha #endif 2438115d60c0SYork Sun #ifdef CONFIG_ARCH_BSC9132 243935fe948eSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 244035fe948eSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 244135fe948eSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 244235fe948eSPrabhakar Kushwaha #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000 244335fe948eSPrabhakar Kushwaha #endif 244419a8dbdcSPrabhakar Kushwaha u32 pmuxcr4; 244519a8dbdcSPrabhakar Kushwaha #else 24466e37a044STimur Tabi u8 res6[8]; 244719a8dbdcSPrabhakar Kushwaha #endif 2448a47a12beSStefan Roese u32 devdisr; /* Device disable control */ 2449a47a12beSStefan Roese #define MPC85xx_DEVDISR_PCI1 0x80000000 2450a47a12beSStefan Roese #define MPC85xx_DEVDISR_PCI2 0x40000000 2451a47a12beSStefan Roese #define MPC85xx_DEVDISR_PCIE 0x20000000 2452a47a12beSStefan Roese #define MPC85xx_DEVDISR_LBC 0x08000000 2453a47a12beSStefan Roese #define MPC85xx_DEVDISR_PCIE2 0x04000000 2454a47a12beSStefan Roese #define MPC85xx_DEVDISR_PCIE3 0x02000000 2455a47a12beSStefan Roese #define MPC85xx_DEVDISR_SEC 0x01000000 2456a47a12beSStefan Roese #define MPC85xx_DEVDISR_SRIO 0x00080000 2457a47a12beSStefan Roese #define MPC85xx_DEVDISR_RMSG 0x00040000 2458a47a12beSStefan Roese #define MPC85xx_DEVDISR_DDR 0x00010000 2459a47a12beSStefan Roese #define MPC85xx_DEVDISR_CPU 0x00008000 2460a47a12beSStefan Roese #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU 2461a47a12beSStefan Roese #define MPC85xx_DEVDISR_TB 0x00004000 2462a47a12beSStefan Roese #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB 2463a47a12beSStefan Roese #define MPC85xx_DEVDISR_CPU1 0x00002000 2464a47a12beSStefan Roese #define MPC85xx_DEVDISR_TB1 0x00001000 2465a47a12beSStefan Roese #define MPC85xx_DEVDISR_DMA 0x00000400 2466a47a12beSStefan Roese #define MPC85xx_DEVDISR_TSEC1 0x00000080 2467a47a12beSStefan Roese #define MPC85xx_DEVDISR_TSEC2 0x00000040 2468a47a12beSStefan Roese #define MPC85xx_DEVDISR_TSEC3 0x00000020 2469a47a12beSStefan Roese #define MPC85xx_DEVDISR_TSEC4 0x00000010 2470a47a12beSStefan Roese #define MPC85xx_DEVDISR_I2C 0x00000004 2471a47a12beSStefan Roese #define MPC85xx_DEVDISR_DUART 0x00000002 2472a47a12beSStefan Roese u8 res7[12]; 2473a47a12beSStefan Roese u32 powmgtcsr; /* Power management status & control */ 2474a47a12beSStefan Roese u8 res8[12]; 2475a47a12beSStefan Roese u32 mcpsumr; /* Machine check summary */ 2476a47a12beSStefan Roese u8 res9[12]; 2477a47a12beSStefan Roese u32 pvr; /* Processor version */ 2478a47a12beSStefan Roese u32 svr; /* System version */ 2479a52d2f81SHaiying Wang u8 res10[8]; 2480a47a12beSStefan Roese u32 rstcr; /* Reset control */ 248123b36a7dSYork Sun #if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569) 2482a52d2f81SHaiying Wang u8 res11a[76]; 2483a47a12beSStefan Roese par_io_t qe_par_io[7]; 2484a52d2f81SHaiying Wang u8 res11b[1600]; 24854167a67dSYork Sun #elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) 2486a52d2f81SHaiying Wang u8 res11a[12]; 2487a52d2f81SHaiying Wang u32 iovselsr; 2488a52d2f81SHaiying Wang u8 res11b[60]; 2489a52d2f81SHaiying Wang par_io_t qe_par_io[3]; 2490a52d2f81SHaiying Wang u8 res11c[1496]; 2491a47a12beSStefan Roese #else 2492a52d2f81SHaiying Wang u8 res11a[1868]; 2493a47a12beSStefan Roese #endif 24946e37a044STimur Tabi u32 clkdvdr; /* Clock Divide register */ 2495a52d2f81SHaiying Wang u8 res12[1532]; 2496a47a12beSStefan Roese u32 clkocr; /* Clock out select */ 2497a52d2f81SHaiying Wang u8 res13[12]; 2498a47a12beSStefan Roese u32 ddrdllcr; /* DDR DLL control */ 2499a52d2f81SHaiying Wang u8 res14[12]; 2500a47a12beSStefan Roese u32 lbcdllcr; /* LBC DLL control */ 2501115d60c0SYork Sun #if defined(CONFIG_ARCH_BSC9131) 250219a8dbdcSPrabhakar Kushwaha u8 res15[12]; 250319a8dbdcSPrabhakar Kushwaha u32 halt_req_mask; 250419a8dbdcSPrabhakar Kushwaha #define HALTED_TO_HALT_REQ_MASK_0 0x80000000 250519a8dbdcSPrabhakar Kushwaha u8 res18[232]; 250619a8dbdcSPrabhakar Kushwaha #else 2507a52d2f81SHaiying Wang u8 res15[248]; 250819a8dbdcSPrabhakar Kushwaha #endif 2509a47a12beSStefan Roese u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ 2510a47a12beSStefan Roese u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ 2511a47a12beSStefan Roese u32 ddrioovcr; /* DDR IO Override Control */ 2512a47a12beSStefan Roese u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ 2513a47a12beSStefan Roese u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ 25144aa8405cSZhao Chenhui u8 res16[52]; 25154aa8405cSZhao Chenhui u32 sdhcdcr; /* SDHC debug control register */ 25164aa8405cSZhao Chenhui u8 res17[61592]; 2517a47a12beSStefan Roese } ccsr_gur_t; 2518a47a12beSStefan Roese #endif 2519a47a12beSStefan Roese 25204aa8405cSZhao Chenhui #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ 25214aa8405cSZhao Chenhui 2522fd3cebd0SYork Sun #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 2523fd3cebd0SYork Sun #define MAX_SERDES 4 2524fbe44dd1SPaulo Zaneti #if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) 2525fbe44dd1SPaulo Zaneti #define SRDS_MAX_LANES 4 2526fbe44dd1SPaulo Zaneti #else 2527d1001e3fSYork Sun #define SRDS_MAX_LANES 8 2528fbe44dd1SPaulo Zaneti #endif 2529d1001e3fSYork Sun #define SRDS_MAX_BANK 2 2530fd3cebd0SYork Sun typedef struct serdes_corenet { 2531fd3cebd0SYork Sun struct { 2532fd3cebd0SYork Sun u32 rstctl; /* Reset Control Register */ 2533fd3cebd0SYork Sun #define SRDS_RSTCTL_RST 0x80000000 2534fd3cebd0SYork Sun #define SRDS_RSTCTL_RSTDONE 0x40000000 2535fd3cebd0SYork Sun #define SRDS_RSTCTL_RSTERR 0x20000000 2536fd3cebd0SYork Sun #define SRDS_RSTCTL_SWRST 0x10000000 25376fbe9889SShaveta Leekha #define SRDS_RSTCTL_SDEN 0x00000020 25386fbe9889SShaveta Leekha #define SRDS_RSTCTL_SDRST_B 0x00000040 25396fbe9889SShaveta Leekha #define SRDS_RSTCTL_PLLRST_B 0x00000080 25407af9a074SShaveta Leekha #define SRDS_RSTCTL_RSTERR_SHIFT 29 2541fd3cebd0SYork Sun u32 pllcr0; /* PLL Control Register 0 */ 2542fd3cebd0SYork Sun #define SRDS_PLLCR0_POFF 0x80000000 2543fd3cebd0SYork Sun #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 2544fd3cebd0SYork Sun #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2545fd3cebd0SYork Sun #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2546fd3cebd0SYork Sun #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2547fd3cebd0SYork Sun #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2548fd3cebd0SYork Sun #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 2549fd3cebd0SYork Sun #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 2550b6808cd8SShaveta Leekha #define SRDS_PLLCR0_PLL_LCK 0x00800000 25517af9a074SShaveta Leekha #define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000 2552fd3cebd0SYork Sun #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 2553fd3cebd0SYork Sun #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2554b6808cd8SShaveta Leekha #define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000 2555fd3cebd0SYork Sun #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 2556fd3cebd0SYork Sun #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 2557fd3cebd0SYork Sun #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 2558b6808cd8SShaveta Leekha #define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000 2559b6808cd8SShaveta Leekha #define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000 2560b6808cd8SShaveta Leekha #define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000 25617af9a074SShaveta Leekha #define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0 25627af9a074SShaveta Leekha #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4 2563fd3cebd0SYork Sun u32 pllcr1; /* PLL Control Register 1 */ 25647af9a074SShaveta Leekha #define SRDS_PLLCR1_BCAP_EN 0x20000000 25657af9a074SShaveta Leekha #define SRDS_PLLCR1_BCAP_OVD 0x10000000 25667af9a074SShaveta Leekha #define SRDS_PLLCR1_PLL_FCAP 0x001F8000 25677af9a074SShaveta Leekha #define SRDS_PLLCR1_PLL_FCAP_SHIFT 15 2568fd3cebd0SYork Sun #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 25697af9a074SShaveta Leekha #define SRDS_PLLCR1_BYP_CAL 0x02000000 25707af9a074SShaveta Leekha u32 pllsr2; /* At 0x00c, PLL Status Register 2 */ 25717af9a074SShaveta Leekha #define SRDS_PLLSR2_BCAP_EN 0x00800000 25727af9a074SShaveta Leekha #define SRDS_PLLSR2_BCAP_EN_SHIFT 23 25737af9a074SShaveta Leekha #define SRDS_PLLSR2_FCAP 0x003F0000 25747af9a074SShaveta Leekha #define SRDS_PLLSR2_FCAP_SHIFT 16 25757af9a074SShaveta Leekha #define SRDS_PLLSR2_DCBIAS 0x000F0000 25767af9a074SShaveta Leekha #define SRDS_PLLSR2_DCBIAS_SHIFT 16 2577fd3cebd0SYork Sun u32 pllcr3; 2578fd3cebd0SYork Sun u32 pllcr4; 2579fd3cebd0SYork Sun u8 res_18[0x20-0x18]; 2580fd3cebd0SYork Sun } bank[2]; 2581fd3cebd0SYork Sun u8 res_40[0x90-0x40]; 2582fd3cebd0SYork Sun u32 srdstcalcr; /* 0x90 TX Calibration Control */ 2583fd3cebd0SYork Sun u8 res_94[0xa0-0x94]; 2584fd3cebd0SYork Sun u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 2585fd3cebd0SYork Sun u8 res_a4[0xb0-0xa4]; 2586fd3cebd0SYork Sun u32 srdsgr0; /* 0xb0 General Register 0 */ 2587fd3cebd0SYork Sun u8 res_b4[0xe0-0xb4]; 2588fd3cebd0SYork Sun u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 2589fd3cebd0SYork Sun u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 2590fd3cebd0SYork Sun u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 2591fd3cebd0SYork Sun u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 2592fd3cebd0SYork Sun u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 2593fd3cebd0SYork Sun u8 res_f4[0x100-0xf4]; 2594fd3cebd0SYork Sun struct { 2595fd3cebd0SYork Sun u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 2596fd3cebd0SYork Sun u8 res_104[0x120-0x104]; 2597fd3cebd0SYork Sun } srdslnpssr[8]; 2598fd3cebd0SYork Sun u8 res_200[0x800-0x200]; 2599fd3cebd0SYork Sun struct { 2600fd3cebd0SYork Sun u32 gcr0; /* 0x800 General Control Register 0 */ 2601fd3cebd0SYork Sun u32 gcr1; /* 0x804 General Control Register 1 */ 2602fd3cebd0SYork Sun u32 gcr2; /* 0x808 General Control Register 2 */ 2603fd3cebd0SYork Sun u32 res_80c; 2604fd3cebd0SYork Sun u32 recr0; /* 0x810 Receive Equalization Control */ 2605fd3cebd0SYork Sun u32 res_814; 2606fd3cebd0SYork Sun u32 tecr0; /* 0x818 Transmit Equalization Control */ 2607fd3cebd0SYork Sun u32 res_81c; 2608fd3cebd0SYork Sun u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 2609fd3cebd0SYork Sun u8 res_824[0x840-0x824]; 2610fd3cebd0SYork Sun } lane[8]; /* Lane A, B, C, D, E, F, G, H */ 2611fd3cebd0SYork Sun u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 2612fd3cebd0SYork Sun } serdes_corenet_t; 2613fd3cebd0SYork Sun 2614fd3cebd0SYork Sun #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2615fd3cebd0SYork Sun 2616d1001e3fSYork Sun #define SRDS_MAX_LANES 18 2617d1001e3fSYork Sun #define SRDS_MAX_BANK 3 2618a47a12beSStefan Roese typedef struct serdes_corenet { 2619a47a12beSStefan Roese struct { 2620a47a12beSStefan Roese u32 rstctl; /* Reset Control Register */ 2621a47a12beSStefan Roese #define SRDS_RSTCTL_RST 0x80000000 2622a47a12beSStefan Roese #define SRDS_RSTCTL_RSTDONE 0x40000000 2623a47a12beSStefan Roese #define SRDS_RSTCTL_RSTERR 0x20000000 26241231c498SKumar Gala #define SRDS_RSTCTL_SDPD 0x00000020 2625a47a12beSStefan Roese u32 pllcr0; /* PLL Control Register 0 */ 2626f8f85b04SYork Sun #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 26274905443fSTimur Tabi #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000 26281231c498SKumar Gala #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 26291231c498SKumar Gala #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 26301231c498SKumar Gala #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2631e02aea61SKumar Gala #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2632f8f85b04SYork Sun #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 26331231c498SKumar Gala #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 26341231c498SKumar Gala #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 26351231c498SKumar Gala #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 2636a47a12beSStefan Roese u32 pllcr1; /* PLL Control Register 1 */ 2637a47a12beSStefan Roese #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2638a47a12beSStefan Roese u32 res[5]; 2639a47a12beSStefan Roese } bank[3]; 2640a47a12beSStefan Roese u32 res1[12]; 2641a47a12beSStefan Roese u32 srdstcalcr; /* TX Calibration Control */ 2642a47a12beSStefan Roese u32 res2[3]; 2643a47a12beSStefan Roese u32 srdsrcalcr; /* RX Calibration Control */ 2644a47a12beSStefan Roese u32 res3[3]; 2645a47a12beSStefan Roese u32 srdsgr0; /* General Register 0 */ 2646a47a12beSStefan Roese u32 res4[11]; 2647a47a12beSStefan Roese u32 srdspccr0; /* Protocol Converter Config 0 */ 2648a47a12beSStefan Roese u32 srdspccr1; /* Protocol Converter Config 1 */ 2649a47a12beSStefan Roese u32 srdspccr2; /* Protocol Converter Config 2 */ 2650a47a12beSStefan Roese #define SRDS_PCCR2_RST_XGMII1 0x00800000 2651a47a12beSStefan Roese #define SRDS_PCCR2_RST_XGMII2 0x00400000 2652a47a12beSStefan Roese u32 res5[197]; 2653d607b968STimur Tabi struct serdes_lane { 2654a47a12beSStefan Roese u32 gcr0; /* General Control Register 0 */ 2655a47a12beSStefan Roese #define SRDS_GCR0_RRST 0x00400000 2656a47a12beSStefan Roese #define SRDS_GCR0_1STLANE 0x00010000 26574905443fSTimur Tabi #define SRDS_GCR0_UOTHL 0x00100000 2658a47a12beSStefan Roese u32 gcr1; /* General Control Register 1 */ 2659a47a12beSStefan Roese #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 2660a47a12beSStefan Roese #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 2661a47a12beSStefan Roese #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 2662a47a12beSStefan Roese #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 2663a47a12beSStefan Roese #define SRDS_GCR1_OPAD_CTL 0x04000000 2664a47a12beSStefan Roese u32 res1[4]; 2665a47a12beSStefan Roese u32 tecr0; /* TX Equalization Control Reg 0 */ 2666a47a12beSStefan Roese #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 2667a47a12beSStefan Roese #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 2668a47a12beSStefan Roese u32 res3; 2669a47a12beSStefan Roese u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ 2670df8af0b4SEmil Medve #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 2671b25f6de7STimur Tabi #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000 2672b25f6de7STimur Tabi #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000 2673f68d3063STimur Tabi #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 2674df8af0b4SEmil Medve #define SRDS_TTLCR0_PM_DIS 0x00004000 2675b25f6de7STimur Tabi #define SRDS_TTLCR0_FREQOVD_EN 0x00000001 2676a47a12beSStefan Roese u32 res4[7]; 2677a47a12beSStefan Roese } lane[24]; 2678a47a12beSStefan Roese u32 res6[384]; 2679a47a12beSStefan Roese } serdes_corenet_t; 2680fd3cebd0SYork Sun #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2681a47a12beSStefan Roese 2682a47a12beSStefan Roese enum { 2683a47a12beSStefan Roese FSL_SRDS_B1_LANE_A = 0, 2684a47a12beSStefan Roese FSL_SRDS_B1_LANE_B = 1, 2685a47a12beSStefan Roese FSL_SRDS_B1_LANE_C = 2, 2686a47a12beSStefan Roese FSL_SRDS_B1_LANE_D = 3, 2687a47a12beSStefan Roese FSL_SRDS_B1_LANE_E = 4, 2688a47a12beSStefan Roese FSL_SRDS_B1_LANE_F = 5, 2689a47a12beSStefan Roese FSL_SRDS_B1_LANE_G = 6, 2690a47a12beSStefan Roese FSL_SRDS_B1_LANE_H = 7, 2691a47a12beSStefan Roese FSL_SRDS_B1_LANE_I = 8, 2692a47a12beSStefan Roese FSL_SRDS_B1_LANE_J = 9, 2693a47a12beSStefan Roese FSL_SRDS_B2_LANE_A = 16, 2694a47a12beSStefan Roese FSL_SRDS_B2_LANE_B = 17, 2695a47a12beSStefan Roese FSL_SRDS_B2_LANE_C = 18, 2696a47a12beSStefan Roese FSL_SRDS_B2_LANE_D = 19, 2697a47a12beSStefan Roese FSL_SRDS_B3_LANE_A = 20, 2698a47a12beSStefan Roese FSL_SRDS_B3_LANE_B = 21, 2699a47a12beSStefan Roese FSL_SRDS_B3_LANE_C = 22, 2700a47a12beSStefan Roese FSL_SRDS_B3_LANE_D = 23, 2701a47a12beSStefan Roese }; 2702a47a12beSStefan Roese 27039ab87d04SKumar Gala typedef struct ccsr_pme { 27049ab87d04SKumar Gala u8 res0[0x804]; 27059ab87d04SKumar Gala u32 liodnbr; /* LIODN Base Register */ 27069ab87d04SKumar Gala u8 res1[0x1f8]; 27079ab87d04SKumar Gala u32 srcidr; /* Source ID Register */ 27089ab87d04SKumar Gala u8 res2[8]; 27099ab87d04SKumar Gala u32 liodnr; /* LIODN Register */ 27109ab87d04SKumar Gala u8 res3[0x1e8]; 27119ab87d04SKumar Gala u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/ 27129ab87d04SKumar Gala u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/ 27139ab87d04SKumar Gala u8 res4[0x400]; 27149ab87d04SKumar Gala } ccsr_pme_t; 27159ab87d04SKumar Gala 2716f698e9f3SAneesh Bansal struct ccsr_pamu { 2717f698e9f3SAneesh Bansal u32 ppbah; 2718f698e9f3SAneesh Bansal u32 ppbal; 2719f698e9f3SAneesh Bansal u32 pplah; 2720f698e9f3SAneesh Bansal u32 pplal; 2721f698e9f3SAneesh Bansal u32 spbah; 2722f698e9f3SAneesh Bansal u32 spbal; 2723f698e9f3SAneesh Bansal u32 splah; 2724f698e9f3SAneesh Bansal u32 splal; 2725f698e9f3SAneesh Bansal u32 obah; 2726f698e9f3SAneesh Bansal u32 obal; 2727f698e9f3SAneesh Bansal u32 olah; 2728f698e9f3SAneesh Bansal u32 olal; 2729f698e9f3SAneesh Bansal }; 2730f698e9f3SAneesh Bansal 27316b3a8d00SKumar Gala #ifdef CONFIG_SYS_FSL_RAID_ENGINE 27326b3a8d00SKumar Gala struct ccsr_raide { 27336b3a8d00SKumar Gala u8 res0[0x543]; 27346b3a8d00SKumar Gala u32 liodnbr; /* LIODN Base Register */ 27356b3a8d00SKumar Gala u8 res1[0xab8]; 27366b3a8d00SKumar Gala struct { 27376b3a8d00SKumar Gala struct { 27386b3a8d00SKumar Gala u32 cfg0; /* cfg register 0 */ 27396b3a8d00SKumar Gala u32 cfg1; /* cfg register 1 */ 27406b3a8d00SKumar Gala u8 res1[0x3f8]; 27416b3a8d00SKumar Gala } ring[2]; 27426b3a8d00SKumar Gala u8 res[0x800]; 27436b3a8d00SKumar Gala } jq[2]; 27446b3a8d00SKumar Gala }; 27456b3a8d00SKumar Gala #endif 27466b3a8d00SKumar Gala 27474d28db8aSKumar Gala #ifdef CONFIG_SYS_DPAA_RMAN 27484d28db8aSKumar Gala struct ccsr_rman { 27494d28db8aSKumar Gala u8 res0[0xf64]; 27504d28db8aSKumar Gala u32 mmliodnbr; /* Message Manager LIODN Base Register */ 27514d28db8aSKumar Gala u32 mmitar; /* RMAN Inbound Translation Address Register */ 27524d28db8aSKumar Gala u32 mmitdr; /* RMAN Inbound Translation Data Register */ 27534d28db8aSKumar Gala u8 res4[0x1f090]; 27544d28db8aSKumar Gala }; 27554d28db8aSKumar Gala #endif 27564d28db8aSKumar Gala 2757f311838dSAndy Fleming #ifdef CONFIG_SYS_PMAN 2758f311838dSAndy Fleming struct ccsr_pman { 2759f311838dSAndy Fleming u8 res_00[0x40]; 2760f311838dSAndy Fleming u32 poes1; /* PMAN Operation Error Status Register 1 */ 2761f311838dSAndy Fleming u32 poes2; /* PMAN Operation Error Status Register 2 */ 2762f311838dSAndy Fleming u32 poeah; /* PMAN Operation Error Address High */ 2763f311838dSAndy Fleming u32 poeal; /* PMAN Operation Error Address Low */ 2764f311838dSAndy Fleming u8 res_50[0x50]; 2765f311838dSAndy Fleming u32 pr1; /* PMAN Revision Register 1 */ 2766f311838dSAndy Fleming u32 pr2; /* PMAN Revision Register 2 */ 2767f311838dSAndy Fleming u8 res_a8[0x8]; 2768f311838dSAndy Fleming u32 pcap; /* PMAN Capabilities Register */ 2769f311838dSAndy Fleming u8 res_b4[0xc]; 2770f311838dSAndy Fleming u32 pc1; /* PMAN Control Register 1 */ 2771f311838dSAndy Fleming u32 pc2; /* PMAN Control Register 2 */ 2772f311838dSAndy Fleming u32 pc3; /* PMAN Control Register 3 */ 2773f311838dSAndy Fleming u32 pc4; /* PMAN Control Register 4 */ 2774f311838dSAndy Fleming u32 pc5; /* PMAN Control Register 5 */ 2775f311838dSAndy Fleming u32 pc6; /* PMAN Control Register 6 */ 2776f311838dSAndy Fleming u8 res_d8[0x8]; 2777f311838dSAndy Fleming u32 ppa1; /* PMAN Prefetch Attributes Register 1 */ 2778f311838dSAndy Fleming u32 ppa2; /* PMAN Prefetch Attributes Register 2 */ 2779f311838dSAndy Fleming u8 res_e8[0x8]; 2780f311838dSAndy Fleming u32 pics; /* PMAN Interrupt Control and Status */ 2781f311838dSAndy Fleming u8 res_f4[0xf0c]; 2782f311838dSAndy Fleming }; 2783f311838dSAndy Fleming #endif 2784f311838dSAndy Fleming 2785a47a12beSStefan Roese #ifdef CONFIG_FSL_CORENET 2786a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 2787f311838dSAndy Fleming #ifdef CONFIG_SYS_PMAN 2788f311838dSAndy Fleming #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 2789f311838dSAndy Fleming #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 2790f311838dSAndy Fleming #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 2791f311838dSAndy Fleming #endif 2792e76cd5d4SAndy Fleming #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000 2793e76cd5d4SAndy Fleming #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 2794e76cd5d4SAndy Fleming #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 2795a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 2796a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 2797b6808cd8SShaveta Leekha #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 2798b6808cd8SShaveta Leekha /* In SFPv3, OSPR register is now at offset 0x200. 2799b6808cd8SShaveta Leekha * * So directly mapping sfp register map to this address */ 2800b6808cd8SShaveta Leekha #define CONFIG_SYS_OSPR_OFFSET 0x200 2801b6808cd8SShaveta Leekha #define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) 2802b6808cd8SShaveta Leekha #else 2803b6808cd8SShaveta Leekha #define CONFIG_SYS_SFP_OFFSET 0xE8000 2804b6808cd8SShaveta Leekha #endif 2805a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 28064905443fSTimur Tabi #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 2807e55782ecSShaohui Xie #define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 2808e55782ecSShaohui Xie #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 2809a47a12beSStefan Roese #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 2810bf4699dbSPriyanka Jain #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 2811f698e9f3SAneesh Bansal #define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000 28129ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 28139ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 2814629d6b32SShengzhou Liu #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 28159ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET 2816a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 2817a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 2818a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 281950d96e95SKumar Gala #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 2820a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 2821377ffcfaSSandeep Singh #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 28222a44efebSZhao Qiang #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 28234d28db8aSKumar Gala #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 2824b41f192bSYork Sun #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ 2825b41f192bSYork Sun !defined(CONFIG_ARCH_B4420) 28269e758758SYork Sun #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 28279e758758SYork Sun #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 28289e758758SYork Sun #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 28299e758758SYork Sun #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 28309e758758SYork Sun #else 28319ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 28329ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 28339ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 28349ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 28359e758758SYork Sun #endif 28369ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 28379ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 283886221f09SRoy Zang #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 283986221f09SRoy Zang #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 28409ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 28419ab87d04SKumar Gala #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 284222f292c7SKim Phillips #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 2843b9eebfadSRuchika Gupta #define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 2844e04916a7Sgaurav rana #define CONFIG_SYS_SEC_MON_OFFSET 0x314000 28459ab87d04SKumar Gala #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 284624995d82SHaiying Wang #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 284724995d82SHaiying Wang #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 28486b3a8d00SKumar Gala #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 28499ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 28509ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 28519ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 28529ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 28539ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 28549ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 2855f311838dSAndy Fleming #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 28569ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 2857f311838dSAndy Fleming #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 28589ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 28599ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 28609ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 28619ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 28629ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 28639ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 28649ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 2865f311838dSAndy Fleming #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 28669ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 2867f311838dSAndy Fleming #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 28686d2b9da1SYork Sun #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 2869a47a12beSStefan Roese #else 2870a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 2871e76cd5d4SAndy Fleming #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 2872a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 2873e76cd5d4SAndy Fleming #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 2874a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 287599d9c07eSKumar Gala #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 2876a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 287799d9c07eSKumar Gala #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 2878a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 287999d9c07eSKumar Gala #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 288099d9c07eSKumar Gala #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 28814593637bSYork Sun #if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) 288299d9c07eSKumar Gala #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 288399d9c07eSKumar Gala #else 288499d9c07eSKumar Gala #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 288599d9c07eSKumar Gala #endif 2886a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 2887a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 2888a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 2889d789b5f5SDipen Dudhat #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 2890a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 2891a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 289277354e9dSramneek mehresh #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 28939839709eSIra W. Snyder #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 289415a6d496SSriram Dash #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 289515a6d496SSriram Dash #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 2896a47a12beSStefan Roese #ifdef CONFIG_TSECV2 2897a47a12beSStefan Roese #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 28983b75e982SMingkai Hu #elif defined(CONFIG_TSECV2_1) 28993b75e982SMingkai Hu #define CONFIG_SYS_TSEC1_OFFSET 0x10000 2900a47a12beSStefan Roese #else 2901a47a12beSStefan Roese #define CONFIG_SYS_TSEC1_OFFSET 0x24000 2902a47a12beSStefan Roese #endif 2903a47a12beSStefan Roese #define CONFIG_SYS_MDIO1_OFFSET 0x24000 2904a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 29054fd64746SYork Sun #if defined(CONFIG_ARCH_C29X) 29063b75e982SMingkai Hu #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 2907b9eebfadSRuchika Gupta #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 29083b75e982SMingkai Hu #else 29095e95e2d8SVakul Garg #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 2910b9eebfadSRuchika Gupta #define CONFIG_SYS_FSL_JR0_OFFSET 0x31000 29113b75e982SMingkai Hu #endif 2912a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 2913a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 2914e04916a7Sgaurav rana #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 29157065b7d4SRuchika Gupta #define CONFIG_SYS_SFP_OFFSET 0xE7000 2916a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 291767a719daSRoy Zang #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 291867a719daSRoy Zang #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 291967a719daSRoy Zang #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 292067a719daSRoy Zang #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 292167a719daSRoy Zang #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 292267a719daSRoy Zang #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 2923a47a12beSStefan Roese #endif 2924a47a12beSStefan Roese 2925a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 2926a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 29275ffa88ecSLiu Gang #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 2928a47a12beSStefan Roese 2929115d60c0SYork Sun #if defined(CONFIG_ARCH_BSC9132) 2930f9d379a7SPriyanka Jain #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 2931f9d379a7SPriyanka Jain #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ 2932f9d379a7SPriyanka Jain (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) 2933f9d379a7SPriyanka Jain #endif 2934f9d379a7SPriyanka Jain 2935a47a12beSStefan Roese #define CONFIG_SYS_FSL_CPC_ADDR \ 2936a47a12beSStefan Roese (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) 2937bf4699dbSPriyanka Jain #define CONFIG_SYS_FSL_SCFG_ADDR \ 2938bf4699dbSPriyanka Jain (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) 2939bf4699dbSPriyanka Jain #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ 2940bf4699dbSPriyanka Jain (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) 29415818643bSShengzhou Liu #define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ 29425818643bSShengzhou Liu (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) 294324995d82SHaiying Wang #define CONFIG_SYS_FSL_QMAN_ADDR \ 294424995d82SHaiying Wang (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) 294524995d82SHaiying Wang #define CONFIG_SYS_FSL_BMAN_ADDR \ 294624995d82SHaiying Wang (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) 29479ab87d04SKumar Gala #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ 29489ab87d04SKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) 29496b3a8d00SKumar Gala #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ 29506b3a8d00SKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) 29514d28db8aSKumar Gala #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ 29524d28db8aSKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) 2953a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ 2954a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) 2955a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ 2956a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) 2957a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ 2958a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) 2959a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ 2960a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) 2961a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ECM_ADDR \ 2962a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) 29635614e71bSYork Sun #define CONFIG_SYS_FSL_DDR_ADDR \ 2964e76cd5d4SAndy Fleming (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) 29655614e71bSYork Sun #define CONFIG_SYS_FSL_DDR2_ADDR \ 2966e76cd5d4SAndy Fleming (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) 29675614e71bSYork Sun #define CONFIG_SYS_FSL_DDR3_ADDR \ 2968e76cd5d4SAndy Fleming (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) 2969f51cdaf1SBecky Bruce #define CONFIG_SYS_LBC_ADDR \ 2970a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) 2971d789b5f5SDipen Dudhat #define CONFIG_SYS_IFC_ADDR \ 2972d789b5f5SDipen Dudhat (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) 2973a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ 2974a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) 2975a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ 2976a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) 2977a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ 2978a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) 2979a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_GPIO_ADDR \ 2980a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) 2981a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SATA1_ADDR \ 2982a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) 2983a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SATA2_ADDR \ 2984a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) 2985a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_L2_ADDR \ 2986a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) 2987a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_DMA_ADDR \ 2988a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) 2989a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ 2990a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) 2991680c613aSKim Phillips #define CONFIG_SYS_MPC8xxx_PIC_ADDR \ 2992a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) 2993a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_CPM_ADDR \ 2994a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) 2995a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ 299617028be2SPrabhakar (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) 2997a47a12beSStefan Roese #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ 2998a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 2999a47a12beSStefan Roese #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ 3000a47a12beSStefan Roese (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) 30014905443fSTimur Tabi #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ 30024905443fSTimur Tabi (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) 3003e55782ecSShaohui Xie #define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \ 3004e55782ecSShaohui Xie (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) 3005e55782ecSShaohui Xie #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ 3006e55782ecSShaohui Xie (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) 300777354e9dSramneek mehresh #define CONFIG_SYS_MPC85xx_USB1_ADDR \ 300877354e9dSramneek mehresh (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) 300977354e9dSramneek mehresh #define CONFIG_SYS_MPC85xx_USB2_ADDR \ 301077354e9dSramneek mehresh (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET) 301186221f09SRoy Zang #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ 301286221f09SRoy Zang (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) 301386221f09SRoy Zang #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ 301486221f09SRoy Zang (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) 301522f292c7SKim Phillips #define CONFIG_SYS_FSL_SEC_ADDR \ 301622f292c7SKim Phillips (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 3017b9eebfadSRuchika Gupta #define CONFIG_SYS_FSL_JR0_ADDR \ 3018b9eebfadSRuchika Gupta (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 30199ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_ADDR \ 30209ab87d04SKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 30219ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 30229ab87d04SKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 30239ab87d04SKumar Gala #define CONFIG_SYS_FSL_FM2_ADDR \ 30249ab87d04SKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) 30255ffa88ecSLiu Gang #define CONFIG_SYS_FSL_SRIO_ADDR \ 30265ffa88ecSLiu Gang (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) 3027f698e9f3SAneesh Bansal #define CONFIG_SYS_PAMU_ADDR \ 3028f698e9f3SAneesh Bansal (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET) 3029a47a12beSStefan Roese 303099d9c07eSKumar Gala #define CONFIG_SYS_PCI1_ADDR \ 303199d9c07eSKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) 303299d9c07eSKumar Gala #define CONFIG_SYS_PCI2_ADDR \ 303399d9c07eSKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) 303499d9c07eSKumar Gala #define CONFIG_SYS_PCIE1_ADDR \ 303599d9c07eSKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) 303699d9c07eSKumar Gala #define CONFIG_SYS_PCIE2_ADDR \ 303799d9c07eSKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) 303899d9c07eSKumar Gala #define CONFIG_SYS_PCIE3_ADDR \ 303999d9c07eSKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) 30409ab87d04SKumar Gala #define CONFIG_SYS_PCIE4_ADDR \ 30419ab87d04SKumar Gala (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) 304299d9c07eSKumar Gala 3043b6808cd8SShaveta Leekha #define CONFIG_SYS_SFP_ADDR \ 3044b6808cd8SShaveta Leekha (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) 3045b6808cd8SShaveta Leekha 3046e04916a7Sgaurav rana #define CONFIG_SYS_SEC_MON_ADDR \ 3047e04916a7Sgaurav rana (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) 3048e04916a7Sgaurav rana 3049a47a12beSStefan Roese #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 3050a47a12beSStefan Roese #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 3051a47a12beSStefan Roese 30526d2b9da1SYork Sun #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 30536d2b9da1SYork Sun struct ccsr_cluster_l2 { 30546d2b9da1SYork Sun u32 l2csr0; /* 0x000 L2 cache control and status register 0 */ 30556d2b9da1SYork Sun u32 l2csr1; /* 0x004 L2 cache control and status register 1 */ 30566d2b9da1SYork Sun u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */ 30576d2b9da1SYork Sun u8 res_0c[500];/* 0x00c - 0x1ff */ 30586d2b9da1SYork Sun u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */ 30596d2b9da1SYork Sun u8 res_204[4]; 30606d2b9da1SYork Sun u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */ 30616d2b9da1SYork Sun u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */ 30626d2b9da1SYork Sun u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */ 30636d2b9da1SYork Sun u8 res_214[4]; 30646d2b9da1SYork Sun u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */ 30656d2b9da1SYork Sun u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */ 30666d2b9da1SYork Sun u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */ 30676d2b9da1SYork Sun u8 res_224[4]; 30686d2b9da1SYork Sun u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */ 30696d2b9da1SYork Sun u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */ 30706d2b9da1SYork Sun u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */ 30716d2b9da1SYork Sun u8 res_234[4]; 30726d2b9da1SYork Sun u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */ 30736d2b9da1SYork Sun u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */ 30746d2b9da1SYork Sun u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */ 30756d2b9da1SYork Sun u8 res244[4]; 30766d2b9da1SYork Sun u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */ 30776d2b9da1SYork Sun u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */ 30786d2b9da1SYork Sun u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */ 30796d2b9da1SYork Sun u8 res_254[4]; 30806d2b9da1SYork Sun u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */ 30816d2b9da1SYork Sun u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */ 30826d2b9da1SYork Sun u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */ 30836d2b9da1SYork Sun u8 res_264[4]; 30846d2b9da1SYork Sun u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */ 30856d2b9da1SYork Sun u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */ 30866d2b9da1SYork Sun u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */ 30876d2b9da1SYork Sun u8 res274[4]; 30886d2b9da1SYork Sun u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */ 30896d2b9da1SYork Sun u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */ 30906d2b9da1SYork Sun u8 res_280[0xb80]; /* 0x280 - 0xdff */ 30916d2b9da1SYork Sun u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */ 30926d2b9da1SYork Sun u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */ 30936d2b9da1SYork Sun u32 l2errinjctl;/* 0xe08 L2 cache error injection control */ 30946d2b9da1SYork Sun u8 res_e0c[20]; /* 0xe0c - 0x01f */ 30956d2b9da1SYork Sun u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */ 30966d2b9da1SYork Sun u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */ 30976d2b9da1SYork Sun u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */ 30986d2b9da1SYork Sun u8 res_e2c[20]; /* 0xe2c - 0xe3f */ 30996d2b9da1SYork Sun u32 l2errdet; /* 0xe40 L2 cache error detect */ 31006d2b9da1SYork Sun u32 l2errdis; /* 0xe44 L2 cache error disable */ 31016d2b9da1SYork Sun u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */ 31026d2b9da1SYork Sun u32 l2errattr; /* 0xe4c L2 cache error attribute */ 31036d2b9da1SYork Sun u32 l2erreaddr; /* 0xe50 L2 cache error extended address */ 31046d2b9da1SYork Sun u32 l2erraddr; /* 0xe54 L2 cache error address */ 31056d2b9da1SYork Sun u32 l2errctl; /* 0xe58 L2 cache error control */ 31066d2b9da1SYork Sun }; 31076d2b9da1SYork Sun #define CONFIG_SYS_FSL_CLUSTER_1_L2 \ 31086d2b9da1SYork Sun (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) 31096d2b9da1SYork Sun #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 311099d7b0a4SXulei 311199d7b0a4SXulei #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 311299d7b0a4SXulei struct dcsr_dcfg_regs { 311399d7b0a4SXulei u8 res_0[0x520]; 311499d7b0a4SXulei u32 ecccr1; 311599d7b0a4SXulei #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000 311699d7b0a4SXulei #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 311799d7b0a4SXulei u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ 311899d7b0a4SXulei }; 31195aef4c86STang Yuantian 31205aef4c86STang Yuantian #define CONFIG_SYS_MPC85xx_SCFG \ 31215aef4c86STang Yuantian (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) 31225aef4c86STang Yuantian #define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 31235aef4c86STang Yuantian /* The supplement configuration unit register */ 31245aef4c86STang Yuantian struct ccsr_scfg { 31255aef4c86STang Yuantian u32 dpslpcr; /* 0x000 Deep Sleep Control register */ 31265aef4c86STang Yuantian u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */ 31275aef4c86STang Yuantian u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */ 31285aef4c86STang Yuantian u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */ 31295aef4c86STang Yuantian u32 res1[4]; 31305aef4c86STang Yuantian u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */ 31315aef4c86STang Yuantian u32 res2; 31325aef4c86STang Yuantian u32 pixclkcr; /* 0x028 Pixel Clock Control register */ 31335aef4c86STang Yuantian u32 res3[245]; 31345aef4c86STang Yuantian u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */ 31355aef4c86STang Yuantian u32 emiiocr; /* 0x404 EMI MDIO Control Register */ 31365aef4c86STang Yuantian u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */ 31375aef4c86STang Yuantian u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */ 31385aef4c86STang Yuantian u32 res4[60]; 31395aef4c86STang Yuantian u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ 31405aef4c86STang Yuantian }; 3141a47a12beSStefan Roese #endif /*__IMMAP_85xx__*/ 3142