target/mips/cpu.h

4 #include "cpu-qom.h"
5 #include "exec/cpu-common.h"
6 #include "exec/cpu-defs.h"
7 #include "exec/cpu-interrupt.h"
11 #include "fpu/softfloat-types.h"
13 #include "mips-defs.h"
32     uint64_t d;    /* binary double fixed-point */
33     uint32_t w[2]; /* binary single fixed-point */
34 /* FPU/MSA register mapping is not tested on big-endian hosts. */
143  *     ----------        ----------        ----------        ----------
156  *     ----------        ----------        ----------        ----------
169  *     ----------        ----------        -----------       -----------
182  *     -----------       -----------       -----------       -----------
195  *     -----------       -----------       -----------       -----------
208  *     -----------       -----------       -----------       -----------
221  *     -----------       -----------       -----------       -----------
234  *     -----------       -----------       -----------       -----------
466      * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
517     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
543 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
988     /* XXX: Maybe make LLAddr per-TC? */
1118 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
1121 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
1124      * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1129 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
1146 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
1147 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
1151     /* MIPS DSP resources access. */
1152 #define MIPS_HFLAG_DSP    0x080000   /* Enable access to DSP resources.    */
1153 #define MIPS_HFLAG_DSP_R2 0x100000   /* Enable access to DSP R2 resources. */
1154 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1191     QEMUTimer *timer; /* Internal timer */  member
1256     return hflags_mmu_index(env->hflags);  in mips_env_mmu_index()
1261     EXCP_NONE          = -1,
1319 /* Check presence of MIPS-3D ASE */
1322     return env->active_fpu.fcr0 & (1 << FCR0_3D);  in ase_3d_available()
1328     return env->CP0_Config3 & (1 << CP0C3_MSAP);  in ase_msa_available()
1334     return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);  in ase_lcsr_available()
1337 /* Check presence of multi-threading ASE implementation */
1340     return env->CP0_Config3 & (1 << CP0C3_MT);  in ase_mt_available()