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/openbmc/linux/drivers/net/ethernet/8390/
H A Dlib8390.c260 int txsr, isr, tickssofar = jiffies - dev_trans_start(dev); in __ei_tx_timeout() local
266 txsr = ei_inb(e8390_base+EN0_TSR); in __ei_tx_timeout()
271 (txsr & ENTSR_ABT) ? "excess collisions." : in __ei_tx_timeout()
273 txsr, isr, tickssofar); in __ei_tx_timeout()
538 unsigned char txsr = ei_inb_p(e8390_base+EN0_TSR); in ei_tx_err() local
539 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU); in ei_tx_err()
542 netdev_dbg(dev, "transmitter error (%#2x):", txsr); in ei_tx_err()
543 if (txsr & ENTSR_ABT) in ei_tx_err()
545 if (txsr & ENTSR_ND) in ei_tx_err()
547 if (txsr & ENTSR_CRS) in ei_tx_err()
[all …]
H A Daxnet_cs.c913 int txsr, isr, tickssofar = jiffies - dev_trans_start(dev); in axnet_tx_timeout() local
919 txsr = inb(e8390_base+EN0_TSR); in axnet_tx_timeout()
924 (txsr & ENTSR_ABT) ? "excess collisions." : in axnet_tx_timeout()
926 txsr, isr, tickssofar); in axnet_tx_timeout()
1214 unsigned char txsr = inb_p(e8390_base+EN0_TSR); in ei_tx_err() local
1215 unsigned char tx_was_aborted = txsr & (ENTSR_ABT+ENTSR_FU); in ei_tx_err()
1218 netdev_dbg(dev, "transmitter error (%#2x):", txsr); in ei_tx_err()
1219 if (txsr & ENTSR_ABT) in ei_tx_err()
1221 if (txsr & ENTSR_ND) in ei_tx_err()
1223 if (txsr & ENTSR_CRS) in ei_tx_err()
[all …]
/openbmc/u-boot/board/work-microwave/work_92105/
H A Dwork_92105_spl.c29 .txsr = 12500000,
49 .txsr = 8333333,
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c32 .tXSR = 140,
56 .tXSR = 140,
H A Dsdram_elpida.c199 .tXSR = 140,
222 .tXSR = 140,
245 .tXSR = 140,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr3.yaml168 tXSR-min-tck:
218 tXSR-min-tck = <12>;
241 tXSR = <70000>;
H A Djedec,lpddr3-timings.yaml119 tXSR:
155 tXSR = <70000>;
/openbmc/linux/drivers/memory/
H A Dof_memory.c191 ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR); in of_lpddr3_get_min_tck()
234 ret |= of_property_read_u32(np, "tXSR", &tim->tXSR); in of_lpddr3_do_get_timings()
H A Djedec_ddr.h244 u32 tXSR; member
273 u32 tXSR; member
/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c121 u8 txsr; member
201 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
211 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dddrmc-vf610.h45 u16 txsr; member
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt20 txsr
/openbmc/u-boot/board/timll/devkit3250/
H A Ddevkit3250_spl.c36 .txsr = 12500000,
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Demif.c33 .tXSR = 140,
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h90 u32 txsr; member
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c47 writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Demc.h49 u32 txsr; /* 0x90: EMC_TXSR */ member
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h39 #define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns)…
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h82 #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ argument
86 ACTIM_CTRLB_TXSR(txsr)
/openbmc/u-boot/drivers/net/
H A Dzynq_gem.c135 u32 txsr; /* 0x14 - TX Status reg */ member
409 writel(0, &regs->txsr); in zynq_gem_init()
582 return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE, in zynq_gem_send()
/openbmc/linux/drivers/tty/serial/
H A Dmpc52xx_uart.c448 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); in mpc512x_psc_raw_tx_rdy()
460 return in_be32(&FIFO_512x(port)->txsr) in mpc512x_psc_tx_rdy()
467 return in_be32(&FIFO_512x(port)->txsr) in mpc512x_psc_tx_empty()
789 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL); in mpc5125_psc_raw_tx_rdy()
800 return in_be32(&FIFO_5125(port)->txsr) & in mpc5125_psc_tx_rdy()
806 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY; in mpc5125_psc_tx_empty()
/openbmc/u-boot/board/phytec/pcm052/
H A Dpcm052.c241 .txsr = 506, in dram_init()
296 .txsr = 512, in dram_init()
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1025 txsr = DIV_ROUND_UP(140000, clkper) - 1; in mx6_lpddr2_cfg()
1029 txsr = DIV_ROUND_UP(220000, clkper) - 1; in mx6_lpddr2_cfg()
1084 debug("txsr=%d\n", txsr); in mx6_lpddr2_cfg()
1140 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) | in mx6_lpddr2_cfg()
/openbmc/u-boot/include/configs/
H A Dpm9263.h93 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610.c158 DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]); in ddrmc_ctrl_init_ddr3()

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