1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2412ae53aSAlbert ARIBAUD \(3ADEV\) /*
3412ae53aSAlbert ARIBAUD \(3ADEV\) * LPC32xx dram init
4412ae53aSAlbert ARIBAUD \(3ADEV\) *
5412ae53aSAlbert ARIBAUD \(3ADEV\) * (C) Copyright 2014 DENX Software Engineering GmbH
6412ae53aSAlbert ARIBAUD \(3ADEV\) * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
7412ae53aSAlbert ARIBAUD \(3ADEV\) *
8412ae53aSAlbert ARIBAUD \(3ADEV\) * This is called by SPL to gain access to the SDR DRAM.
9412ae53aSAlbert ARIBAUD \(3ADEV\) *
10412ae53aSAlbert ARIBAUD \(3ADEV\) * This code runs from SRAM.
11412ae53aSAlbert ARIBAUD \(3ADEV\) */
12412ae53aSAlbert ARIBAUD \(3ADEV\)
13412ae53aSAlbert ARIBAUD \(3ADEV\) #include <common.h>
14412ae53aSAlbert ARIBAUD \(3ADEV\) #include <netdev.h>
15412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/cpu.h>
16412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/clk.h>
17412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/wdt.h>
18412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/emc.h>
19412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/io.h>
20412ae53aSAlbert ARIBAUD \(3ADEV\)
21412ae53aSAlbert ARIBAUD \(3ADEV\) static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
22412ae53aSAlbert ARIBAUD \(3ADEV\) static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
23412ae53aSAlbert ARIBAUD \(3ADEV\)
ddr_init(struct emc_dram_settings * dram)24412ae53aSAlbert ARIBAUD \(3ADEV\) void ddr_init(struct emc_dram_settings *dram)
25412ae53aSAlbert ARIBAUD \(3ADEV\) {
26412ae53aSAlbert ARIBAUD \(3ADEV\) uint32_t ck;
27412ae53aSAlbert ARIBAUD \(3ADEV\)
28412ae53aSAlbert ARIBAUD \(3ADEV\) /* Enable EMC interface and choose little endian mode */
29412ae53aSAlbert ARIBAUD \(3ADEV\) writel(1, &emc->ctrl);
30412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0, &emc->config);
31412ae53aSAlbert ARIBAUD \(3ADEV\) /* Select maximum EMC Dynamic Memory Refresh Time */
32412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0x7FF, &emc->refresh);
33412ae53aSAlbert ARIBAUD \(3ADEV\) /* Determine CLK */
34412ae53aSAlbert ARIBAUD \(3ADEV\) ck = get_sdram_clk_rate();
35412ae53aSAlbert ARIBAUD \(3ADEV\) /* Configure SDRAM */
36412ae53aSAlbert ARIBAUD \(3ADEV\) writel(dram->cmddelay, &clk->sdramclk_ctrl);
37412ae53aSAlbert ARIBAUD \(3ADEV\) writel(dram->config0, &emc->config0);
38412ae53aSAlbert ARIBAUD \(3ADEV\) writel(dram->rascas0, &emc->rascas0);
39412ae53aSAlbert ARIBAUD \(3ADEV\) writel(dram->rdconfig, &emc->read_config);
40412ae53aSAlbert ARIBAUD \(3ADEV\) /* Set timings */
41412ae53aSAlbert ARIBAUD \(3ADEV\) writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
42412ae53aSAlbert ARIBAUD \(3ADEV\) writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
43412ae53aSAlbert ARIBAUD \(3ADEV\) writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
44412ae53aSAlbert ARIBAUD \(3ADEV\) writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
45412ae53aSAlbert ARIBAUD \(3ADEV\) writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
46412ae53aSAlbert ARIBAUD \(3ADEV\) writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
47412ae53aSAlbert ARIBAUD \(3ADEV\) writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
48412ae53aSAlbert ARIBAUD \(3ADEV\) writel(dram->trrd, &emc->t_rrd);
49412ae53aSAlbert ARIBAUD \(3ADEV\) writel(dram->tmrd, &emc->t_mrd);
50412ae53aSAlbert ARIBAUD \(3ADEV\) writel(dram->tcdlr, &emc->t_cdlr);
51412ae53aSAlbert ARIBAUD \(3ADEV\) /* Dynamic refresh */
52412ae53aSAlbert ARIBAUD \(3ADEV\) writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
53412ae53aSAlbert ARIBAUD \(3ADEV\) udelay(10);
54412ae53aSAlbert ARIBAUD \(3ADEV\) /* Force all clocks, enable inverted ck, issue NOP command */
55412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0x00000193, &emc->control);
56412ae53aSAlbert ARIBAUD \(3ADEV\) udelay(100);
57412ae53aSAlbert ARIBAUD \(3ADEV\) /* Keep all clocks enabled, issue a PRECHARGE ALL command */
58412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0x00000113, &emc->control);
59412ae53aSAlbert ARIBAUD \(3ADEV\) /* Fast dynamic refresh for at least a few SDRAM ck cycles */
60412ae53aSAlbert ARIBAUD \(3ADEV\) writel((((128) >> 4) & 0x7FF), &emc->refresh);
61412ae53aSAlbert ARIBAUD \(3ADEV\) udelay(10);
62412ae53aSAlbert ARIBAUD \(3ADEV\) /* set correct dynamic refresh timing */
63412ae53aSAlbert ARIBAUD \(3ADEV\) writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
64412ae53aSAlbert ARIBAUD \(3ADEV\) udelay(10);
65412ae53aSAlbert ARIBAUD \(3ADEV\) /* set normal mode to CAS=3 */
66412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0x00000093, &emc->control);
67412ae53aSAlbert ARIBAUD \(3ADEV\) readl(EMC_DYCS0_BASE | dram->mode);
68412ae53aSAlbert ARIBAUD \(3ADEV\) /* set extended mode to all zeroes */
69412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0x00000093, &emc->control);
70412ae53aSAlbert ARIBAUD \(3ADEV\) readl(EMC_DYCS0_BASE | dram->emode);
71412ae53aSAlbert ARIBAUD \(3ADEV\) /* stop forcing clocks, keep inverted clock, issue normal mode */
72412ae53aSAlbert ARIBAUD \(3ADEV\) writel(0x00000010, &emc->control);
73412ae53aSAlbert ARIBAUD \(3ADEV\) }
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