1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2412ae53aSAlbert ARIBAUD \(3ADEV\) /*
3412ae53aSAlbert ARIBAUD \(3ADEV\)  * WORK Microwave work_92105 board support
4412ae53aSAlbert ARIBAUD \(3ADEV\)  *
5412ae53aSAlbert ARIBAUD \(3ADEV\)  * (C) Copyright 2014  DENX Software Engineering GmbH
6412ae53aSAlbert ARIBAUD \(3ADEV\)  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
7412ae53aSAlbert ARIBAUD \(3ADEV\)  */
8412ae53aSAlbert ARIBAUD \(3ADEV\) 
9412ae53aSAlbert ARIBAUD \(3ADEV\) #include <common.h>
10412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/io.h>
11412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/sys_proto.h>
12412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/cpu.h>
13412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/arch/emc.h>
14412ae53aSAlbert ARIBAUD \(3ADEV\) #include <asm/gpio.h>
15412ae53aSAlbert ARIBAUD \(3ADEV\) #include <spl.h>
16412ae53aSAlbert ARIBAUD \(3ADEV\) #include "work_92105_display.h"
17412ae53aSAlbert ARIBAUD \(3ADEV\) 
18412ae53aSAlbert ARIBAUD \(3ADEV\) struct emc_dram_settings dram_64mb = {
19412ae53aSAlbert ARIBAUD \(3ADEV\) 	.cmddelay = 0x0001C000,
20412ae53aSAlbert ARIBAUD \(3ADEV\) 	.config0 = 0x00005682,
21412ae53aSAlbert ARIBAUD \(3ADEV\) 	.rascas0 = 0x00000302,
22412ae53aSAlbert ARIBAUD \(3ADEV\) 	.rdconfig = 0x00000011,
23412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trp = 52631578,
24412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tras = 20833333,
25412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tsrex = 12500000,
26412ae53aSAlbert ARIBAUD \(3ADEV\) 	.twr = 66666666,
27412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trc = 13888888,
28412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trfc = 10256410,
29412ae53aSAlbert ARIBAUD \(3ADEV\) 	.txsr = 12500000,
30412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trrd = 1,
31412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tmrd = 1,
32412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tcdlr = 0,
33412ae53aSAlbert ARIBAUD \(3ADEV\) 	.refresh = 128000,
34412ae53aSAlbert ARIBAUD \(3ADEV\) 	.mode = 0x00018000,
35412ae53aSAlbert ARIBAUD \(3ADEV\) 	.emode = 0x02000000
36412ae53aSAlbert ARIBAUD \(3ADEV\) };
37412ae53aSAlbert ARIBAUD \(3ADEV\) 
38412ae53aSAlbert ARIBAUD \(3ADEV\) const struct emc_dram_settings dram_128mb = {
39412ae53aSAlbert ARIBAUD \(3ADEV\) 	.cmddelay = 0x0001C000,
40412ae53aSAlbert ARIBAUD \(3ADEV\) 	.config0 = 0x00005882,
41412ae53aSAlbert ARIBAUD \(3ADEV\) 	.rascas0 = 0x00000302,
42412ae53aSAlbert ARIBAUD \(3ADEV\) 	.rdconfig = 0x00000011,
43412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trp = 52631578,
44412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tras = 22222222,
45412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tsrex = 8333333,
46412ae53aSAlbert ARIBAUD \(3ADEV\) 	.twr = 66666666,
47412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trc = 14814814,
48412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trfc = 10256410,
49412ae53aSAlbert ARIBAUD \(3ADEV\) 	.txsr = 8333333,
50412ae53aSAlbert ARIBAUD \(3ADEV\) 	.trrd = 1,
51412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tmrd = 1,
52412ae53aSAlbert ARIBAUD \(3ADEV\) 	.tcdlr = 0,
53412ae53aSAlbert ARIBAUD \(3ADEV\) 	.refresh = 128000,
54412ae53aSAlbert ARIBAUD \(3ADEV\) 	.mode = 0x00030000,
55412ae53aSAlbert ARIBAUD \(3ADEV\) 	.emode = 0x02000000
56412ae53aSAlbert ARIBAUD \(3ADEV\) };
57412ae53aSAlbert ARIBAUD \(3ADEV\) 
spl_board_init(void)58412ae53aSAlbert ARIBAUD \(3ADEV\) void spl_board_init(void)
59412ae53aSAlbert ARIBAUD \(3ADEV\) {
60412ae53aSAlbert ARIBAUD \(3ADEV\) 	/* initialize serial port for console */
61412ae53aSAlbert ARIBAUD \(3ADEV\) 	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
62412ae53aSAlbert ARIBAUD \(3ADEV\) 	/* initialize console */
63412ae53aSAlbert ARIBAUD \(3ADEV\) 	preloader_console_init();
64412ae53aSAlbert ARIBAUD \(3ADEV\) 	/* init DDR and NAND to chainload U-Boot */
65412ae53aSAlbert ARIBAUD \(3ADEV\) 	ddr_init(&dram_128mb);
66412ae53aSAlbert ARIBAUD \(3ADEV\) 	/*
67412ae53aSAlbert ARIBAUD \(3ADEV\) 	 * If this is actually a 64MB module, then the highest column
68412ae53aSAlbert ARIBAUD \(3ADEV\) 	 * bit in any address will be ignored, and thus address 0x80000000
69412ae53aSAlbert ARIBAUD \(3ADEV\) 	 * should be mirrored at address 0x80000800. Test this.
70412ae53aSAlbert ARIBAUD \(3ADEV\) 	 */
71412ae53aSAlbert ARIBAUD \(3ADEV\) 	writel(0x31415926, 0x80000000); /* write Pi at 0x80000000 */
72412ae53aSAlbert ARIBAUD \(3ADEV\) 	writel(0x16180339, 0x80000800); /* write Phi at 0x80000800 */
73412ae53aSAlbert ARIBAUD \(3ADEV\) 	if (readl(0x80000000) == 0x16180339) /* check 0x80000000 */ {
74412ae53aSAlbert ARIBAUD \(3ADEV\) 		/* actually 64MB mirrored: reconfigure controller */
75412ae53aSAlbert ARIBAUD \(3ADEV\) 		ddr_init(&dram_64mb);
76412ae53aSAlbert ARIBAUD \(3ADEV\) 	}
77412ae53aSAlbert ARIBAUD \(3ADEV\) 	/* initialize NAND controller to load U-Boot from NAND */
78412ae53aSAlbert ARIBAUD \(3ADEV\) 	lpc32xx_mlc_nand_init();
79412ae53aSAlbert ARIBAUD \(3ADEV\) }
80412ae53aSAlbert ARIBAUD \(3ADEV\) 
spl_boot_device(void)81412ae53aSAlbert ARIBAUD \(3ADEV\) u32 spl_boot_device(void)
82412ae53aSAlbert ARIBAUD \(3ADEV\) {
83412ae53aSAlbert ARIBAUD \(3ADEV\) 	return BOOT_DEVICE_NAND;
84412ae53aSAlbert ARIBAUD \(3ADEV\) }
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