183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2185f7d9aSMichal Simek /*
3185f7d9aSMichal Simek * (C) Copyright 2011 Michal Simek
4185f7d9aSMichal Simek *
5185f7d9aSMichal Simek * Michal SIMEK <monstr@monstr.eu>
6185f7d9aSMichal Simek *
7185f7d9aSMichal Simek * Based on Xilinx gmac driver:
8185f7d9aSMichal Simek * (C) Copyright 2011 Xilinx
9185f7d9aSMichal Simek */
10185f7d9aSMichal Simek
11a765bdd1SSiva Durga Prasad Paladugu #include <clk.h>
12185f7d9aSMichal Simek #include <common.h>
136889ca71SMichal Simek #include <dm.h>
14185f7d9aSMichal Simek #include <net.h>
152fd2489bSMichal Simek #include <netdev.h>
16185f7d9aSMichal Simek #include <config.h>
17b8de29feSMichal Simek #include <console.h>
18185f7d9aSMichal Simek #include <malloc.h>
19185f7d9aSMichal Simek #include <asm/io.h>
20185f7d9aSMichal Simek #include <phy.h>
21185f7d9aSMichal Simek #include <miiphy.h>
22e7138b34SMateusz Kulikowski #include <wait_bit.h>
23185f7d9aSMichal Simek #include <watchdog.h>
2496f4f149SSiva Durga Prasad Paladugu #include <asm/system.h>
2501fbf310SDavid Andrey #include <asm/arch/hardware.h>
2680243528SMichal Simek #include <asm/arch/sys_proto.h>
275d97dff0SMasahiro Yamada #include <linux/errno.h>
28185f7d9aSMichal Simek
296889ca71SMichal Simek DECLARE_GLOBAL_DATA_PTR;
306889ca71SMichal Simek
31185f7d9aSMichal Simek /* Bit/mask specification */
32185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
33185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
34185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
35185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
36185f7d9aSMichal Simek #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
37185f7d9aSMichal Simek
38185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
39185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
40185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
41185f7d9aSMichal Simek
42185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
43185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
44185f7d9aSMichal Simek #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
45185f7d9aSMichal Simek
46185f7d9aSMichal Simek /* Wrap bit, last descriptor */
47185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
48185f7d9aSMichal Simek #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
4923a598f7SMichal Simek #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
50185f7d9aSMichal Simek
51185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
52185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
53185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
54185f7d9aSMichal Simek #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
55185f7d9aSMichal Simek
5627183d7cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
5727183d7cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
5827183d7cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
5927183d7cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
604eaf8f54SSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
6127183d7cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
62f17ea71dSMichal Simek #ifdef CONFIG_ARM64
6327183d7cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
64f17ea71dSMichal Simek #else
6527183d7cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
66f17ea71dSMichal Simek #endif
67185f7d9aSMichal Simek
688a584c8aSSiva Durga Prasad Paladugu #ifdef CONFIG_ARM64
698a584c8aSSiva Durga Prasad Paladugu # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
708a584c8aSSiva Durga Prasad Paladugu #else
718a584c8aSSiva Durga Prasad Paladugu # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
728a584c8aSSiva Durga Prasad Paladugu #endif
738a584c8aSSiva Durga Prasad Paladugu
748a584c8aSSiva Durga Prasad Paladugu #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
758a584c8aSSiva Durga Prasad Paladugu ZYNQ_GEM_NWCFG_FDEN | \
76185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_FSREM | \
77185f7d9aSMichal Simek ZYNQ_GEM_NWCFG_MDCCLKDIV)
78185f7d9aSMichal Simek
79185f7d9aSMichal Simek #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
80185f7d9aSMichal Simek
81185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
82185f7d9aSMichal Simek /* Use full configured addressable space (8 Kb) */
83185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
84185f7d9aSMichal Simek /* Use full configured addressable space (4 Kb) */
85185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
86185f7d9aSMichal Simek /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
87185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
88185f7d9aSMichal Simek
899a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
909a7799f4SVipul Kumar # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
919a7799f4SVipul Kumar #else
929a7799f4SVipul Kumar # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
939a7799f4SVipul Kumar #endif
949a7799f4SVipul Kumar
95185f7d9aSMichal Simek #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
96185f7d9aSMichal Simek ZYNQ_GEM_DMACR_RXSIZE | \
97185f7d9aSMichal Simek ZYNQ_GEM_DMACR_TXSIZE | \
989a7799f4SVipul Kumar ZYNQ_GEM_DMACR_RXBUF | \
999a7799f4SVipul Kumar ZYNQ_GEM_DMA_BUS_WIDTH)
100185f7d9aSMichal Simek
101e4d2318aSMichal Simek #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
102e4d2318aSMichal Simek
103845ee5f6SSiva Durga Prasad Paladugu #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
104845ee5f6SSiva Durga Prasad Paladugu
1055f68f44cSSiva Durga Prasad Paladugu #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
1065f68f44cSSiva Durga Prasad Paladugu
107f97d7e8bSMichal Simek /* Use MII register 1 (MII status register) to detect PHY */
108f97d7e8bSMichal Simek #define PHY_DETECT_REG 1
109f97d7e8bSMichal Simek
110f97d7e8bSMichal Simek /* Mask used to verify certain PHY features (or register contents)
111f97d7e8bSMichal Simek * in the register above:
112f97d7e8bSMichal Simek * 0x1000: 10Mbps full duplex support
113f97d7e8bSMichal Simek * 0x0800: 10Mbps half duplex support
114f97d7e8bSMichal Simek * 0x0008: Auto-negotiation support
115f97d7e8bSMichal Simek */
116f97d7e8bSMichal Simek #define PHY_DETECT_MASK 0x1808
117f97d7e8bSMichal Simek
118a5144237SSrikanth Thokala /* TX BD status masks */
119a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
120a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
121a5144237SSrikanth Thokala #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
122a5144237SSrikanth Thokala
12397598fcfSSoren Brinkmann /* Clock frequencies for different speeds */
12497598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_10 2500000UL
12597598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_100 25000000UL
12697598fcfSSoren Brinkmann #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
12797598fcfSSoren Brinkmann
128185f7d9aSMichal Simek /* Device registers */
129185f7d9aSMichal Simek struct zynq_gem_regs {
13097a51a03SMichal Simek u32 nwctrl; /* 0x0 - Network Control reg */
13197a51a03SMichal Simek u32 nwcfg; /* 0x4 - Network Config reg */
13297a51a03SMichal Simek u32 nwsr; /* 0x8 - Network Status reg */
133185f7d9aSMichal Simek u32 reserved1;
13497a51a03SMichal Simek u32 dmacr; /* 0x10 - DMA Control reg */
13597a51a03SMichal Simek u32 txsr; /* 0x14 - TX Status reg */
13697a51a03SMichal Simek u32 rxqbase; /* 0x18 - RX Q Base address reg */
13797a51a03SMichal Simek u32 txqbase; /* 0x1c - TX Q Base address reg */
13897a51a03SMichal Simek u32 rxsr; /* 0x20 - RX Status reg */
139185f7d9aSMichal Simek u32 reserved2[2];
14097a51a03SMichal Simek u32 idr; /* 0x2c - Interrupt Disable reg */
141185f7d9aSMichal Simek u32 reserved3;
14297a51a03SMichal Simek u32 phymntnc; /* 0x34 - Phy Maintaince reg */
143185f7d9aSMichal Simek u32 reserved4[18];
14497a51a03SMichal Simek u32 hashl; /* 0x80 - Hash Low address reg */
14597a51a03SMichal Simek u32 hashh; /* 0x84 - Hash High address reg */
146185f7d9aSMichal Simek #define LADDR_LOW 0
147185f7d9aSMichal Simek #define LADDR_HIGH 1
14897a51a03SMichal Simek u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
14997a51a03SMichal Simek u32 match[4]; /* 0xa8 - Type ID1 Match reg */
150185f7d9aSMichal Simek u32 reserved6[18];
1510ebf4041SMichal Simek #define STAT_SIZE 44
1520ebf4041SMichal Simek u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
153845ee5f6SSiva Durga Prasad Paladugu u32 reserved9[20];
154845ee5f6SSiva Durga Prasad Paladugu u32 pcscntrl;
1555f68f44cSSiva Durga Prasad Paladugu u32 rserved12[36];
1565f68f44cSSiva Durga Prasad Paladugu u32 dcfg6; /* 0x294 Design config reg6 */
1575f68f44cSSiva Durga Prasad Paladugu u32 reserved7[106];
158603ff008SEdgar E. Iglesias u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
159603ff008SEdgar E. Iglesias u32 reserved8[15];
160603ff008SEdgar E. Iglesias u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
1619a7799f4SVipul Kumar u32 reserved10[17];
1629a7799f4SVipul Kumar u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
1639a7799f4SVipul Kumar u32 reserved11[2];
1649a7799f4SVipul Kumar u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
165185f7d9aSMichal Simek };
166185f7d9aSMichal Simek
167185f7d9aSMichal Simek /* BD descriptors */
168185f7d9aSMichal Simek struct emac_bd {
169185f7d9aSMichal Simek u32 addr; /* Next descriptor pointer */
170185f7d9aSMichal Simek u32 status;
1719a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
1729a7799f4SVipul Kumar u32 addr_hi;
1739a7799f4SVipul Kumar u32 reserved;
1749a7799f4SVipul Kumar #endif
175185f7d9aSMichal Simek };
176185f7d9aSMichal Simek
177eda9d307SSiva Durga Prasad Paladugu #define RX_BUF 32
178a5144237SSrikanth Thokala /* Page table entries are set to 1MB, or multiples of 1MB
179a5144237SSrikanth Thokala * (not < 1MB). driver uses less bd's so use 1MB bdspace.
180a5144237SSrikanth Thokala */
181a5144237SSrikanth Thokala #define BD_SPACE 0x100000
182a5144237SSrikanth Thokala /* BD separation space */
183ff475878SMichal Simek #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
184185f7d9aSMichal Simek
185603ff008SEdgar E. Iglesias /* Setup the first free TX descriptor */
186603ff008SEdgar E. Iglesias #define TX_FREE_DESC 2
187603ff008SEdgar E. Iglesias
188185f7d9aSMichal Simek /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
189185f7d9aSMichal Simek struct zynq_gem_priv {
190a5144237SSrikanth Thokala struct emac_bd *tx_bd;
191a5144237SSrikanth Thokala struct emac_bd *rx_bd;
192a5144237SSrikanth Thokala char *rxbuffers;
193185f7d9aSMichal Simek u32 rxbd_current;
194185f7d9aSMichal Simek u32 rx_first_buf;
195185f7d9aSMichal Simek int phyaddr;
19605868759SMichal Simek int init;
197f2fc2768SMichal Simek struct zynq_gem_regs *iobase;
19816ce6de8SMichal Simek phy_interface_t interface;
199185f7d9aSMichal Simek struct phy_device *phydev;
20026026e69SSiva Durga Prasad Paladugu ofnode phy_of_node;
201185f7d9aSMichal Simek struct mii_dev *bus;
202a765bdd1SSiva Durga Prasad Paladugu struct clk clk;
20369065e8fSSiva Durga Prasad Paladugu u32 max_speed;
204dd12a27cSSiva Durga Prasad Paladugu bool int_pcs;
2055f68f44cSSiva Durga Prasad Paladugu bool dma_64bit;
206185f7d9aSMichal Simek };
207185f7d9aSMichal Simek
phy_setup_op(struct zynq_gem_priv * priv,u32 phy_addr,u32 regnum,u32 op,u16 * data)208b33d4a5fSMichal Simek static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
209185f7d9aSMichal Simek u32 op, u16 *data)
210185f7d9aSMichal Simek {
211185f7d9aSMichal Simek u32 mgtcr;
212f2fc2768SMichal Simek struct zynq_gem_regs *regs = priv->iobase;
213b908fcadSMichal Simek int err;
214185f7d9aSMichal Simek
21548263504SÁlvaro Fernández Rojas err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
216dea004e4SSiva Durga Prasad Paladugu true, 20000, false);
217b908fcadSMichal Simek if (err)
218b908fcadSMichal Simek return err;
219185f7d9aSMichal Simek
220185f7d9aSMichal Simek /* Construct mgtcr mask for the operation */
221185f7d9aSMichal Simek mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
222185f7d9aSMichal Simek (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
223185f7d9aSMichal Simek (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
224185f7d9aSMichal Simek
225185f7d9aSMichal Simek /* Write mgtcr and wait for completion */
226185f7d9aSMichal Simek writel(mgtcr, ®s->phymntnc);
227185f7d9aSMichal Simek
22848263504SÁlvaro Fernández Rojas err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
229dea004e4SSiva Durga Prasad Paladugu true, 20000, false);
230b908fcadSMichal Simek if (err)
231b908fcadSMichal Simek return err;
232185f7d9aSMichal Simek
233185f7d9aSMichal Simek if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
234185f7d9aSMichal Simek *data = readl(®s->phymntnc);
235185f7d9aSMichal Simek
236185f7d9aSMichal Simek return 0;
237185f7d9aSMichal Simek }
238185f7d9aSMichal Simek
phyread(struct zynq_gem_priv * priv,u32 phy_addr,u32 regnum,u16 * val)239b33d4a5fSMichal Simek static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
240f2fc2768SMichal Simek u32 regnum, u16 *val)
241185f7d9aSMichal Simek {
242b33d4a5fSMichal Simek int ret;
243198e9a4fSMichal Simek
244f2fc2768SMichal Simek ret = phy_setup_op(priv, phy_addr, regnum,
245185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
246198e9a4fSMichal Simek
247198e9a4fSMichal Simek if (!ret)
248198e9a4fSMichal Simek debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
249198e9a4fSMichal Simek phy_addr, regnum, *val);
250198e9a4fSMichal Simek
251198e9a4fSMichal Simek return ret;
252185f7d9aSMichal Simek }
253185f7d9aSMichal Simek
phywrite(struct zynq_gem_priv * priv,u32 phy_addr,u32 regnum,u16 data)254b33d4a5fSMichal Simek static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
255f2fc2768SMichal Simek u32 regnum, u16 data)
256185f7d9aSMichal Simek {
257198e9a4fSMichal Simek debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
258198e9a4fSMichal Simek regnum, data);
259198e9a4fSMichal Simek
260f2fc2768SMichal Simek return phy_setup_op(priv, phy_addr, regnum,
261185f7d9aSMichal Simek ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
262185f7d9aSMichal Simek }
263185f7d9aSMichal Simek
phy_detection(struct udevice * dev)2646889ca71SMichal Simek static int phy_detection(struct udevice *dev)
265f97d7e8bSMichal Simek {
266f97d7e8bSMichal Simek int i;
2677674b64dSMichal Simek u16 phyreg = 0;
268f97d7e8bSMichal Simek struct zynq_gem_priv *priv = dev->priv;
269f97d7e8bSMichal Simek
270f97d7e8bSMichal Simek if (priv->phyaddr != -1) {
271f2fc2768SMichal Simek phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
272f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) &&
273f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
274f97d7e8bSMichal Simek /* Found a valid PHY address */
275f97d7e8bSMichal Simek debug("Default phy address %d is valid\n",
276f97d7e8bSMichal Simek priv->phyaddr);
277b904725aSMichal Simek return 0;
278f97d7e8bSMichal Simek } else {
279f97d7e8bSMichal Simek debug("PHY address is not setup correctly %d\n",
280f97d7e8bSMichal Simek priv->phyaddr);
281f97d7e8bSMichal Simek priv->phyaddr = -1;
282f97d7e8bSMichal Simek }
283f97d7e8bSMichal Simek }
284f97d7e8bSMichal Simek
285f97d7e8bSMichal Simek debug("detecting phy address\n");
286f97d7e8bSMichal Simek if (priv->phyaddr == -1) {
287f97d7e8bSMichal Simek /* detect the PHY address */
288f97d7e8bSMichal Simek for (i = 31; i >= 0; i--) {
289f2fc2768SMichal Simek phyread(priv, i, PHY_DETECT_REG, &phyreg);
290f97d7e8bSMichal Simek if ((phyreg != 0xFFFF) &&
291f97d7e8bSMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
292f97d7e8bSMichal Simek /* Found a valid PHY address */
293f97d7e8bSMichal Simek priv->phyaddr = i;
294f97d7e8bSMichal Simek debug("Found valid phy address, %d\n", i);
295b904725aSMichal Simek return 0;
296f97d7e8bSMichal Simek }
297f97d7e8bSMichal Simek }
298f97d7e8bSMichal Simek }
299f97d7e8bSMichal Simek printf("PHY is not detected\n");
300b904725aSMichal Simek return -1;
301f97d7e8bSMichal Simek }
302f97d7e8bSMichal Simek
zynq_gem_setup_mac(struct udevice * dev)3036889ca71SMichal Simek static int zynq_gem_setup_mac(struct udevice *dev)
304185f7d9aSMichal Simek {
305185f7d9aSMichal Simek u32 i, macaddrlow, macaddrhigh;
3066889ca71SMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev);
3076889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
3086889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase;
309185f7d9aSMichal Simek
310185f7d9aSMichal Simek /* Set the MAC bits [31:0] in BOT */
3116889ca71SMichal Simek macaddrlow = pdata->enetaddr[0];
3126889ca71SMichal Simek macaddrlow |= pdata->enetaddr[1] << 8;
3136889ca71SMichal Simek macaddrlow |= pdata->enetaddr[2] << 16;
3146889ca71SMichal Simek macaddrlow |= pdata->enetaddr[3] << 24;
315185f7d9aSMichal Simek
316185f7d9aSMichal Simek /* Set MAC bits [47:32] in TOP */
3176889ca71SMichal Simek macaddrhigh = pdata->enetaddr[4];
3186889ca71SMichal Simek macaddrhigh |= pdata->enetaddr[5] << 8;
319185f7d9aSMichal Simek
320185f7d9aSMichal Simek for (i = 0; i < 4; i++) {
321185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_LOW]);
322185f7d9aSMichal Simek writel(0, ®s->laddr[i][LADDR_HIGH]);
323185f7d9aSMichal Simek /* Do not use MATCHx register */
324185f7d9aSMichal Simek writel(0, ®s->match[i]);
325185f7d9aSMichal Simek }
326185f7d9aSMichal Simek
327185f7d9aSMichal Simek writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
328185f7d9aSMichal Simek writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
329185f7d9aSMichal Simek
330185f7d9aSMichal Simek return 0;
331185f7d9aSMichal Simek }
332185f7d9aSMichal Simek
zynq_phy_init(struct udevice * dev)3336889ca71SMichal Simek static int zynq_phy_init(struct udevice *dev)
33468cc3bd8SMichal Simek {
33568cc3bd8SMichal Simek int ret;
3366889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
3376889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase;
33868cc3bd8SMichal Simek const u32 supported = SUPPORTED_10baseT_Half |
33968cc3bd8SMichal Simek SUPPORTED_10baseT_Full |
34068cc3bd8SMichal Simek SUPPORTED_100baseT_Half |
34168cc3bd8SMichal Simek SUPPORTED_100baseT_Full |
34268cc3bd8SMichal Simek SUPPORTED_1000baseT_Half |
34368cc3bd8SMichal Simek SUPPORTED_1000baseT_Full;
34468cc3bd8SMichal Simek
345c8e29271SMichal Simek /* Enable only MDIO bus */
346c8e29271SMichal Simek writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
347c8e29271SMichal Simek
348d77081cfSSiva Durga Prasad Paladugu if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
349d77081cfSSiva Durga Prasad Paladugu (priv->interface != PHY_INTERFACE_MODE_GMII)) {
35068cc3bd8SMichal Simek ret = phy_detection(dev);
35168cc3bd8SMichal Simek if (ret) {
35268cc3bd8SMichal Simek printf("GEM PHY init failed\n");
35368cc3bd8SMichal Simek return ret;
35468cc3bd8SMichal Simek }
355a06c341fSSiva Durga Prasad Paladugu }
35668cc3bd8SMichal Simek
35768cc3bd8SMichal Simek priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
35868cc3bd8SMichal Simek priv->interface);
35990c6f2e2SMichal Simek if (!priv->phydev)
36090c6f2e2SMichal Simek return -ENODEV;
36168cc3bd8SMichal Simek
3622c2ab8d6SNathan Rossi priv->phydev->supported &= supported | ADVERTISED_Pause |
36368cc3bd8SMichal Simek ADVERTISED_Asym_Pause;
36469065e8fSSiva Durga Prasad Paladugu if (priv->max_speed) {
36569065e8fSSiva Durga Prasad Paladugu ret = phy_set_supported(priv->phydev, priv->max_speed);
36669065e8fSSiva Durga Prasad Paladugu if (ret)
36769065e8fSSiva Durga Prasad Paladugu return ret;
36869065e8fSSiva Durga Prasad Paladugu }
36969065e8fSSiva Durga Prasad Paladugu
37068cc3bd8SMichal Simek priv->phydev->advertising = priv->phydev->supported;
37126026e69SSiva Durga Prasad Paladugu priv->phydev->node = priv->phy_of_node;
37220671a98SDan Murphy
3737a673f0bSMichal Simek return phy_config(priv->phydev);
37468cc3bd8SMichal Simek }
37568cc3bd8SMichal Simek
zynq_gem_init(struct udevice * dev)3766889ca71SMichal Simek static int zynq_gem_init(struct udevice *dev)
377185f7d9aSMichal Simek {
378a06c341fSSiva Durga Prasad Paladugu u32 i, nwconfig;
37955259e7cSMichal Simek int ret;
38097598fcfSSoren Brinkmann unsigned long clk_rate = 0;
3816889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
3826889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase;
383603ff008SEdgar E. Iglesias struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
384603ff008SEdgar E. Iglesias struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
385185f7d9aSMichal Simek
3865f68f44cSSiva Durga Prasad Paladugu if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
3875f68f44cSSiva Durga Prasad Paladugu priv->dma_64bit = true;
3885f68f44cSSiva Durga Prasad Paladugu else
3895f68f44cSSiva Durga Prasad Paladugu priv->dma_64bit = false;
3905f68f44cSSiva Durga Prasad Paladugu
3915f68f44cSSiva Durga Prasad Paladugu #if defined(CONFIG_PHYS_64BIT)
3925f68f44cSSiva Durga Prasad Paladugu if (!priv->dma_64bit) {
3935f68f44cSSiva Durga Prasad Paladugu printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
3945f68f44cSSiva Durga Prasad Paladugu __func__);
3955f68f44cSSiva Durga Prasad Paladugu return -EINVAL;
3965f68f44cSSiva Durga Prasad Paladugu }
3975f68f44cSSiva Durga Prasad Paladugu #else
3985f68f44cSSiva Durga Prasad Paladugu if (priv->dma_64bit)
3995f68f44cSSiva Durga Prasad Paladugu debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
4005f68f44cSSiva Durga Prasad Paladugu __func__);
4015f68f44cSSiva Durga Prasad Paladugu #endif
4025f68f44cSSiva Durga Prasad Paladugu
40305868759SMichal Simek if (!priv->init) {
404185f7d9aSMichal Simek /* Disable all interrupts */
405185f7d9aSMichal Simek writel(0xFFFFFFFF, ®s->idr);
406185f7d9aSMichal Simek
407185f7d9aSMichal Simek /* Disable the receiver & transmitter */
408185f7d9aSMichal Simek writel(0, ®s->nwctrl);
409185f7d9aSMichal Simek writel(0, ®s->txsr);
410185f7d9aSMichal Simek writel(0, ®s->rxsr);
411185f7d9aSMichal Simek writel(0, ®s->phymntnc);
412185f7d9aSMichal Simek
41305868759SMichal Simek /* Clear the Hash registers for the mac address
41405868759SMichal Simek * pointed by AddressPtr
41505868759SMichal Simek */
416185f7d9aSMichal Simek writel(0x0, ®s->hashl);
417185f7d9aSMichal Simek /* Write bits [63:32] in TOP */
418185f7d9aSMichal Simek writel(0x0, ®s->hashh);
419185f7d9aSMichal Simek
420185f7d9aSMichal Simek /* Clear all counters */
4210ebf4041SMichal Simek for (i = 0; i < STAT_SIZE; i++)
422185f7d9aSMichal Simek readl(®s->stat[i]);
423185f7d9aSMichal Simek
424185f7d9aSMichal Simek /* Setup RxBD space */
425a5144237SSrikanth Thokala memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
426185f7d9aSMichal Simek
427185f7d9aSMichal Simek for (i = 0; i < RX_BUF; i++) {
428185f7d9aSMichal Simek priv->rx_bd[i].status = 0xF0000000;
42905868759SMichal Simek priv->rx_bd[i].addr =
4309a7799f4SVipul Kumar (lower_32_bits((ulong)(priv->rxbuffers)
4319a7799f4SVipul Kumar + (i * PKTSIZE_ALIGN)));
4329a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
4339a7799f4SVipul Kumar priv->rx_bd[i].addr_hi =
4349a7799f4SVipul Kumar (upper_32_bits((ulong)(priv->rxbuffers)
4359a7799f4SVipul Kumar + (i * PKTSIZE_ALIGN)));
4369a7799f4SVipul Kumar #endif
437185f7d9aSMichal Simek }
438185f7d9aSMichal Simek /* WRAP bit to last BD */
439185f7d9aSMichal Simek priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
440185f7d9aSMichal Simek /* Write RxBDs to IP */
4419a7799f4SVipul Kumar writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase);
4429a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
4439a7799f4SVipul Kumar writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase);
4449a7799f4SVipul Kumar #endif
445185f7d9aSMichal Simek
446185f7d9aSMichal Simek /* Setup for DMA Configuration register */
447185f7d9aSMichal Simek writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
448185f7d9aSMichal Simek
449185f7d9aSMichal Simek /* Setup for Network Control register, MDIO, Rx and Tx enable */
45080243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
451185f7d9aSMichal Simek
452603ff008SEdgar E. Iglesias /* Disable the second priority queue */
453603ff008SEdgar E. Iglesias dummy_tx_bd->addr = 0;
4549a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
4559a7799f4SVipul Kumar dummy_tx_bd->addr_hi = 0;
4569a7799f4SVipul Kumar #endif
457603ff008SEdgar E. Iglesias dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
458603ff008SEdgar E. Iglesias ZYNQ_GEM_TXBUF_LAST_MASK|
459603ff008SEdgar E. Iglesias ZYNQ_GEM_TXBUF_USED_MASK;
460603ff008SEdgar E. Iglesias
461603ff008SEdgar E. Iglesias dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
462603ff008SEdgar E. Iglesias ZYNQ_GEM_RXBUF_NEW_MASK;
4639a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
4649a7799f4SVipul Kumar dummy_rx_bd->addr_hi = 0;
4659a7799f4SVipul Kumar #endif
466603ff008SEdgar E. Iglesias dummy_rx_bd->status = 0;
467603ff008SEdgar E. Iglesias
468603ff008SEdgar E. Iglesias writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
469603ff008SEdgar E. Iglesias writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
470603ff008SEdgar E. Iglesias
47105868759SMichal Simek priv->init++;
47205868759SMichal Simek }
47305868759SMichal Simek
47455259e7cSMichal Simek ret = phy_startup(priv->phydev);
47555259e7cSMichal Simek if (ret)
47655259e7cSMichal Simek return ret;
477185f7d9aSMichal Simek
47864a7ead6SMichal Simek if (!priv->phydev->link) {
47964a7ead6SMichal Simek printf("%s: No link.\n", priv->phydev->dev->name);
4804ed4aa20SMichal Simek return -1;
4814ed4aa20SMichal Simek }
4824ed4aa20SMichal Simek
483a06c341fSSiva Durga Prasad Paladugu nwconfig = ZYNQ_GEM_NWCFG_INIT;
484a06c341fSSiva Durga Prasad Paladugu
485dd12a27cSSiva Durga Prasad Paladugu /*
486dd12a27cSSiva Durga Prasad Paladugu * Set SGMII enable PCS selection only if internal PCS/PMA
487dd12a27cSSiva Durga Prasad Paladugu * core is used and interface is SGMII.
488dd12a27cSSiva Durga Prasad Paladugu */
489dd12a27cSSiva Durga Prasad Paladugu if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
490dd12a27cSSiva Durga Prasad Paladugu priv->int_pcs) {
491a06c341fSSiva Durga Prasad Paladugu nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
492a06c341fSSiva Durga Prasad Paladugu ZYNQ_GEM_NWCFG_PCS_SEL;
493845ee5f6SSiva Durga Prasad Paladugu #ifdef CONFIG_ARM64
494845ee5f6SSiva Durga Prasad Paladugu writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
495845ee5f6SSiva Durga Prasad Paladugu ®s->pcscntrl);
496845ee5f6SSiva Durga Prasad Paladugu #endif
497845ee5f6SSiva Durga Prasad Paladugu }
498a06c341fSSiva Durga Prasad Paladugu
49964a7ead6SMichal Simek switch (priv->phydev->speed) {
50080243528SMichal Simek case SPEED_1000:
501a06c341fSSiva Durga Prasad Paladugu writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
50280243528SMichal Simek ®s->nwcfg);
50397598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_1000;
50480243528SMichal Simek break;
50580243528SMichal Simek case SPEED_100:
506a06c341fSSiva Durga Prasad Paladugu writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
507242b1547SMichal Simek ®s->nwcfg);
50897598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_100;
50980243528SMichal Simek break;
51080243528SMichal Simek case SPEED_10:
51197598fcfSSoren Brinkmann clk_rate = ZYNQ_GEM_FREQUENCY_10;
51280243528SMichal Simek break;
51380243528SMichal Simek }
51401fbf310SDavid Andrey
5153dc80934SMichal Simek #if !defined(CONFIG_ARCH_VERSAL)
516a765bdd1SSiva Durga Prasad Paladugu ret = clk_set_rate(&priv->clk, clk_rate);
517eff55c55SStefan Herbrechtsmeier if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
518eff55c55SStefan Herbrechtsmeier dev_err(dev, "failed to set tx clock rate\n");
519eff55c55SStefan Herbrechtsmeier return ret;
520eff55c55SStefan Herbrechtsmeier }
521eff55c55SStefan Herbrechtsmeier
522eff55c55SStefan Herbrechtsmeier ret = clk_enable(&priv->clk);
523eff55c55SStefan Herbrechtsmeier if (ret && ret != -ENOSYS) {
524eff55c55SStefan Herbrechtsmeier dev_err(dev, "failed to enable tx clock\n");
525eff55c55SStefan Herbrechtsmeier return ret;
526eff55c55SStefan Herbrechtsmeier }
5273dc80934SMichal Simek #else
5283dc80934SMichal Simek debug("requested clk_rate %ld\n", clk_rate);
5293dc80934SMichal Simek #endif
53080243528SMichal Simek
53180243528SMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
53280243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK);
53380243528SMichal Simek
534185f7d9aSMichal Simek return 0;
535185f7d9aSMichal Simek }
536185f7d9aSMichal Simek
zynq_gem_send(struct udevice * dev,void * ptr,int len)5376889ca71SMichal Simek static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
538185f7d9aSMichal Simek {
5399a7799f4SVipul Kumar dma_addr_t addr;
5409a7799f4SVipul Kumar u32 size;
5416889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
5426889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase;
54323a598f7SMichal Simek struct emac_bd *current_bd = &priv->tx_bd[1];
544185f7d9aSMichal Simek
545185f7d9aSMichal Simek /* Setup Tx BD */
546a5144237SSrikanth Thokala memset(priv->tx_bd, 0, sizeof(struct emac_bd));
547185f7d9aSMichal Simek
5489a7799f4SVipul Kumar priv->tx_bd->addr = lower_32_bits((ulong)ptr);
5499a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
5509a7799f4SVipul Kumar priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
5519a7799f4SVipul Kumar #endif
552a5144237SSrikanth Thokala priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
55323a598f7SMichal Simek ZYNQ_GEM_TXBUF_LAST_MASK;
55423a598f7SMichal Simek /* Dummy descriptor to mark it as the last in descriptor chain */
55523a598f7SMichal Simek current_bd->addr = 0x0;
5569a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
5579a7799f4SVipul Kumar current_bd->addr_hi = 0x0;
5589a7799f4SVipul Kumar #endif
55923a598f7SMichal Simek current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
560e65d33cfSMichal Simek ZYNQ_GEM_TXBUF_LAST_MASK|
56123a598f7SMichal Simek ZYNQ_GEM_TXBUF_USED_MASK;
562a5144237SSrikanth Thokala
56345c07741SMichal Simek /* setup BD */
5649a7799f4SVipul Kumar writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase);
5659a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
5669a7799f4SVipul Kumar writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase);
5679a7799f4SVipul Kumar #endif
56845c07741SMichal Simek
5695b47d407SPrabhakar Kushwaha addr = (ulong) ptr;
570a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1);
571a5144237SSrikanth Thokala size = roundup(len, ARCH_DMA_MINALIGN);
572a5144237SSrikanth Thokala flush_dcache_range(addr, addr + size);
573a5144237SSrikanth Thokala barrier();
574185f7d9aSMichal Simek
575185f7d9aSMichal Simek /* Start transmit */
576185f7d9aSMichal Simek setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
577185f7d9aSMichal Simek
578a5144237SSrikanth Thokala /* Read TX BD status */
579a5144237SSrikanth Thokala if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
580a5144237SSrikanth Thokala printf("TX buffers exhausted in mid frame\n");
581185f7d9aSMichal Simek
58248263504SÁlvaro Fernández Rojas return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
583e7138b34SMateusz Kulikowski true, 20000, true);
584185f7d9aSMichal Simek }
585185f7d9aSMichal Simek
586185f7d9aSMichal Simek /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
zynq_gem_recv(struct udevice * dev,int flags,uchar ** packetp)5876889ca71SMichal Simek static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
588185f7d9aSMichal Simek {
589185f7d9aSMichal Simek int frame_len;
5909a7799f4SVipul Kumar dma_addr_t addr;
5916889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
592185f7d9aSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
593185f7d9aSMichal Simek
594185f7d9aSMichal Simek if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
5959d9211acSMichal Simek return -1;
596185f7d9aSMichal Simek
597185f7d9aSMichal Simek if (!(current_bd->status &
598185f7d9aSMichal Simek (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
599185f7d9aSMichal Simek printf("GEM: SOF or EOF not set for last buffer received!\n");
6009d9211acSMichal Simek return -1;
601185f7d9aSMichal Simek }
602185f7d9aSMichal Simek
603185f7d9aSMichal Simek frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
6049d9211acSMichal Simek if (!frame_len) {
6059d9211acSMichal Simek printf("%s: Zero size packet?\n", __func__);
6069d9211acSMichal Simek return -1;
6079d9211acSMichal Simek }
6089d9211acSMichal Simek
6099a7799f4SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
6109a7799f4SVipul Kumar addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
6119a7799f4SVipul Kumar | ((dma_addr_t)current_bd->addr_hi << 32));
6129a7799f4SVipul Kumar #else
6139d9211acSMichal Simek addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
6149a7799f4SVipul Kumar #endif
615a5144237SSrikanth Thokala addr &= ~(ARCH_DMA_MINALIGN - 1);
6169a7799f4SVipul Kumar
6179d9211acSMichal Simek *packetp = (uchar *)(uintptr_t)addr;
618a5144237SSrikanth Thokala
619*10598580SStefan Theil invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
620*10598580SStefan Theil barrier();
621*10598580SStefan Theil
6229d9211acSMichal Simek return frame_len;
6239d9211acSMichal Simek }
624185f7d9aSMichal Simek
zynq_gem_free_pkt(struct udevice * dev,uchar * packet,int length)6259d9211acSMichal Simek static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
6269d9211acSMichal Simek {
6279d9211acSMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
6289d9211acSMichal Simek struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
6299d9211acSMichal Simek struct emac_bd *first_bd;
6309d9211acSMichal Simek
6319d9211acSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
632185f7d9aSMichal Simek priv->rx_first_buf = priv->rxbd_current;
6339d9211acSMichal Simek } else {
634185f7d9aSMichal Simek current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
635185f7d9aSMichal Simek current_bd->status = 0xF0000000; /* FIXME */
636185f7d9aSMichal Simek }
637185f7d9aSMichal Simek
638185f7d9aSMichal Simek if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
639185f7d9aSMichal Simek first_bd = &priv->rx_bd[priv->rx_first_buf];
640185f7d9aSMichal Simek first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
641185f7d9aSMichal Simek first_bd->status = 0xF0000000;
642185f7d9aSMichal Simek }
643185f7d9aSMichal Simek
644185f7d9aSMichal Simek if ((++priv->rxbd_current) >= RX_BUF)
645185f7d9aSMichal Simek priv->rxbd_current = 0;
646185f7d9aSMichal Simek
647da872d7cSMichal Simek return 0;
648185f7d9aSMichal Simek }
649185f7d9aSMichal Simek
zynq_gem_halt(struct udevice * dev)6506889ca71SMichal Simek static void zynq_gem_halt(struct udevice *dev)
651185f7d9aSMichal Simek {
6526889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
6536889ca71SMichal Simek struct zynq_gem_regs *regs = priv->iobase;
654185f7d9aSMichal Simek
65580243528SMichal Simek clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
65680243528SMichal Simek ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
657185f7d9aSMichal Simek }
658185f7d9aSMichal Simek
zynq_board_read_rom_ethaddr(unsigned char * ethaddr)659a509a1d4SJoe Hershberger __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
660a509a1d4SJoe Hershberger {
661a509a1d4SJoe Hershberger return -ENOSYS;
662a509a1d4SJoe Hershberger }
663a509a1d4SJoe Hershberger
zynq_gem_read_rom_mac(struct udevice * dev)664a509a1d4SJoe Hershberger static int zynq_gem_read_rom_mac(struct udevice *dev)
665a509a1d4SJoe Hershberger {
666a509a1d4SJoe Hershberger struct eth_pdata *pdata = dev_get_platdata(dev);
667a509a1d4SJoe Hershberger
668b2330897SOlliver Schinagl if (!pdata)
669b2330897SOlliver Schinagl return -ENOSYS;
670a509a1d4SJoe Hershberger
671b2330897SOlliver Schinagl return zynq_board_read_rom_ethaddr(pdata->enetaddr);
672a509a1d4SJoe Hershberger }
673a509a1d4SJoe Hershberger
zynq_gem_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)6746889ca71SMichal Simek static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
6756889ca71SMichal Simek int devad, int reg)
676185f7d9aSMichal Simek {
6776889ca71SMichal Simek struct zynq_gem_priv *priv = bus->priv;
678185f7d9aSMichal Simek int ret;
679d1b226b7SMichal Simek u16 val = 0;
680185f7d9aSMichal Simek
6816889ca71SMichal Simek ret = phyread(priv, addr, reg, &val);
6826889ca71SMichal Simek debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
6836889ca71SMichal Simek return val;
684185f7d9aSMichal Simek }
685185f7d9aSMichal Simek
zynq_gem_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)6866889ca71SMichal Simek static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
6876889ca71SMichal Simek int reg, u16 value)
688185f7d9aSMichal Simek {
6896889ca71SMichal Simek struct zynq_gem_priv *priv = bus->priv;
690185f7d9aSMichal Simek
6916889ca71SMichal Simek debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
6926889ca71SMichal Simek return phywrite(priv, addr, reg, value);
693185f7d9aSMichal Simek }
694185f7d9aSMichal Simek
zynq_gem_probe(struct udevice * dev)6956889ca71SMichal Simek static int zynq_gem_probe(struct udevice *dev)
696185f7d9aSMichal Simek {
697a5144237SSrikanth Thokala void *bd_space;
6986889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
6996889ca71SMichal Simek int ret;
700185f7d9aSMichal Simek
701a5144237SSrikanth Thokala /* Align rxbuffers to ARCH_DMA_MINALIGN */
702a5144237SSrikanth Thokala priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
7035b2c9a6cSMichal Simek if (!priv->rxbuffers)
7045b2c9a6cSMichal Simek return -ENOMEM;
7055b2c9a6cSMichal Simek
706a5144237SSrikanth Thokala memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
707*10598580SStefan Theil u32 addr = (ulong)priv->rxbuffers;
708*10598580SStefan Theil flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
709*10598580SStefan Theil barrier();
710a5144237SSrikanth Thokala
71196f4f149SSiva Durga Prasad Paladugu /* Align bd_space to MMU_SECTION_SHIFT */
712a5144237SSrikanth Thokala bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
7135b2c9a6cSMichal Simek if (!bd_space)
7145b2c9a6cSMichal Simek return -ENOMEM;
7155b2c9a6cSMichal Simek
7169ce1edc8SMichal Simek mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
7179ce1edc8SMichal Simek BD_SPACE, DCACHE_OFF);
718a5144237SSrikanth Thokala
719a5144237SSrikanth Thokala /* Initialize the bd spaces for tx and rx bd's */
720a5144237SSrikanth Thokala priv->tx_bd = (struct emac_bd *)bd_space;
7215b47d407SPrabhakar Kushwaha priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
722a5144237SSrikanth Thokala
723a765bdd1SSiva Durga Prasad Paladugu ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
724a765bdd1SSiva Durga Prasad Paladugu if (ret < 0) {
725a765bdd1SSiva Durga Prasad Paladugu dev_err(dev, "failed to get clock\n");
726a765bdd1SSiva Durga Prasad Paladugu return -EINVAL;
727a765bdd1SSiva Durga Prasad Paladugu }
728a765bdd1SSiva Durga Prasad Paladugu
7296889ca71SMichal Simek priv->bus = mdio_alloc();
7306889ca71SMichal Simek priv->bus->read = zynq_gem_miiphy_read;
7316889ca71SMichal Simek priv->bus->write = zynq_gem_miiphy_write;
7326889ca71SMichal Simek priv->bus->priv = priv;
733185f7d9aSMichal Simek
7346516e3f2SMichal Simek ret = mdio_register_seq(priv->bus, dev->seq);
735c8e29271SMichal Simek if (ret)
736c8e29271SMichal Simek return ret;
737c8e29271SMichal Simek
738e76d2dcaSSiva Durga Prasad Paladugu return zynq_phy_init(dev);
739185f7d9aSMichal Simek }
7406889ca71SMichal Simek
zynq_gem_remove(struct udevice * dev)7416889ca71SMichal Simek static int zynq_gem_remove(struct udevice *dev)
7426889ca71SMichal Simek {
7436889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
7446889ca71SMichal Simek
7456889ca71SMichal Simek free(priv->phydev);
7466889ca71SMichal Simek mdio_unregister(priv->bus);
7476889ca71SMichal Simek mdio_free(priv->bus);
7486889ca71SMichal Simek
7496889ca71SMichal Simek return 0;
7506889ca71SMichal Simek }
7516889ca71SMichal Simek
7526889ca71SMichal Simek static const struct eth_ops zynq_gem_ops = {
7536889ca71SMichal Simek .start = zynq_gem_init,
7546889ca71SMichal Simek .send = zynq_gem_send,
7556889ca71SMichal Simek .recv = zynq_gem_recv,
7569d9211acSMichal Simek .free_pkt = zynq_gem_free_pkt,
7576889ca71SMichal Simek .stop = zynq_gem_halt,
7586889ca71SMichal Simek .write_hwaddr = zynq_gem_setup_mac,
759a509a1d4SJoe Hershberger .read_rom_hwaddr = zynq_gem_read_rom_mac,
7606889ca71SMichal Simek };
7616889ca71SMichal Simek
zynq_gem_ofdata_to_platdata(struct udevice * dev)7626889ca71SMichal Simek static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
7636889ca71SMichal Simek {
7646889ca71SMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev);
7656889ca71SMichal Simek struct zynq_gem_priv *priv = dev_get_priv(dev);
76626026e69SSiva Durga Prasad Paladugu struct ofnode_phandle_args phandle_args;
7673cdb1450SMichal Simek const char *phy_mode;
7686889ca71SMichal Simek
76926026e69SSiva Durga Prasad Paladugu pdata->iobase = (phys_addr_t)dev_read_addr(dev);
7706889ca71SMichal Simek priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
7716889ca71SMichal Simek /* Hardcode for now */
772bcdfef7aSMichal Simek priv->phyaddr = -1;
7736889ca71SMichal Simek
7743888c8d1SMichal Simek if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
77526026e69SSiva Durga Prasad Paladugu &phandle_args)) {
7763888c8d1SMichal Simek debug("phy-handle does exist %s\n", dev->name);
7773888c8d1SMichal Simek priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
7783888c8d1SMichal Simek "reg", -1);
7793888c8d1SMichal Simek priv->phy_of_node = phandle_args.node;
7803888c8d1SMichal Simek priv->max_speed = ofnode_read_u32_default(phandle_args.node,
7813888c8d1SMichal Simek "max-speed",
7823888c8d1SMichal Simek SPEED_1000);
78326026e69SSiva Durga Prasad Paladugu }
7846889ca71SMichal Simek
78526026e69SSiva Durga Prasad Paladugu phy_mode = dev_read_prop(dev, "phy-mode", NULL);
7863cdb1450SMichal Simek if (phy_mode)
7873cdb1450SMichal Simek pdata->phy_interface = phy_get_interface_by_name(phy_mode);
7883cdb1450SMichal Simek if (pdata->phy_interface == -1) {
7893cdb1450SMichal Simek debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
7903cdb1450SMichal Simek return -EINVAL;
7913cdb1450SMichal Simek }
7923cdb1450SMichal Simek priv->interface = pdata->phy_interface;
7933cdb1450SMichal Simek
79426026e69SSiva Durga Prasad Paladugu priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
795dd12a27cSSiva Durga Prasad Paladugu
79615a2acdfSMichal Simek printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
7973cdb1450SMichal Simek priv->phyaddr, phy_string_for_interface(priv->interface));
7986889ca71SMichal Simek
7996889ca71SMichal Simek return 0;
8006889ca71SMichal Simek }
8016889ca71SMichal Simek
8026889ca71SMichal Simek static const struct udevice_id zynq_gem_ids[] = {
8036889ca71SMichal Simek { .compatible = "cdns,zynqmp-gem" },
8046889ca71SMichal Simek { .compatible = "cdns,zynq-gem" },
8056889ca71SMichal Simek { .compatible = "cdns,gem" },
8066889ca71SMichal Simek { }
8076889ca71SMichal Simek };
8086889ca71SMichal Simek
8096889ca71SMichal Simek U_BOOT_DRIVER(zynq_gem) = {
8106889ca71SMichal Simek .name = "zynq_gem",
8116889ca71SMichal Simek .id = UCLASS_ETH,
8126889ca71SMichal Simek .of_match = zynq_gem_ids,
8136889ca71SMichal Simek .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
8146889ca71SMichal Simek .probe = zynq_gem_probe,
8156889ca71SMichal Simek .remove = zynq_gem_remove,
8166889ca71SMichal Simek .ops = &zynq_gem_ops,
8176889ca71SMichal Simek .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
8186889ca71SMichal Simek .platdata_auto_alloc_size = sizeof(struct eth_pdata),
8196889ca71SMichal Simek };
820