1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2819833afSPeter Tyser /* 3819833afSPeter Tyser * (C) Copyright 2006-2008 4819833afSPeter Tyser * Texas Instruments, <www.ti.com> 5819833afSPeter Tyser * Richard Woodruff <r-woodruff2@ti.com> 6819833afSPeter Tyser */ 7819833afSPeter Tyser 8819833afSPeter Tyser #ifndef _MEM_H_ 9819833afSPeter Tyser #define _MEM_H_ 10819833afSPeter Tyser 11819833afSPeter Tyser #define CS0 0x0 12819833afSPeter Tyser #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 13819833afSPeter Tyser 14819833afSPeter Tyser #ifndef __ASSEMBLY__ 15819833afSPeter Tyser enum { 16819833afSPeter Tyser STACKED = 0, 17819833afSPeter Tyser IP_DDR = 1, 18819833afSPeter Tyser COMBO_DDR = 2, 19819833afSPeter Tyser IP_SDR = 3, 20819833afSPeter Tyser }; 21819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 22819833afSPeter Tyser 23819833afSPeter Tyser #define EARLY_INIT 1 24819833afSPeter Tyser 2514ca3deeSTom Rini /* 2614ca3deeSTom Rini * For a full explanation of these registers and values please see 2714ca3deeSTom Rini * the Technical Reference Manual (TRM) for any of the processors in 2814ca3deeSTom Rini * this family. 2914ca3deeSTom Rini */ 3014ca3deeSTom Rini 31819833afSPeter Tyser /* Slower full frequency range default timings for x32 operation*/ 32819833afSPeter Tyser #define SDRC_SHARING 0x00000100 33819833afSPeter Tyser #define SDRC_MR_0_SDR 0x00000031 34819833afSPeter Tyser 351be1433bSTom Rini /* 361be1433bSTom Rini * SDRC autorefresh control values. This register consists of autorefresh 371be1433bSTom Rini * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The 381be1433bSTom Rini * counter is a result of ( tREFI / tCK ) - 50. 391be1433bSTom Rini */ 401be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 411be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ 421be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ 431be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ 441be1433bSTom Rini 45819833afSPeter Tyser #define DLL_OFFSET 0 46819833afSPeter Tyser #define DLL_WRITEDDRCLKX2DIS 1 47819833afSPeter Tyser #define DLL_ENADLL 1 48819833afSPeter Tyser #define DLL_LOCKDLL 0 49819833afSPeter Tyser #define DLL_DLLPHASE_72 0 50819833afSPeter Tyser #define DLL_DLLPHASE_90 1 51819833afSPeter Tyser 52819833afSPeter Tyser /* rkw - need to find of 90/72 degree recommendation for speed like before */ 53819833afSPeter Tyser #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 54819833afSPeter Tyser (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 55819833afSPeter Tyser 56e3596e35SSanjeev Premi /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ 57e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ 58e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ 59e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ 60e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ 61e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ 62e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ 63e3596e35SSanjeev Premi #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ 64e3596e35SSanjeev Premi #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ 65e3596e35SSanjeev Premi 669540c7e9SPeter Barada #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ 679540c7e9SPeter Barada ACTIM_CTRLA_TRFC(trfc) | \ 689540c7e9SPeter Barada ACTIM_CTRLA_TRC(trc) | \ 699540c7e9SPeter Barada ACTIM_CTRLA_TRAS(tras) | \ 709540c7e9SPeter Barada ACTIM_CTRLA_TRP(trp) | \ 719540c7e9SPeter Barada ACTIM_CTRLA_TRCD(trcd) | \ 729540c7e9SPeter Barada ACTIM_CTRLA_TRRD(trrd) | \ 739540c7e9SPeter Barada ACTIM_CTRLA_TDPL(tdpl) | \ 749540c7e9SPeter Barada ACTIM_CTRLA_TDAL(tdal) 75e3596e35SSanjeev Premi 76e3596e35SSanjeev Premi /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ 77e3596e35SSanjeev Premi #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ 78e3596e35SSanjeev Premi #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ 79e3596e35SSanjeev Premi #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ 80e3596e35SSanjeev Premi #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ 81e3596e35SSanjeev Premi 829540c7e9SPeter Barada #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ 839540c7e9SPeter Barada ACTIM_CTRLB_TWTR(twtr) | \ 849540c7e9SPeter Barada ACTIM_CTRLB_TCKE(tcke) | \ 859540c7e9SPeter Barada ACTIM_CTRLB_TXP(txp) | \ 869540c7e9SPeter Barada ACTIM_CTRLB_TXSR(txsr) 87e3596e35SSanjeev Premi 8814ca3deeSTom Rini /* 8914ca3deeSTom Rini * Values used in the MCFG register. Only values we use today 9014ca3deeSTom Rini * are defined and the rest can be found in the TRM. Unless otherwise 9114ca3deeSTom Rini * noted all fields are one bit. 9214ca3deeSTom Rini */ 9314ca3deeSTom Rini #define V_MCFG_RAMTYPE_DDR (0x1) 9414ca3deeSTom Rini #define V_MCFG_DEEPPD_EN (0x1 << 3) 9514ca3deeSTom Rini #define V_MCFG_B32NOT16_32 (0x1 << 4) 9614ca3deeSTom Rini #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ 979540c7e9SPeter Barada #define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */ 9814ca3deeSTom Rini #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) 999540c7e9SPeter Barada #define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */ 1009540c7e9SPeter Barada #define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10) 1019540c7e9SPeter Barada #define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */ 10214ca3deeSTom Rini 10314ca3deeSTom Rini /* Macro to construct MCFG */ 1049540c7e9SPeter Barada #define MCFG(ramsize, raswidth) \ 1059540c7e9SPeter Barada V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \ 1069540c7e9SPeter Barada V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \ 1079540c7e9SPeter Barada V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \ 1089540c7e9SPeter Barada V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR 10914ca3deeSTom Rini 110137703b8SAndreas Müller /* Hynix part of Overo (165MHz optimized) 6.06ns */ 111137703b8SAndreas Müller #define HYNIX_TDAL_165 6 112137703b8SAndreas Müller #define HYNIX_TDPL_165 3 113137703b8SAndreas Müller #define HYNIX_TRRD_165 2 114137703b8SAndreas Müller #define HYNIX_TRCD_165 3 115137703b8SAndreas Müller #define HYNIX_TRP_165 3 116137703b8SAndreas Müller #define HYNIX_TRAS_165 7 117137703b8SAndreas Müller #define HYNIX_TRC_165 10 118137703b8SAndreas Müller #define HYNIX_TRFC_165 21 119137703b8SAndreas Müller #define HYNIX_V_ACTIMA_165 \ 120137703b8SAndreas Müller ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ 121137703b8SAndreas Müller HYNIX_TRAS_165, HYNIX_TRP_165, \ 122137703b8SAndreas Müller HYNIX_TRCD_165, HYNIX_TRRD_165, \ 123137703b8SAndreas Müller HYNIX_TDPL_165, HYNIX_TDAL_165) 124137703b8SAndreas Müller 125137703b8SAndreas Müller #define HYNIX_TWTR_165 1 126137703b8SAndreas Müller #define HYNIX_TCKE_165 1 127137703b8SAndreas Müller #define HYNIX_TXP_165 2 128137703b8SAndreas Müller #define HYNIX_XSR_165 24 129137703b8SAndreas Müller #define HYNIX_V_ACTIMB_165 \ 130137703b8SAndreas Müller ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ 131137703b8SAndreas Müller HYNIX_TXP_165, HYNIX_XSR_165) 132137703b8SAndreas Müller 1339540c7e9SPeter Barada #define HYNIX_RASWIDTH_165 13 134137703b8SAndreas Müller #define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) 135137703b8SAndreas Müller 136673283f3STom Rini /* Hynix part of AM/DM37xEVM (200MHz optimized) */ 137673283f3STom Rini #define HYNIX_TDAL_200 6 138673283f3STom Rini #define HYNIX_TDPL_200 3 139673283f3STom Rini #define HYNIX_TRRD_200 2 140673283f3STom Rini #define HYNIX_TRCD_200 4 141673283f3STom Rini #define HYNIX_TRP_200 3 142673283f3STom Rini #define HYNIX_TRAS_200 8 143673283f3STom Rini #define HYNIX_TRC_200 11 144673283f3STom Rini #define HYNIX_TRFC_200 18 145673283f3STom Rini #define HYNIX_V_ACTIMA_200 \ 146673283f3STom Rini ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ 147673283f3STom Rini HYNIX_TRAS_200, HYNIX_TRP_200, \ 148673283f3STom Rini HYNIX_TRCD_200, HYNIX_TRRD_200, \ 149673283f3STom Rini HYNIX_TDPL_200, HYNIX_TDAL_200) 150673283f3STom Rini 151673283f3STom Rini #define HYNIX_TWTR_200 2 152673283f3STom Rini #define HYNIX_TCKE_200 1 153673283f3STom Rini #define HYNIX_TXP_200 1 154673283f3STom Rini #define HYNIX_XSR_200 28 155673283f3STom Rini #define HYNIX_V_ACTIMB_200 \ 156673283f3STom Rini ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ 157673283f3STom Rini HYNIX_TXP_200, HYNIX_XSR_200) 158673283f3STom Rini 1599540c7e9SPeter Barada #define HYNIX_RASWIDTH_200 14 160673283f3STom Rini #define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) 161673283f3STom Rini 1622c5b8756SSanjeev Premi /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ 1632c5b8756SSanjeev Premi #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 1642c5b8756SSanjeev Premi /* 15/6 + 18/6 = 5.5 -> 6 */ 1652c5b8756SSanjeev Premi #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 1662c5b8756SSanjeev Premi #define INFINEON_TRRD_165 2 /* 12/6 = 2 */ 1672c5b8756SSanjeev Premi #define INFINEON_TRCD_165 3 /* 18/6 = 3 */ 1682c5b8756SSanjeev Premi #define INFINEON_TRP_165 3 /* 18/6 = 3 */ 1692c5b8756SSanjeev Premi #define INFINEON_TRAS_165 7 /* 42/6 = 7 */ 1702c5b8756SSanjeev Premi #define INFINEON_TRC_165 10 /* 60/6 = 10 */ 1712c5b8756SSanjeev Premi #define INFINEON_TRFC_165 12 /* 72/6 = 12 */ 172e3596e35SSanjeev Premi 173e3596e35SSanjeev Premi #define INFINEON_V_ACTIMA_165 \ 174e3596e35SSanjeev Premi ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ 175e3596e35SSanjeev Premi INFINEON_TRAS_165, INFINEON_TRP_165, \ 176e3596e35SSanjeev Premi INFINEON_TRCD_165, INFINEON_TRRD_165, \ 177e3596e35SSanjeev Premi INFINEON_TDPL_165, INFINEON_TDAL_165) 178819833afSPeter Tyser 179819833afSPeter Tyser #define INFINEON_TWTR_165 1 180819833afSPeter Tyser #define INFINEON_TCKE_165 2 181819833afSPeter Tyser #define INFINEON_TXP_165 2 1822c5b8756SSanjeev Premi #define INFINEON_XSR_165 20 /* 120/6 = 20 */ 183e3596e35SSanjeev Premi 184e3596e35SSanjeev Premi #define INFINEON_V_ACTIMB_165 \ 185e3596e35SSanjeev Premi ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ 186e3596e35SSanjeev Premi INFINEON_TXP_165, INFINEON_XSR_165) 187819833afSPeter Tyser 1882c5b8756SSanjeev Premi /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ 1892c5b8756SSanjeev Premi #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 1902c5b8756SSanjeev Premi /* 15/6 + 18/6 = 5.5 -> 6 */ 1912c5b8756SSanjeev Premi #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 1922c5b8756SSanjeev Premi #define MICRON_TRRD_165 2 /* 12/6 = 2 */ 1932c5b8756SSanjeev Premi #define MICRON_TRCD_165 3 /* 18/6 = 3 */ 1942c5b8756SSanjeev Premi #define MICRON_TRP_165 3 /* 18/6 = 3 */ 1952c5b8756SSanjeev Premi #define MICRON_TRAS_165 7 /* 42/6 = 7 */ 1962c5b8756SSanjeev Premi #define MICRON_TRC_165 10 /* 60/6 = 10 */ 1972c5b8756SSanjeev Premi #define MICRON_TRFC_165 21 /* 125/6 = 21 */ 198e3596e35SSanjeev Premi 199e3596e35SSanjeev Premi #define MICRON_V_ACTIMA_165 \ 200e3596e35SSanjeev Premi ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ 201e3596e35SSanjeev Premi MICRON_TRAS_165, MICRON_TRP_165, \ 202e3596e35SSanjeev Premi MICRON_TRCD_165, MICRON_TRRD_165, \ 203e3596e35SSanjeev Premi MICRON_TDPL_165, MICRON_TDAL_165) 204819833afSPeter Tyser 205819833afSPeter Tyser #define MICRON_TWTR_165 1 206819833afSPeter Tyser #define MICRON_TCKE_165 1 2072c5b8756SSanjeev Premi #define MICRON_XSR_165 23 /* 138/6 = 23 */ 2082c5b8756SSanjeev Premi #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ 209e3596e35SSanjeev Premi 210e3596e35SSanjeev Premi #define MICRON_V_ACTIMB_165 \ 211e3596e35SSanjeev Premi ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ 212e3596e35SSanjeev Premi MICRON_TXP_165, MICRON_XSR_165) 213819833afSPeter Tyser 2149540c7e9SPeter Barada #define MICRON_RASWIDTH_165 13 215fc41ba1eSTom Rini #define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) 216b88e4256SSimon Schwarz 217fc41ba1eSTom Rini #define MICRON_BL_165 0x2 218fc41ba1eSTom Rini #define MICRON_SIL_165 0x0 219fc41ba1eSTom Rini #define MICRON_CASL_165 0x3 220fc41ba1eSTom Rini #define MICRON_WBST_165 0x0 221fc41ba1eSTom Rini #define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ 222fc41ba1eSTom Rini (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ 223fc41ba1eSTom Rini (MICRON_BL_165)) 224b88e4256SSimon Schwarz 22575c57a35STom Rini /* Micron part (200MHz optimized) 5 ns */ 22675c57a35STom Rini #define MICRON_TDAL_200 6 22775c57a35STom Rini #define MICRON_TDPL_200 3 22875c57a35STom Rini #define MICRON_TRRD_200 2 22975c57a35STom Rini #define MICRON_TRCD_200 3 23075c57a35STom Rini #define MICRON_TRP_200 3 23175c57a35STom Rini #define MICRON_TRAS_200 8 23275c57a35STom Rini #define MICRON_TRC_200 11 23375c57a35STom Rini #define MICRON_TRFC_200 15 23475c57a35STom Rini #define MICRON_V_ACTIMA_200 \ 23575c57a35STom Rini ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ 23675c57a35STom Rini MICRON_TRAS_200, MICRON_TRP_200, \ 23775c57a35STom Rini MICRON_TRCD_200, MICRON_TRRD_200, \ 23875c57a35STom Rini MICRON_TDPL_200, MICRON_TDAL_200) 23975c57a35STom Rini 24075c57a35STom Rini #define MICRON_TWTR_200 2 24175c57a35STom Rini #define MICRON_TCKE_200 4 24275c57a35STom Rini #define MICRON_TXP_200 2 24375c57a35STom Rini #define MICRON_XSR_200 23 24475c57a35STom Rini #define MICRON_V_ACTIMB_200 \ 24575c57a35STom Rini ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ 24675c57a35STom Rini MICRON_TXP_200, MICRON_XSR_200) 24775c57a35STom Rini 2489540c7e9SPeter Barada #define MICRON_RASWIDTH_200 14 24975c57a35STom Rini #define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) 25075c57a35STom Rini 251d215b3e5SAlbert ARIBAUD \(3ADEV\) /* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */ 252d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TDAL_165 5 253d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TDPL_165 2 254d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TRRD_165 2 255d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TRCD_165 3 256d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TRP_165 3 257d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TRAS_165 7 258d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TRC_165 10 259d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TRFC_165 12 260d215b3e5SAlbert ARIBAUD \(3ADEV\) 261d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_V_ACTIMA_165 \ 262d215b3e5SAlbert ARIBAUD \(3ADEV\) ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \ 263d215b3e5SAlbert ARIBAUD \(3ADEV\) SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \ 264d215b3e5SAlbert ARIBAUD \(3ADEV\) SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \ 265d215b3e5SAlbert ARIBAUD \(3ADEV\) SAMSUNG_TDPL_165, SAMSUNG_TDAL_165) 266d215b3e5SAlbert ARIBAUD \(3ADEV\) 267d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TWTR_165 1 268d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TCKE_165 2 269d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_XSR_165 20 270d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_TXP_165 5 271d215b3e5SAlbert ARIBAUD \(3ADEV\) 272d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_V_ACTIMB_165 \ 273d215b3e5SAlbert ARIBAUD \(3ADEV\) ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \ 274d215b3e5SAlbert ARIBAUD \(3ADEV\) SAMSUNG_TXP_165, SAMSUNG_XSR_165) 275d215b3e5SAlbert ARIBAUD \(3ADEV\) 276d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_RASWIDTH_165 14 277d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_V_MCFG_165(size) \ 278d215b3e5SAlbert ARIBAUD \(3ADEV\) V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \ 279d215b3e5SAlbert ARIBAUD \(3ADEV\) V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \ 280d215b3e5SAlbert ARIBAUD \(3ADEV\) V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR 281d215b3e5SAlbert ARIBAUD \(3ADEV\) 282d215b3e5SAlbert ARIBAUD \(3ADEV\) /* TODO: find which register these were taken from */ 283d215b3e5SAlbert ARIBAUD \(3ADEV\) 284d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_BL_165 0x2 285d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_SIL_165 0x0 286d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_CASL_165 0x3 287d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_WBST_165 0x0 288d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \ 289d215b3e5SAlbert ARIBAUD \(3ADEV\) (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \ 290d215b3e5SAlbert ARIBAUD \(3ADEV\) (SAMSUNG_BL_165)) 291d215b3e5SAlbert ARIBAUD \(3ADEV\) 292d215b3e5SAlbert ARIBAUD \(3ADEV\) #define SAMSUNG_SHARING 0x00003700 293d215b3e5SAlbert ARIBAUD \(3ADEV\) 2942c5b8756SSanjeev Premi /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ 2952c5b8756SSanjeev Premi #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ 2962c5b8756SSanjeev Premi /* 15/6 + 18/6 = 5.5 -> 6 */ 2972c5b8756SSanjeev Premi #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 2982c5b8756SSanjeev Premi #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ 2992c5b8756SSanjeev Premi #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ 3002c5b8756SSanjeev Premi #define NUMONYX_TRP_165 3 /* 18/6 = 3 */ 3012c5b8756SSanjeev Premi #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ 3022c5b8756SSanjeev Premi #define NUMONYX_TRC_165 10 /* 60/6 = 10 */ 3032c5b8756SSanjeev Premi #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ 304e3596e35SSanjeev Premi 305e3596e35SSanjeev Premi #define NUMONYX_V_ACTIMA_165 \ 306e3596e35SSanjeev Premi ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ 307e3596e35SSanjeev Premi NUMONYX_TRAS_165, NUMONYX_TRP_165, \ 308e3596e35SSanjeev Premi NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ 309e3596e35SSanjeev Premi NUMONYX_TDPL_165, NUMONYX_TDAL_165) 31084b66310SEnric Balletbo i Serra 31184b66310SEnric Balletbo i Serra #define NUMONYX_TWTR_165 2 31284b66310SEnric Balletbo i Serra #define NUMONYX_TCKE_165 2 3132c5b8756SSanjeev Premi #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ 3142c5b8756SSanjeev Premi #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ 315e3596e35SSanjeev Premi 316e3596e35SSanjeev Premi #define NUMONYX_V_ACTIMB_165 \ 317e3596e35SSanjeev Premi ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ 318e3596e35SSanjeev Premi NUMONYX_TXP_165, NUMONYX_XSR_165) 31984b66310SEnric Balletbo i Serra 3209540c7e9SPeter Barada #define NUMONYX_RASWIDTH_165 15 32175c57a35STom Rini #define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) 32275c57a35STom Rini 32341708a5dSJavier Martinez Canillas /* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */ 32441708a5dSJavier Martinez Canillas #define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */ 32541708a5dSJavier Martinez Canillas /* 15/5 + 15/5 = 3 + 3 -> 6 */ 32641708a5dSJavier Martinez Canillas #define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */ 32741708a5dSJavier Martinez Canillas #define NUMONYX_TRRD_200 2 /* 10/5 = 2 */ 32841708a5dSJavier Martinez Canillas #define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */ 32941708a5dSJavier Martinez Canillas #define NUMONYX_TRP_200 3 /* 15/5 = 3 */ 33041708a5dSJavier Martinez Canillas #define NUMONYX_TRAS_200 8 /* 40/5 = 8 */ 33141708a5dSJavier Martinez Canillas #define NUMONYX_TRC_200 11 /* 55/5 = 11 */ 33241708a5dSJavier Martinez Canillas #define NUMONYX_TRFC_200 28 /* 140/5 = 28 */ 33341708a5dSJavier Martinez Canillas 33441708a5dSJavier Martinez Canillas #define NUMONYX_V_ACTIMA_200 \ 33541708a5dSJavier Martinez Canillas ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \ 33641708a5dSJavier Martinez Canillas NUMONYX_TRAS_200, NUMONYX_TRP_200, \ 33741708a5dSJavier Martinez Canillas NUMONYX_TRCD_200, NUMONYX_TRRD_200, \ 33841708a5dSJavier Martinez Canillas NUMONYX_TDPL_200, NUMONYX_TDAL_200) 33941708a5dSJavier Martinez Canillas 34041708a5dSJavier Martinez Canillas #define NUMONYX_TWTR_200 2 34141708a5dSJavier Martinez Canillas #define NUMONYX_TCKE_200 2 34241708a5dSJavier Martinez Canillas #define NUMONYX_TXP_200 3 34341708a5dSJavier Martinez Canillas #define NUMONYX_XSR_200 40 34441708a5dSJavier Martinez Canillas 34541708a5dSJavier Martinez Canillas #define NUMONYX_V_ACTIMB_200 \ 34641708a5dSJavier Martinez Canillas ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \ 34741708a5dSJavier Martinez Canillas NUMONYX_TXP_200, NUMONYX_XSR_200) 34841708a5dSJavier Martinez Canillas 34941708a5dSJavier Martinez Canillas #define NUMONYX_RASWIDTH_200 15 35041708a5dSJavier Martinez Canillas #define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200) 35141708a5dSJavier Martinez Canillas 352819833afSPeter Tyser /* 353819833afSPeter Tyser * GPMC settings - 354819833afSPeter Tyser * Definitions is as per the following format 355819833afSPeter Tyser * #define <PART>_GPMC_CONFIG<x> <value> 356819833afSPeter Tyser * Where: 357819833afSPeter Tyser * PART is the part name e.g. STNOR - Intel Strata Flash 358819833afSPeter Tyser * x is GPMC config registers from 1 to 6 (there will be 6 macros) 359819833afSPeter Tyser * Value is corresponding value 360819833afSPeter Tyser * 361819833afSPeter Tyser * For every valid PRCM configuration there should be only one definition of 362819833afSPeter Tyser * the same. if values are independent of the board, this definition will be 363819833afSPeter Tyser * present in this file if values are dependent on the board, then this should 364819833afSPeter Tyser * go into corresponding mem-boardName.h file 365819833afSPeter Tyser * 366819833afSPeter Tyser * Currently valid part Names are (PART): 367819833afSPeter Tyser * STNOR - Intel Strata Flash 368819833afSPeter Tyser * SMNAND - Samsung NAND 369819833afSPeter Tyser * MPDB - H4 MPDB board 370819833afSPeter Tyser * SBNOR - Sibley NOR 371819833afSPeter Tyser * MNAND - Micron Large page x16 NAND 372819833afSPeter Tyser * ONNAND - Samsung One NAND 373819833afSPeter Tyser * 374819833afSPeter Tyser * include/configs/file.h contains the defn - for all CS we are interested 375819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx PART 376819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_SIZE Size 377819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_MAP Map 378819833afSPeter Tyser * Where: 379819833afSPeter Tyser * x - CS number 380819833afSPeter Tyser * PART - Part Name as defined above 381819833afSPeter Tyser * SIZE - how big is the mapping to be 382819833afSPeter Tyser * GPMC_SIZE_128M - 0x8 383819833afSPeter Tyser * GPMC_SIZE_64M - 0xC 384819833afSPeter Tyser * GPMC_SIZE_32M - 0xE 385819833afSPeter Tyser * GPMC_SIZE_16M - 0xF 386819833afSPeter Tyser * MAP - Map this CS to which address(GPMC address space)- Absolute address 387819833afSPeter Tyser * >>24 before being used. 388819833afSPeter Tyser */ 389a0a37183Spekon gupta #define GPMC_SIZE_256M 0x0 390819833afSPeter Tyser #define GPMC_SIZE_128M 0x8 391819833afSPeter Tyser #define GPMC_SIZE_64M 0xC 392819833afSPeter Tyser #define GPMC_SIZE_32M 0xE 393819833afSPeter Tyser #define GPMC_SIZE_16M 0xF 394819833afSPeter Tyser 395b7eb9e78STom Rini #define GPMC_BASEADDR_MASK 0x3F 396b7eb9e78STom Rini 397b7eb9e78STom Rini #define GPMC_CS_ENABLE 0x1 398b7eb9e78STom Rini 399819833afSPeter Tyser #define M_NAND_GPMC_CONFIG1 0x00001800 400819833afSPeter Tyser #define M_NAND_GPMC_CONFIG2 0x00141400 401819833afSPeter Tyser #define M_NAND_GPMC_CONFIG3 0x00141400 402819833afSPeter Tyser #define M_NAND_GPMC_CONFIG4 0x0F010F01 403819833afSPeter Tyser #define M_NAND_GPMC_CONFIG5 0x010C1414 404819833afSPeter Tyser #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 405819833afSPeter Tyser #define M_NAND_GPMC_CONFIG7 0x00000C44 406819833afSPeter Tyser 407819833afSPeter Tyser #define STNOR_GPMC_CONFIG1 0x3 408819833afSPeter Tyser #define STNOR_GPMC_CONFIG2 0x00151501 409819833afSPeter Tyser #define STNOR_GPMC_CONFIG3 0x00060602 410819833afSPeter Tyser #define STNOR_GPMC_CONFIG4 0x11091109 411819833afSPeter Tyser #define STNOR_GPMC_CONFIG5 0x01141F1F 412819833afSPeter Tyser #define STNOR_GPMC_CONFIG6 0x000004c4 413819833afSPeter Tyser 414819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG1 0x1200 415819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG2 0x001f1f00 416819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG3 0x00080802 417819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG4 0x1C091C09 418819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG5 0x01131F1F 419819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 420819833afSPeter Tyser 421819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 422819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 423819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 424819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 425819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 426819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 427819833afSPeter Tyser 428819833afSPeter Tyser #define MPDB_GPMC_CONFIG1 0x00011000 429819833afSPeter Tyser #define MPDB_GPMC_CONFIG2 0x001f1f01 430819833afSPeter Tyser #define MPDB_GPMC_CONFIG3 0x00080803 431819833afSPeter Tyser #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 432819833afSPeter Tyser #define MPDB_GPMC_CONFIG5 0x041f1F1F 433819833afSPeter Tyser #define MPDB_GPMC_CONFIG6 0x1F0F04C4 434819833afSPeter Tyser 435819833afSPeter Tyser #define P2_GPMC_CONFIG1 0x0 436819833afSPeter Tyser #define P2_GPMC_CONFIG2 0x0 437819833afSPeter Tyser #define P2_GPMC_CONFIG3 0x0 438819833afSPeter Tyser #define P2_GPMC_CONFIG4 0x0 439819833afSPeter Tyser #define P2_GPMC_CONFIG5 0x0 440819833afSPeter Tyser #define P2_GPMC_CONFIG6 0x0 441819833afSPeter Tyser 442819833afSPeter Tyser #define ONENAND_GPMC_CONFIG1 0x00001200 443819833afSPeter Tyser #define ONENAND_GPMC_CONFIG2 0x000F0F01 444819833afSPeter Tyser #define ONENAND_GPMC_CONFIG3 0x00030301 445819833afSPeter Tyser #define ONENAND_GPMC_CONFIG4 0x0F040F04 446819833afSPeter Tyser #define ONENAND_GPMC_CONFIG5 0x010F1010 447819833afSPeter Tyser #define ONENAND_GPMC_CONFIG6 0x1F060000 448819833afSPeter Tyser 449819833afSPeter Tyser #define NET_GPMC_CONFIG1 0x00001000 450819833afSPeter Tyser #define NET_GPMC_CONFIG2 0x001e1e01 451819833afSPeter Tyser #define NET_GPMC_CONFIG3 0x00080300 452819833afSPeter Tyser #define NET_GPMC_CONFIG4 0x1c091c09 453819833afSPeter Tyser #define NET_GPMC_CONFIG5 0x04181f1f 454819833afSPeter Tyser #define NET_GPMC_CONFIG6 0x00000FCF 455819833afSPeter Tyser #define NET_GPMC_CONFIG7 0x00000f6c 456819833afSPeter Tyser 45750899183Spekon gupta /* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ 45850899183Spekon gupta #define NET_LAN9221_GPMC_CONFIG1 0x00001000 45950899183Spekon gupta #define NET_LAN9221_GPMC_CONFIG2 0x00060700 46050899183Spekon gupta #define NET_LAN9221_GPMC_CONFIG3 0x00020201 46150899183Spekon gupta #define NET_LAN9221_GPMC_CONFIG4 0x06000700 46250899183Spekon gupta #define NET_LAN9221_GPMC_CONFIG5 0x0006090A 46350899183Spekon gupta #define NET_LAN9221_GPMC_CONFIG6 0x87030000 46450899183Spekon gupta #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c 46550899183Spekon gupta 46650899183Spekon gupta 467819833afSPeter Tyser /* max number of GPMC Chip Selects */ 468819833afSPeter Tyser #define GPMC_MAX_CS 8 469819833afSPeter Tyser /* max number of GPMC regs */ 470819833afSPeter Tyser #define GPMC_MAX_REG 7 471819833afSPeter Tyser 472819833afSPeter Tyser #define DBG_MPDB 6 473819833afSPeter Tyser #define DBG_MPDB_BASE DEBUG_BASE 474819833afSPeter Tyser 475cae377b5SVaibhav Hiremath #ifndef __ASSEMBLY__ 476cae377b5SVaibhav Hiremath 477cae377b5SVaibhav Hiremath /* Function prototypes */ 478cae377b5SVaibhav Hiremath void mem_init(void); 479cae377b5SVaibhav Hiremath 480cae377b5SVaibhav Hiremath u32 is_mem_sdr(void); 481cae377b5SVaibhav Hiremath u32 mem_ok(u32 cs); 482cae377b5SVaibhav Hiremath 483cae377b5SVaibhav Hiremath u32 get_sdr_cs_size(u32); 484cae377b5SVaibhav Hiremath u32 get_sdr_cs_offset(u32); 485cae377b5SVaibhav Hiremath 486cae377b5SVaibhav Hiremath #endif /* __ASSEMBLY__ */ 487cae377b5SVaibhav Hiremath 488819833afSPeter Tyser #endif /* endif _MEM_H_ */ 489