1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2983e3700STom Rini /*
3983e3700STom Rini * EMIF programming
4983e3700STom Rini *
5983e3700STom Rini * (C) Copyright 2010
6983e3700STom Rini * Texas Instruments, <www.ti.com>
7983e3700STom Rini *
8983e3700STom Rini * Aneesh V <aneesh@ti.com> for OMAP4
9983e3700STom Rini */
10983e3700STom Rini
11983e3700STom Rini #include <common.h>
12983e3700STom Rini #include <asm/emif.h>
13983e3700STom Rini #include <asm/arch/sys_proto.h>
14983e3700STom Rini #include <asm/utils.h>
15983e3700STom Rini
16983e3700STom Rini #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
17983e3700STom Rini #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
18983e3700STom Rini static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
19983e3700STom Rini static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
20983e3700STom Rini #endif
21983e3700STom Rini
22983e3700STom Rini #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
23983e3700STom Rini /* Base AC Timing values specified by JESD209-2 for 532MHz operation */
24983e3700STom Rini static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
25983e3700STom Rini .max_freq = 532000000,
26983e3700STom Rini .RL = 8,
27983e3700STom Rini .tRPab = 21,
28983e3700STom Rini .tRCD = 18,
29983e3700STom Rini .tWR = 15,
30983e3700STom Rini .tRASmin = 42,
31983e3700STom Rini .tRRD = 10,
32983e3700STom Rini .tWTRx2 = 15,
33983e3700STom Rini .tXSR = 140,
34983e3700STom Rini .tXPx2 = 15,
35983e3700STom Rini .tRFCab = 130,
36983e3700STom Rini .tRTPx2 = 15,
37983e3700STom Rini .tCKE = 3,
38983e3700STom Rini .tCKESR = 15,
39983e3700STom Rini .tZQCS = 90,
40983e3700STom Rini .tZQCL = 360,
41983e3700STom Rini .tZQINIT = 1000,
42983e3700STom Rini .tDQSCKMAXx2 = 11,
43983e3700STom Rini .tRASmax = 70,
44983e3700STom Rini .tFAW = 50
45983e3700STom Rini };
46983e3700STom Rini
47983e3700STom Rini /*
48983e3700STom Rini * Min tCK values specified by JESD209-2
49983e3700STom Rini * Min tCK specifies the minimum duration of some AC timing parameters in terms
50983e3700STom Rini * of the number of cycles. If the calculated number of cycles based on the
51983e3700STom Rini * absolute time value is less than the min tCK value, min tCK value should
52983e3700STom Rini * be used instead. This typically happens at low frequencies.
53983e3700STom Rini */
54983e3700STom Rini static const struct lpddr2_min_tck min_tck_jedec = {
55983e3700STom Rini .tRL = 3,
56983e3700STom Rini .tRP_AB = 3,
57983e3700STom Rini .tRCD = 3,
58983e3700STom Rini .tWR = 3,
59983e3700STom Rini .tRAS_MIN = 3,
60983e3700STom Rini .tRRD = 2,
61983e3700STom Rini .tWTR = 2,
62983e3700STom Rini .tXP = 2,
63983e3700STom Rini .tRTP = 2,
64983e3700STom Rini .tCKE = 3,
65983e3700STom Rini .tCKESR = 3,
66983e3700STom Rini .tFAW = 8
67983e3700STom Rini };
68983e3700STom Rini
69983e3700STom Rini static const struct lpddr2_ac_timings const*
70983e3700STom Rini jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
71983e3700STom Rini &timings_jedec_532_mhz
72983e3700STom Rini };
73983e3700STom Rini
74983e3700STom Rini static const struct lpddr2_device_timings jedec_default_timings = {
75983e3700STom Rini .ac_timings = jedec_ac_timings,
76983e3700STom Rini .min_tck = &min_tck_jedec
77983e3700STom Rini };
78983e3700STom Rini
emif_get_device_timings(u32 emif_nr,const struct lpddr2_device_timings ** cs0_device_timings,const struct lpddr2_device_timings ** cs1_device_timings)79983e3700STom Rini void emif_get_device_timings(u32 emif_nr,
80983e3700STom Rini const struct lpddr2_device_timings **cs0_device_timings,
81983e3700STom Rini const struct lpddr2_device_timings **cs1_device_timings)
82983e3700STom Rini {
83983e3700STom Rini /* Assume Identical devices on EMIF1 & EMIF2 */
84983e3700STom Rini *cs0_device_timings = &jedec_default_timings;
85983e3700STom Rini *cs1_device_timings = NULL;
86983e3700STom Rini }
87983e3700STom Rini #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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