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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Darm-smc-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm-smc-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: watchdog.yaml#
13 - Julius Werner <jwerner@chromium.org>
18 - arm,smc-wdt
20 arm,smc-id:
23 The ATF smc function id used by the firmware.
27 - compatible
[all …]
/openbmc/u-boot/arch/powerpc/dts/
H A Dmcr3000.dts6 * SPDX-License-Identifier: GPL-2.0+
9 /dts-v1/;
12 WDT: watchdog@0 { label
13 compatible = "fsl,pq1-wdt";
15 SERIAL: smc@0 {
16 compatible = "fsl,pq1-smc";
20 stdout-path = &SERIAL;
/openbmc/linux/drivers/watchdog/
H A Dkeembay_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
8 #include <linux/arm-smccc.h>
20 /* Non-secure watchdog register offsets */
59 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset) in keembay_wdt_readl() argument
61 return readl(wdt->base + offset); in keembay_wdt_readl()
64 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val) in keembay_wdt_writel() argument
66 writel(WDT_UNLOCK, wdt->base + TIM_SAFE); in keembay_wdt_writel()
67 writel(val, wdt->base + offset); in keembay_wdt_writel()
72 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); in keembay_wdt_set_timeout_reg() local
[all …]
H A Darm_smc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/arm-smccc.h>
45 if (res->a0 == PSCI_RET_NOT_SUPPORTED) in smcwd_call()
46 return -ENODEV; in smcwd_call()
47 if (res->a0 == PSCI_RET_INVALID_PARAMS) in smcwd_call()
48 return -EINVAL; in smcwd_call()
49 if (res->a0 != PSCI_RET_SUCCESS) in smcwd_call()
50 return -EIO; in smcwd_call()
75 wdd->timeout = timeout; in smcwd_set_timeout()
118 wdd = devm_kzalloc(&pdev->dev, sizeof(*wdd), GFP_KERNEL); in smcwd_probe()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/
H A Dspl.c1 // SPDX-License-Identifier: GPL-2.0+
17 struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; in at91_disable_wdt() local
19 writel(AT91_WDT_MR_WDDIS, &wdt->mr); in at91_disable_wdt()
67 printf("ERROR: SMC/TWI/QSPI boot device not supported!\n" in spl_boot_device()
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
16 - OCM 256KB
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm11351.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012-2013 Broadcom Corporation
4 #include <dt-bindings/clock/bcm281xx.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
30 gic: interrupt-controller@2561000 {
31 compatible = "arm,gic-400", "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/synaptics/
H A Dberlin4ct.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "arm,psci-1.0", "arm,psci-0.2";
22 method = "smc";
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a53";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
H A Darmada-37xx.dtsi6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/comphy/comphy_data.h>
49 #include <dt-bindings/gpio/gpio.h>
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
63 #address-cells = <1>;
64 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm6858.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
[all …]
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
H A Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9261.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 #include <dt-bindings/pinctrl/at91.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Dat91sam9rl.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/clock/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include <dt-bindings/mfd/at91-usart.h>
17 #address-cells = <1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dipq5332.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-h3.c22 #include "qemu/error-report.h"
25 #include "hw/qdev-core.h"
27 #include "hw/char/serial-mm.h"
29 #include "hw/usb/hcd-ehci.h"
32 #include "hw/arm/allwinner-h3.h"
33 #include "target/arm/cpu-qom.h"
82 { "d-engine", 0x01000000, 4 * MiB },
83 { "d-inter", 0x01400000, 128 * KiB },
96 { "usb0-otg", 0x01c19000, 4 * KiB },
97 { "usb0-phy", 0x01c1a000, 4 * KiB },
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
20 method = "smc";
[all …]

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