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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41 |
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| #
ef89fd56 |
| 24-Jul-2023 |
Haibo Chen <haibo.chen@nxp.com> |
arm64: dts: imx8ulp: add flexspi node
Add flexspi node, flexspi has a special memory region mapped to
0x60000000~0x6fffffff. This region is for AHB usage. So add this region
to SoC ranges.
Signed-o
arm64: dts: imx8ulp: add flexspi node
Add flexspi node, flexspi has a special memory region mapped to
0x60000000~0x6fffffff. This region is for AHB usage. So add this region
to SoC ranges.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
db2c35aa |
| 24-Jul-2023 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add cpuidle node
Add cpuidle node and enable cpuidle for dual cores. The HW mode in
Arm Trusted Firmware is SoC Application Power Domain Sleep mode.
Signed-off-by: Jacky Bai <p
arm64: dts: imx8ulp: add cpuidle node
Add cpuidle node and enable cpuidle for dual cores. The HW mode in
Arm Trusted Firmware is SoC Application Power Domain Sleep mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
a9624b4e |
| 24-Jul-2023 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add thermal node
Add thermal node. Cooling map is not added, because frequency runtime
changing not supported for now.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by:
arm64: dts: imx8ulp: add thermal node
Add thermal node. Cooling map is not added, because frequency runtime
changing not supported for now.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
97803407 |
| 24-Jul-2023 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: set default clock for SDHC
Set default clock rate and parents for SDHC[0,1,2].
The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz
as USDHC clock parent. Becau
arm64: dts: imx8ulp: set default clock for SDHC
Set default clock rate and parents for SDHC[0,1,2].
The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz
as USDHC clock parent. Because PLL3 PFD0 is used for NIC, PFD1 is used
for audio, the only choice is PFD3 which can reach to 400Mhz.
USDHC1 and USDHC2 maximum PCC clock rate is 200Mhz in Over Drive mode,
and 100Mhz in Nominal/Low Drive mode, when PTE or PTF is used.
The patch adjusts clock parent to PLL3 PFD3 DIV1 for USDHC0, PLL3
PFD3 DIV2 for USDHC1 and USDHC2. And set the max rate to meet
restrictions.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
5b9435d6 |
| 24-Jul-2023 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add cm33 node
Add i.MX8ULP CM33 node.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3 |
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| #
d2bd9471 |
| 21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: imx: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
imx8dxl-evk.dtb: l2-cache0: 'cache-unified
arm64: dts: imx: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
imx8dxl-evk.dtb: l2-cache0: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
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| #
3b450831 |
| 07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: dts: Update cache properties for freescale
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and S
arm64: dts: Update cache properties for freescale
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chester Lin <clin@suse.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64 |
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| #
0acd1b1c |
| 31-Aug-2022 |
Clark Wang <xiaoning.wang@nxp.com> |
arm64: dts: imx8ulp: increase the clock speed of LPSPI
LPSPI transfer max speed is half of the root clock.
Increase the root clock speed to support faster data transmission.
And update the parent c
arm64: dts: imx8ulp: increase the clock speed of LPSPI
LPSPI transfer max speed is half of the root clock.
Increase the root clock speed to support faster data transmission.
And update the parent clock of all i2c/spi with IMX8ULP_CLK_FROSC_DIV2
which could produce accurate clock for i2c/spi usage.
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
d2209e65 |
| 31-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add mailbox node
Add Sentinel Message Unit(MU), Generic MU nodes.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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| #
ed4b58fa |
| 31-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add pmu node
Add i.MX8ULP pmu node
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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| #
b2ca6369 |
| 31-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: correct the scmi sram node name
Follow sram/sram.yaml to update the sram node name.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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| #
7e2c9e51 |
| 31-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: drop undocumented property in cgc
The clocks and clocks-names are not documented in binding doc,
and the clk-imx8ulp driver not use the undocumented property,
so drop them.
Sig
arm64: dts: imx8ulp: drop undocumented property in cgc
The clocks and clocks-names are not documented in binding doc,
and the clk-imx8ulp driver not use the undocumented property,
so drop them.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58 |
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| #
683d7ffb |
| 26-Jul-2022 |
Wei Fang <wei.fang@nxp.com> |
arm64: dts: imx8ulp: Add the fec support
Add the fec support on i.MX8ULP platforms.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sha
arm64: dts: imx8ulp: Add the fec support
Add the fec support on i.MX8ULP platforms.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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| #
5fa383a2 |
| 31-Aug-2022 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add #reset-cells for pcc
The binding file clock/imx8ulp-pcc-clock.yaml indicates '#reset-cells'
is a required property, add it.
Fixes: fe6291e96313 ("arm64: dts: imx8ulp: Add t
arm64: dts: imx8ulp: add #reset-cells for pcc
The binding file clock/imx8ulp-pcc-clock.yaml indicates '#reset-cells'
is a required property, add it.
Fixes: fe6291e96313 ("arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48 |
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| #
fcdef92b |
| 14-Jun-2022 |
Fabio Estevam <festevam@gmail.com> |
arm64: dts: imx8m: Pass a label to the soc node
Pass a label to the 'soc' node to make it easier to reference
it from other devicetree files.
U-Boot, for example usually needs to access the AIPS no
arm64: dts: imx8m: Pass a label to the soc node
Pass a label to the 'soc' node to make it easier to reference
it from other devicetree files.
U-Boot, for example usually needs to access the AIPS node to
pass U-Boot-specific properties.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.47, v5.15.46, v5.15.45, v5.15.44 |
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| #
33597c62 |
| 26-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: fsl: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DT
arm64: dts: fsl: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39 |
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| #
0a078845 |
| 10-May-2022 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: address build warning
Fix warnings such as:
Warning (simple_bus_reg): /soc@0/gpio@2e200000: simple-bus unit address
format error, expected "2e200080"
Signed-off-by: Peng Fan
arm64: dts: imx8ulp: address build warning
Fix warnings such as:
Warning (simple_bus_reg): /soc@0/gpio@2e200000: simple-bus unit address
format error, expected "2e200080"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24 |
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| #
45d941f6 |
| 11-Feb-2022 |
Sudeep Holla <sudeep.holla@arm.com> |
arm64: dts: imx8ulp: Set #thermal-sensor-cells to 1 as required
The SCMI binding clearly states the value of #thermal-sensor-cells must
be 1. However arch/arm64/boot/dts/freescale/imx8ulp.dtsi sets
arm64: dts: imx8ulp: Set #thermal-sensor-cells to 1 as required
The SCMI binding clearly states the value of #thermal-sensor-cells must
be 1. However arch/arm64/boot/dts/freescale/imx8ulp.dtsi sets it 0 which
results in the following warning with dtbs_check:
| arch/arm64/boot/dts/freescale/imx8ulp-evk.dt.yaml: scmi:
| protocol@15:#thermal-sensor-cells:0:0: 1 was expected
| From schema: Documentation/devicetree/bindings/firmware/arm,scmi.yaml
Fix it by setting it to 1 as required.
Cc:Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Fixes: a38771d7a49b ("arm64: dts: imx8ulp: add scmi firmware node")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8 |
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| #
03eb813d |
| 08-Dec-2021 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add power domain entry for usdhc
Add power domain for USDHC node.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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| #
a38771d7 |
| 08-Dec-2021 |
Peng Fan <peng.fan@nxp.com> |
arm64: dts: imx8ulp: add scmi firmware node
i.MX8ULP use scmi firmware based power domain and sensor support.
So add the firmware node and the sram it uses.
Signed-off-by: Peng Fan <peng.fan@nxp.co
arm64: dts: imx8ulp: add scmi firmware node
i.MX8ULP use scmi firmware based power domain and sensor support.
So add the firmware node and the sram it uses.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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Revision tags: v5.15.7, v5.15.6 |
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| #
fe6291e9 |
| 26-Nov-2021 |
Jacky Bai <ping.bai@nxp.com> |
arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
Add the basic dtsi support for i.MX8ULP.
i.MX 8ULP is part of the ULP family with emphasis on extreme
low-power techniques using the 28 nm f
arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
Add the basic dtsi support for i.MX8ULP.
i.MX 8ULP is part of the ULP family with emphasis on extreme
low-power techniques using the 28 nm fully depleted silicon on
insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
based on asymmetric architecture, however will add a third DSP
domain for advanced voice/audio capability and a Graphics domain
where it is possible to access graphics resources from the
application side or the realtime side.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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