17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27a5d7347SHarninder Rai/* 37a5d7347SHarninder Rai * Device Tree Include file for NXP Layerscape-1088A family SoC. 47a5d7347SHarninder Rai * 5f7d48ffcSWasim Khan * Copyright 2017-2020 NXP 67a5d7347SHarninder Rai * 77a5d7347SHarninder Rai * Harninder Rai <harninder.rai@nxp.com> 87a5d7347SHarninder Rai * 97a5d7347SHarninder Rai */ 10f9799323SMichael Walle#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 117a5d7347SHarninder Rai#include <dt-bindings/interrupt-controller/arm-gic.h> 12e4990b44SYuantian Tang#include <dt-bindings/thermal/thermal.h> 137a5d7347SHarninder Rai 147a5d7347SHarninder Rai/ { 157a5d7347SHarninder Rai compatible = "fsl,ls1088a"; 167a5d7347SHarninder Rai interrupt-parent = <&gic>; 177a5d7347SHarninder Rai #address-cells = <2>; 187a5d7347SHarninder Rai #size-cells = <2>; 197a5d7347SHarninder Rai 201e09dec9SHoria Geantă aliases { 211e09dec9SHoria Geantă crypto = &crypto; 22f4fe3a86SBiwen Li rtc1 = &ftm_alarm0; 231e09dec9SHoria Geantă }; 241e09dec9SHoria Geantă 257a5d7347SHarninder Rai cpus { 267a5d7347SHarninder Rai #address-cells = <1>; 277a5d7347SHarninder Rai #size-cells = <0>; 287a5d7347SHarninder Rai 297a5d7347SHarninder Rai /* We have 2 clusters having 4 Cortex-A53 cores each */ 307a5d7347SHarninder Rai cpu0: cpu@0 { 317a5d7347SHarninder Rai device_type = "cpu"; 327a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 337a5d7347SHarninder Rai reg = <0x0>; 34f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 355334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 36e4990b44SYuantian Tang #cooling-cells = <2>; 377a5d7347SHarninder Rai }; 387a5d7347SHarninder Rai 397a5d7347SHarninder Rai cpu1: cpu@1 { 407a5d7347SHarninder Rai device_type = "cpu"; 417a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 427a5d7347SHarninder Rai reg = <0x1>; 43f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 445334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 45346f5976SViresh Kumar #cooling-cells = <2>; 467a5d7347SHarninder Rai }; 477a5d7347SHarninder Rai 487a5d7347SHarninder Rai cpu2: cpu@2 { 497a5d7347SHarninder Rai device_type = "cpu"; 507a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 517a5d7347SHarninder Rai reg = <0x2>; 52f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 535334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 54346f5976SViresh Kumar #cooling-cells = <2>; 557a5d7347SHarninder Rai }; 567a5d7347SHarninder Rai 577a5d7347SHarninder Rai cpu3: cpu@3 { 587a5d7347SHarninder Rai device_type = "cpu"; 597a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 607a5d7347SHarninder Rai reg = <0x3>; 61f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 625334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 63346f5976SViresh Kumar #cooling-cells = <2>; 647a5d7347SHarninder Rai }; 657a5d7347SHarninder Rai 667a5d7347SHarninder Rai cpu4: cpu@100 { 677a5d7347SHarninder Rai device_type = "cpu"; 687a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 697a5d7347SHarninder Rai reg = <0x100>; 70f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 715334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 72e4990b44SYuantian Tang #cooling-cells = <2>; 737a5d7347SHarninder Rai }; 747a5d7347SHarninder Rai 757a5d7347SHarninder Rai cpu5: cpu@101 { 767a5d7347SHarninder Rai device_type = "cpu"; 777a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 787a5d7347SHarninder Rai reg = <0x101>; 79f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 805334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 81346f5976SViresh Kumar #cooling-cells = <2>; 827a5d7347SHarninder Rai }; 837a5d7347SHarninder Rai 847a5d7347SHarninder Rai cpu6: cpu@102 { 857a5d7347SHarninder Rai device_type = "cpu"; 867a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 877a5d7347SHarninder Rai reg = <0x102>; 88f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 895334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 90346f5976SViresh Kumar #cooling-cells = <2>; 917a5d7347SHarninder Rai }; 927a5d7347SHarninder Rai 937a5d7347SHarninder Rai cpu7: cpu@103 { 947a5d7347SHarninder Rai device_type = "cpu"; 957a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 967a5d7347SHarninder Rai reg = <0x103>; 97f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 985334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 99346f5976SViresh Kumar #cooling-cells = <2>; 1005334e1a2SYuantian Tang }; 1015334e1a2SYuantian Tang 1025334e1a2SYuantian Tang CPU_PH20: cpu-ph20 { 1035334e1a2SYuantian Tang compatible = "arm,idle-state"; 1045334e1a2SYuantian Tang idle-state-name = "PH20"; 10569ea29b0SYuantian Tang arm,psci-suspend-param = <0x0>; 1065334e1a2SYuantian Tang entry-latency-us = <1000>; 1075334e1a2SYuantian Tang exit-latency-us = <1000>; 1085334e1a2SYuantian Tang min-residency-us = <3000>; 1097a5d7347SHarninder Rai }; 1107a5d7347SHarninder Rai }; 1117a5d7347SHarninder Rai 1127a5d7347SHarninder Rai gic: interrupt-controller@6000000 { 1137a5d7347SHarninder Rai compatible = "arm,gic-v3"; 1147a5d7347SHarninder Rai #interrupt-cells = <3>; 1157a5d7347SHarninder Rai interrupt-controller; 1167a5d7347SHarninder Rai reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1177a5d7347SHarninder Rai <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 1187a5d7347SHarninder Rai <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 1197a5d7347SHarninder Rai <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 1207a5d7347SHarninder Rai <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 1217a5d7347SHarninder Rai interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 122a3bbf4c5SHou Zhiqiang #address-cells = <2>; 123a3bbf4c5SHou Zhiqiang #size-cells = <2>; 124a3bbf4c5SHou Zhiqiang ranges; 125a3bbf4c5SHou Zhiqiang 126*04b09f6eSRob Herring its: msi-controller@6020000 { 127a3bbf4c5SHou Zhiqiang compatible = "arm,gic-v3-its"; 128a3bbf4c5SHou Zhiqiang msi-controller; 129a3bbf4c5SHou Zhiqiang reg = <0x0 0x6020000 0 0x20000>; 130a3bbf4c5SHou Zhiqiang }; 1317a5d7347SHarninder Rai }; 1327a5d7347SHarninder Rai 13385530a7aSFabio Estevam thermal-zones { 134acfa13abSYuantian Tang core-cluster { 13585530a7aSFabio Estevam polling-delay-passive = <1000>; 13685530a7aSFabio Estevam polling-delay = <5000>; 13785530a7aSFabio Estevam thermal-sensors = <&tmu 0>; 13885530a7aSFabio Estevam 13985530a7aSFabio Estevam trips { 140acfa13abSYuantian Tang core_cluster_alert: core-cluster-alert { 14185530a7aSFabio Estevam temperature = <85000>; 14285530a7aSFabio Estevam hysteresis = <2000>; 14385530a7aSFabio Estevam type = "passive"; 14485530a7aSFabio Estevam }; 14585530a7aSFabio Estevam 146acfa13abSYuantian Tang core-cluster-crit { 14785530a7aSFabio Estevam temperature = <95000>; 14885530a7aSFabio Estevam hysteresis = <2000>; 14985530a7aSFabio Estevam type = "critical"; 15085530a7aSFabio Estevam }; 15185530a7aSFabio Estevam }; 15285530a7aSFabio Estevam 15385530a7aSFabio Estevam cooling-maps { 15485530a7aSFabio Estevam map0 { 155acfa13abSYuantian Tang trip = <&core_cluster_alert>; 15685530a7aSFabio Estevam cooling-device = 157c9a1f243SViresh Kumar <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158c9a1f243SViresh Kumar <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159c9a1f243SViresh Kumar <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160c9a1f243SViresh Kumar <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161c9a1f243SViresh Kumar <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162c9a1f243SViresh Kumar <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163c9a1f243SViresh Kumar <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 164c9a1f243SViresh Kumar <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 16585530a7aSFabio Estevam }; 16685530a7aSFabio Estevam }; 16785530a7aSFabio Estevam }; 168acfa13abSYuantian Tang 169acfa13abSYuantian Tang soc { 170acfa13abSYuantian Tang polling-delay-passive = <1000>; 171acfa13abSYuantian Tang polling-delay = <5000>; 172acfa13abSYuantian Tang thermal-sensors = <&tmu 1>; 173acfa13abSYuantian Tang 174acfa13abSYuantian Tang trips { 175acfa13abSYuantian Tang soc-crit { 176acfa13abSYuantian Tang temperature = <95000>; 177acfa13abSYuantian Tang hysteresis = <2000>; 178acfa13abSYuantian Tang type = "critical"; 179acfa13abSYuantian Tang }; 180acfa13abSYuantian Tang }; 181acfa13abSYuantian Tang }; 18285530a7aSFabio Estevam }; 18385530a7aSFabio Estevam 1847a5d7347SHarninder Rai timer { 1857a5d7347SHarninder Rai compatible = "arm,armv8-timer"; 1867a5d7347SHarninder Rai interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 1877a5d7347SHarninder Rai <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 1887a5d7347SHarninder Rai <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 1897a5d7347SHarninder Rai <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 1907a5d7347SHarninder Rai }; 1917a5d7347SHarninder Rai 1922cfad132SMathew McBride pmu { 1932cfad132SMathew McBride compatible = "arm,cortex-a53-pmu"; 1942cfad132SMathew McBride interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 1952cfad132SMathew McBride }; 1962cfad132SMathew McBride 1975334e1a2SYuantian Tang psci { 1985334e1a2SYuantian Tang compatible = "arm,psci-0.2"; 1995334e1a2SYuantian Tang method = "smc"; 2005334e1a2SYuantian Tang }; 2015334e1a2SYuantian Tang 2027a5d7347SHarninder Rai sysclk: sysclk { 2037a5d7347SHarninder Rai compatible = "fixed-clock"; 2047a5d7347SHarninder Rai #clock-cells = <0>; 2057a5d7347SHarninder Rai clock-frequency = <100000000>; 2067a5d7347SHarninder Rai clock-output-names = "sysclk"; 2077a5d7347SHarninder Rai }; 2087a5d7347SHarninder Rai 20922e9e261SLi Yang reboot { 21022e9e261SLi Yang compatible = "syscon-reboot"; 21122e9e261SLi Yang regmap = <&reset>; 21222e9e261SLi Yang offset = <0x0>; 21322e9e261SLi Yang mask = <0x02>; 21422e9e261SLi Yang }; 21522e9e261SLi Yang 2167a5d7347SHarninder Rai soc { 2177a5d7347SHarninder Rai compatible = "simple-bus"; 2187a5d7347SHarninder Rai #address-cells = <2>; 2197a5d7347SHarninder Rai #size-cells = <2>; 2207a5d7347SHarninder Rai ranges; 221d9a71ef0SIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 2227a5d7347SHarninder Rai 2237a5d7347SHarninder Rai clockgen: clocking@1300000 { 2247a5d7347SHarninder Rai compatible = "fsl,ls1088a-clockgen"; 2257a5d7347SHarninder Rai reg = <0 0x1300000 0 0xa0000>; 2267a5d7347SHarninder Rai #clock-cells = <2>; 2277a5d7347SHarninder Rai clocks = <&sysclk>; 2287a5d7347SHarninder Rai }; 2297a5d7347SHarninder Rai 23088b64bb1SAshish Kumar dcfg: dcfg@1e00000 { 23188b64bb1SAshish Kumar compatible = "fsl,ls1088a-dcfg", "syscon"; 23288b64bb1SAshish Kumar reg = <0x0 0x1e00000 0x0 0x10000>; 23388b64bb1SAshish Kumar little-endian; 23488b64bb1SAshish Kumar }; 23588b64bb1SAshish Kumar 23622e9e261SLi Yang reset: syscon@1e60000 { 23722e9e261SLi Yang compatible = "fsl,ls1088a-reset", "syscon"; 23822e9e261SLi Yang reg = <0x0 0x1e60000 0x0 0x10000>; 23922e9e261SLi Yang }; 24022e9e261SLi Yang 2410e88b5fdSBiwen Li isc: syscon@1f70000 { 2420e88b5fdSBiwen Li compatible = "fsl,ls1088a-isc", "syscon"; 2430e88b5fdSBiwen Li reg = <0x0 0x1f70000 0x0 0x10000>; 2440e88b5fdSBiwen Li little-endian; 2450e88b5fdSBiwen Li #address-cells = <1>; 2460e88b5fdSBiwen Li #size-cells = <1>; 2470e88b5fdSBiwen Li ranges = <0x0 0x0 0x1f70000 0x10000>; 2480e88b5fdSBiwen Li 2490e88b5fdSBiwen Li extirq: interrupt-controller@14 { 2500e88b5fdSBiwen Li compatible = "fsl,ls1088a-extirq"; 2510e88b5fdSBiwen Li #interrupt-cells = <2>; 2520e88b5fdSBiwen Li #address-cells = <0>; 2530e88b5fdSBiwen Li interrupt-controller; 2540e88b5fdSBiwen Li reg = <0x14 4>; 2550e88b5fdSBiwen Li interrupt-map = 2561447c635SVladimir Oltean <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2571447c635SVladimir Oltean <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2581447c635SVladimir Oltean <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2591447c635SVladimir Oltean <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2601447c635SVladimir Oltean <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2611447c635SVladimir Oltean <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2621447c635SVladimir Oltean <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2631447c635SVladimir Oltean <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2641447c635SVladimir Oltean <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2651447c635SVladimir Oltean <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2661447c635SVladimir Oltean <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2671447c635SVladimir Oltean <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 268339c8beaSMichael Walle interrupt-map-mask = <0xf 0x0>; 2690e88b5fdSBiwen Li }; 2700e88b5fdSBiwen Li }; 2710e88b5fdSBiwen Li 272e0f6d9ebSSean Anderson sfp: efuse@1e80000 { 273e0f6d9ebSSean Anderson compatible = "fsl,ls1028a-sfp"; 274e0f6d9ebSSean Anderson reg = <0x0 0x1e80000 0x0 0x10000>; 275e0f6d9ebSSean Anderson clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 276e0f6d9ebSSean Anderson QORIQ_CLK_PLL_DIV(4)>; 277e0f6d9ebSSean Anderson clock-names = "sfp"; 278e0f6d9ebSSean Anderson }; 279e0f6d9ebSSean Anderson 280e4990b44SYuantian Tang tmu: tmu@1f80000 { 281e4990b44SYuantian Tang compatible = "fsl,qoriq-tmu"; 282e4990b44SYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 283e4990b44SYuantian Tang interrupts = <0 23 0x4>; 284acfa13abSYuantian Tang fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 285e4990b44SYuantian Tang fsl,tmu-calibration = 286e4990b44SYuantian Tang /* Calibration data group 1 */ 287acfa13abSYuantian Tang <0x00000000 0x00000023 288acfa13abSYuantian Tang 0x00000001 0x0000002a 289acfa13abSYuantian Tang 0x00000002 0x00000030 290acfa13abSYuantian Tang 0x00000003 0x00000037 291acfa13abSYuantian Tang 0x00000004 0x0000003d 292acfa13abSYuantian Tang 0x00000005 0x00000044 293acfa13abSYuantian Tang 0x00000006 0x0000004a 294acfa13abSYuantian Tang 0x00000007 0x00000051 295acfa13abSYuantian Tang 0x00000008 0x00000057 296acfa13abSYuantian Tang 0x00000009 0x0000005e 297acfa13abSYuantian Tang 0x0000000a 0x00000064 298acfa13abSYuantian Tang 0x0000000b 0x0000006b 299e4990b44SYuantian Tang /* Calibration data group 2 */ 300acfa13abSYuantian Tang 0x00010000 0x00000022 301acfa13abSYuantian Tang 0x00010001 0x0000002a 302acfa13abSYuantian Tang 0x00010002 0x00000032 303acfa13abSYuantian Tang 0x00010003 0x0000003a 304acfa13abSYuantian Tang 0x00010004 0x00000042 305acfa13abSYuantian Tang 0x00010005 0x0000004a 306acfa13abSYuantian Tang 0x00010006 0x00000052 307acfa13abSYuantian Tang 0x00010007 0x0000005a 308acfa13abSYuantian Tang 0x00010008 0x00000062 309acfa13abSYuantian Tang 0x00010009 0x0000006a 310e4990b44SYuantian Tang /* Calibration data group 3 */ 311acfa13abSYuantian Tang 0x00020000 0x00000021 312acfa13abSYuantian Tang 0x00020001 0x0000002b 313acfa13abSYuantian Tang 0x00020002 0x00000035 314acfa13abSYuantian Tang 0x00020003 0x00000040 315acfa13abSYuantian Tang 0x00020004 0x0000004a 316acfa13abSYuantian Tang 0x00020005 0x00000054 317acfa13abSYuantian Tang 0x00020006 0x0000005e 318e4990b44SYuantian Tang /* Calibration data group 4 */ 319acfa13abSYuantian Tang 0x00030000 0x00000010 320acfa13abSYuantian Tang 0x00030001 0x0000001c 321acfa13abSYuantian Tang 0x00030002 0x00000027 322acfa13abSYuantian Tang 0x00030003 0x00000032 323acfa13abSYuantian Tang 0x00030004 0x0000003e 324acfa13abSYuantian Tang 0x00030005 0x00000049 325acfa13abSYuantian Tang 0x00030006 0x00000054 326acfa13abSYuantian Tang 0x00030007 0x00000060>; 327e4990b44SYuantian Tang little-endian; 328e4990b44SYuantian Tang #thermal-sensor-cells = <1>; 329e4990b44SYuantian Tang }; 330e4990b44SYuantian Tang 33160ca9248SChuanhua Han dspi: spi@2100000 { 33260ca9248SChuanhua Han compatible = "fsl,ls1088a-dspi", 33360ca9248SChuanhua Han "fsl,ls1021a-v1.0-dspi"; 33460ca9248SChuanhua Han #address-cells = <1>; 33560ca9248SChuanhua Han #size-cells = <0>; 33660ca9248SChuanhua Han reg = <0x0 0x2100000 0x0 0x10000>; 33760ca9248SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 33860ca9248SChuanhua Han clock-names = "dspi"; 339f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 340f9799323SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 34160ca9248SChuanhua Han spi-num-chipselects = <6>; 34260ca9248SChuanhua Han status = "disabled"; 34360ca9248SChuanhua Han }; 34460ca9248SChuanhua Han 3457a5d7347SHarninder Rai duart0: serial@21c0500 { 3467a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 3477a5d7347SHarninder Rai reg = <0x0 0x21c0500 0x0 0x100>; 348f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 349f9799323SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3507a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 3517a5d7347SHarninder Rai status = "disabled"; 3527a5d7347SHarninder Rai }; 3537a5d7347SHarninder Rai 3547a5d7347SHarninder Rai duart1: serial@21c0600 { 3557a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 3567a5d7347SHarninder Rai reg = <0x0 0x21c0600 0x0 0x100>; 357f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 358f9799323SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3597a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 3607a5d7347SHarninder Rai status = "disabled"; 3617a5d7347SHarninder Rai }; 3627a5d7347SHarninder Rai 3637a5d7347SHarninder Rai gpio0: gpio@2300000 { 364afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3657a5d7347SHarninder Rai reg = <0x0 0x2300000 0x0 0x10000>; 3667a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 36766f1f580SChuanhua Han little-endian; 3687a5d7347SHarninder Rai gpio-controller; 3697a5d7347SHarninder Rai #gpio-cells = <2>; 3707a5d7347SHarninder Rai interrupt-controller; 3717a5d7347SHarninder Rai #interrupt-cells = <2>; 3727a5d7347SHarninder Rai }; 3737a5d7347SHarninder Rai 3747a5d7347SHarninder Rai gpio1: gpio@2310000 { 375afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3767a5d7347SHarninder Rai reg = <0x0 0x2310000 0x0 0x10000>; 3777a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 37866f1f580SChuanhua Han little-endian; 3797a5d7347SHarninder Rai gpio-controller; 3807a5d7347SHarninder Rai #gpio-cells = <2>; 3817a5d7347SHarninder Rai interrupt-controller; 3827a5d7347SHarninder Rai #interrupt-cells = <2>; 3837a5d7347SHarninder Rai }; 3847a5d7347SHarninder Rai 3857a5d7347SHarninder Rai gpio2: gpio@2320000 { 386afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3877a5d7347SHarninder Rai reg = <0x0 0x2320000 0x0 0x10000>; 3887a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 38966f1f580SChuanhua Han little-endian; 3907a5d7347SHarninder Rai gpio-controller; 3917a5d7347SHarninder Rai #gpio-cells = <2>; 3927a5d7347SHarninder Rai interrupt-controller; 3937a5d7347SHarninder Rai #interrupt-cells = <2>; 3947a5d7347SHarninder Rai }; 3957a5d7347SHarninder Rai 3967a5d7347SHarninder Rai gpio3: gpio@2330000 { 397afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3987a5d7347SHarninder Rai reg = <0x0 0x2330000 0x0 0x10000>; 3997a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 40066f1f580SChuanhua Han little-endian; 4017a5d7347SHarninder Rai gpio-controller; 4027a5d7347SHarninder Rai #gpio-cells = <2>; 4037a5d7347SHarninder Rai interrupt-controller; 4047a5d7347SHarninder Rai #interrupt-cells = <2>; 4057a5d7347SHarninder Rai }; 4067a5d7347SHarninder Rai 407e55264f3SLi Yang ifc: memory-controller@2240000 { 408fefbc002SLi Yang compatible = "fsl,ifc"; 4097a5d7347SHarninder Rai reg = <0x0 0x2240000 0x0 0x20000>; 4107a5d7347SHarninder Rai interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 4117a5d7347SHarninder Rai little-endian; 4127a5d7347SHarninder Rai #address-cells = <2>; 4137a5d7347SHarninder Rai #size-cells = <1>; 4147a5d7347SHarninder Rai status = "disabled"; 4157a5d7347SHarninder Rai }; 4167a5d7347SHarninder Rai 4177a5d7347SHarninder Rai i2c0: i2c@2000000 { 4187a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 4197a5d7347SHarninder Rai #address-cells = <1>; 4207a5d7347SHarninder Rai #size-cells = <0>; 4217a5d7347SHarninder Rai reg = <0x0 0x2000000 0x0 0x10000>; 4227a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 423f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 424f9799323SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 4257a5d7347SHarninder Rai status = "disabled"; 4267a5d7347SHarninder Rai }; 4277a5d7347SHarninder Rai 4287a5d7347SHarninder Rai i2c1: i2c@2010000 { 4297a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 4307a5d7347SHarninder Rai #address-cells = <1>; 4317a5d7347SHarninder Rai #size-cells = <0>; 4327a5d7347SHarninder Rai reg = <0x0 0x2010000 0x0 0x10000>; 4337a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 434f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 435f9799323SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 4367a5d7347SHarninder Rai status = "disabled"; 4377a5d7347SHarninder Rai }; 4387a5d7347SHarninder Rai 4397a5d7347SHarninder Rai i2c2: i2c@2020000 { 4407a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 4417a5d7347SHarninder Rai #address-cells = <1>; 4427a5d7347SHarninder Rai #size-cells = <0>; 4437a5d7347SHarninder Rai reg = <0x0 0x2020000 0x0 0x10000>; 4447a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 445f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 446f9799323SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 4477a5d7347SHarninder Rai status = "disabled"; 4487a5d7347SHarninder Rai }; 4497a5d7347SHarninder Rai 4507a5d7347SHarninder Rai i2c3: i2c@2030000 { 4517a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 4527a5d7347SHarninder Rai #address-cells = <1>; 4537a5d7347SHarninder Rai #size-cells = <0>; 4547a5d7347SHarninder Rai reg = <0x0 0x2030000 0x0 0x10000>; 4557a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 456f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 457f9799323SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 4587a5d7347SHarninder Rai status = "disabled"; 4597a5d7347SHarninder Rai }; 4607a5d7347SHarninder Rai 46168a2b3fdSAshish Kumar qspi: spi@20c0000 { 46268a2b3fdSAshish Kumar compatible = "fsl,ls2080a-qspi"; 46368a2b3fdSAshish Kumar #address-cells = <1>; 46468a2b3fdSAshish Kumar #size-cells = <0>; 46568a2b3fdSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 46668a2b3fdSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 46768a2b3fdSAshish Kumar reg-names = "QuadSPI", "QuadSPI-memory"; 46868a2b3fdSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 46968a2b3fdSAshish Kumar clock-names = "qspi_en", "qspi"; 470f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 471f9799323SMichael Walle QORIQ_CLK_PLL_DIV(4)>, 472f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 473f9799323SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 47468a2b3fdSAshish Kumar status = "disabled"; 47568a2b3fdSAshish Kumar }; 47668a2b3fdSAshish Kumar 477e56ae178SYangbo Lu esdhc: esdhc@2140000 { 478e56ae178SYangbo Lu compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 479e56ae178SYangbo Lu reg = <0x0 0x2140000 0x0 0x10000>; 480e56ae178SYangbo Lu interrupts = <0 28 0x4>; /* Level high type */ 481e56ae178SYangbo Lu clock-frequency = <0>; 482f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 483e56ae178SYangbo Lu voltage-ranges = <1800 1800 3300 3300>; 484e56ae178SYangbo Lu sdhci,auto-cmd12; 485e56ae178SYangbo Lu little-endian; 486e56ae178SYangbo Lu bus-width = <4>; 487e56ae178SYangbo Lu status = "disabled"; 488e56ae178SYangbo Lu }; 489e56ae178SYangbo Lu 490da244504SSerge Semin usb0: usb@3100000 { 491df063a1fSyinbo.zhu compatible = "snps,dwc3"; 492df063a1fSyinbo.zhu reg = <0x0 0x3100000 0x0 0x10000>; 493df063a1fSyinbo.zhu interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 494df063a1fSyinbo.zhu dr_mode = "host"; 495df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 496df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 4971000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 498df063a1fSyinbo.zhu status = "disabled"; 499df063a1fSyinbo.zhu }; 500df063a1fSyinbo.zhu 501da244504SSerge Semin usb1: usb@3110000 { 502df063a1fSyinbo.zhu compatible = "snps,dwc3"; 503df063a1fSyinbo.zhu reg = <0x0 0x3110000 0x0 0x10000>; 504df063a1fSyinbo.zhu interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 505df063a1fSyinbo.zhu dr_mode = "host"; 506df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 507df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 508a3d5b4e2SLi Yang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 509df063a1fSyinbo.zhu status = "disabled"; 510df063a1fSyinbo.zhu }; 511df063a1fSyinbo.zhu 5127a5d7347SHarninder Rai sata: sata@3200000 { 513375b6755SYuantian Tang compatible = "fsl,ls1088a-ahci"; 51483d0c697SYuantian Tang reg = <0x0 0x3200000 0x0 0x10000>, 515375b6755SYuantian Tang <0x7 0x100520 0x0 0x4>; 51683d0c697SYuantian Tang reg-names = "ahci", "sata-ecc"; 5177a5d7347SHarninder Rai interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 518f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 519f9799323SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 52083d0c697SYuantian Tang dma-coherent; 5217a5d7347SHarninder Rai status = "disabled"; 5227a5d7347SHarninder Rai }; 5231e09dec9SHoria Geantă 5241e09dec9SHoria Geantă crypto: crypto@8000000 { 5251e09dec9SHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 5261e09dec9SHoria Geantă fsl,sec-era = <8>; 5271e09dec9SHoria Geantă #address-cells = <1>; 5281e09dec9SHoria Geantă #size-cells = <1>; 5291e09dec9SHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 5301e09dec9SHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 5311e09dec9SHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 5321e09dec9SHoria Geantă dma-coherent; 5331e09dec9SHoria Geantă 5341e09dec9SHoria Geantă sec_jr0: jr@10000 { 5351e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5361e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 5371e09dec9SHoria Geantă reg = <0x10000 0x10000>; 5381e09dec9SHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 5391e09dec9SHoria Geantă }; 5401e09dec9SHoria Geantă 5411e09dec9SHoria Geantă sec_jr1: jr@20000 { 5421e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5431e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 5441e09dec9SHoria Geantă reg = <0x20000 0x10000>; 5451e09dec9SHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 5461e09dec9SHoria Geantă }; 5471e09dec9SHoria Geantă 5481e09dec9SHoria Geantă sec_jr2: jr@30000 { 5491e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5501e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 5511e09dec9SHoria Geantă reg = <0x30000 0x10000>; 5521e09dec9SHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 5531e09dec9SHoria Geantă }; 5541e09dec9SHoria Geantă 5551e09dec9SHoria Geantă sec_jr3: jr@40000 { 5561e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5571e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 5581e09dec9SHoria Geantă reg = <0x40000 0x10000>; 5591e09dec9SHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 5601e09dec9SHoria Geantă }; 5611e09dec9SHoria Geantă }; 562647911c8SHou Zhiqiang 563f7d48ffcSWasim Khan pcie1: pcie@3400000 { 5641fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 565ce87d936SZhen Lei reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 566ce87d936SZhen Lei <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 567647911c8SHou Zhiqiang reg-names = "regs", "config"; 568647911c8SHou Zhiqiang interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 569647911c8SHou Zhiqiang interrupt-names = "aer"; 570647911c8SHou Zhiqiang #address-cells = <3>; 571647911c8SHou Zhiqiang #size-cells = <2>; 572647911c8SHou Zhiqiang device_type = "pci"; 573647911c8SHou Zhiqiang dma-coherent; 574881e90d2SHou Zhiqiang num-viewport = <256>; 575647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 576647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 577647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 578647911c8SHou Zhiqiang msi-parent = <&its>; 579647911c8SHou Zhiqiang #interrupt-cells = <1>; 580647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 581647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 582647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 583647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 584647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 585f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 586aa2aa888SBao Xiaowei status = "disabled"; 587647911c8SHou Zhiqiang }; 588647911c8SHou Zhiqiang 589b6abb313SXiaowei Bao pcie_ep1: pcie-ep@3400000 { 590b6abb313SXiaowei Bao compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 591ce87d936SZhen Lei reg = <0x00 0x03400000 0x0 0x00100000>, 592ce87d936SZhen Lei <0x20 0x00000000 0x8 0x00000000>; 593b6abb313SXiaowei Bao reg-names = "regs", "addr_space"; 594b6abb313SXiaowei Bao num-ib-windows = <24>; 595b6abb313SXiaowei Bao num-ob-windows = <256>; 596b6abb313SXiaowei Bao max-functions = /bits/ 8 <2>; 597b6abb313SXiaowei Bao status = "disabled"; 598b6abb313SXiaowei Bao }; 599b6abb313SXiaowei Bao 600f7d48ffcSWasim Khan pcie2: pcie@3500000 { 6011fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 602ce87d936SZhen Lei reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 603ce87d936SZhen Lei <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 604647911c8SHou Zhiqiang reg-names = "regs", "config"; 605647911c8SHou Zhiqiang interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 606647911c8SHou Zhiqiang interrupt-names = "aer"; 607647911c8SHou Zhiqiang #address-cells = <3>; 608647911c8SHou Zhiqiang #size-cells = <2>; 609647911c8SHou Zhiqiang device_type = "pci"; 610647911c8SHou Zhiqiang dma-coherent; 611881e90d2SHou Zhiqiang num-viewport = <6>; 612647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 613647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 614647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 615647911c8SHou Zhiqiang msi-parent = <&its>; 616647911c8SHou Zhiqiang #interrupt-cells = <1>; 617647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 618647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 619647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 620647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 621647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 622f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 623aa2aa888SBao Xiaowei status = "disabled"; 624647911c8SHou Zhiqiang }; 625647911c8SHou Zhiqiang 626b6abb313SXiaowei Bao pcie_ep2: pcie-ep@3500000 { 627b6abb313SXiaowei Bao compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 628ce87d936SZhen Lei reg = <0x00 0x03500000 0x0 0x00100000>, 629ce87d936SZhen Lei <0x28 0x00000000 0x8 0x00000000>; 630b6abb313SXiaowei Bao reg-names = "regs", "addr_space"; 631b6abb313SXiaowei Bao num-ib-windows = <6>; 632b6abb313SXiaowei Bao num-ob-windows = <6>; 633b6abb313SXiaowei Bao status = "disabled"; 634b6abb313SXiaowei Bao }; 635b6abb313SXiaowei Bao 636f7d48ffcSWasim Khan pcie3: pcie@3600000 { 6371fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 638ce87d936SZhen Lei reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 639ce87d936SZhen Lei <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 640647911c8SHou Zhiqiang reg-names = "regs", "config"; 641647911c8SHou Zhiqiang interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 642647911c8SHou Zhiqiang interrupt-names = "aer"; 643647911c8SHou Zhiqiang #address-cells = <3>; 644647911c8SHou Zhiqiang #size-cells = <2>; 645647911c8SHou Zhiqiang device_type = "pci"; 646647911c8SHou Zhiqiang dma-coherent; 647881e90d2SHou Zhiqiang num-viewport = <6>; 648647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 649647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 650647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 651647911c8SHou Zhiqiang msi-parent = <&its>; 652647911c8SHou Zhiqiang #interrupt-cells = <1>; 653647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 654647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 655647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 656647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 657647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 658f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 659aa2aa888SBao Xiaowei status = "disabled"; 660647911c8SHou Zhiqiang }; 661cc223282SZhang Ying-22455 662b6abb313SXiaowei Bao pcie_ep3: pcie-ep@3600000 { 663b6abb313SXiaowei Bao compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 664ce87d936SZhen Lei reg = <0x00 0x03600000 0x0 0x00100000>, 665ce87d936SZhen Lei <0x30 0x00000000 0x8 0x00000000>; 666b6abb313SXiaowei Bao reg-names = "regs", "addr_space"; 667b6abb313SXiaowei Bao num-ib-windows = <6>; 668b6abb313SXiaowei Bao num-ob-windows = <6>; 669b6abb313SXiaowei Bao status = "disabled"; 670b6abb313SXiaowei Bao }; 671b6abb313SXiaowei Bao 67283c58a55SNipun Gupta smmu: iommu@5000000 { 67383c58a55SNipun Gupta compatible = "arm,mmu-500"; 67483c58a55SNipun Gupta reg = <0 0x5000000 0 0x800000>; 67583c58a55SNipun Gupta #iommu-cells = <1>; 67683c58a55SNipun Gupta stream-match-mask = <0x7C00>; 677acc985b8SVladimir Oltean dma-coherent; 67883c58a55SNipun Gupta #global-interrupts = <12>; 67983c58a55SNipun Gupta // global secure fault 68083c58a55SNipun Gupta interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 68183c58a55SNipun Gupta // combined secure 68283c58a55SNipun Gupta <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 68383c58a55SNipun Gupta // global non-secure fault 68483c58a55SNipun Gupta <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 68583c58a55SNipun Gupta // combined non-secure 68683c58a55SNipun Gupta <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 68783c58a55SNipun Gupta // performance counter interrupts 0-7 68883c58a55SNipun Gupta <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 68983c58a55SNipun Gupta <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 69083c58a55SNipun Gupta <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 69183c58a55SNipun Gupta <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 69283c58a55SNipun Gupta <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 69383c58a55SNipun Gupta <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 69483c58a55SNipun Gupta <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 69583c58a55SNipun Gupta <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 69683c58a55SNipun Gupta // per context interrupt, 64 interrupts 69783c58a55SNipun Gupta <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 69883c58a55SNipun Gupta <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 69983c58a55SNipun Gupta <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 70083c58a55SNipun Gupta <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 70183c58a55SNipun Gupta <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 70283c58a55SNipun Gupta <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 70383c58a55SNipun Gupta <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 70483c58a55SNipun Gupta <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 70583c58a55SNipun Gupta <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 70683c58a55SNipun Gupta <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 70783c58a55SNipun Gupta <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 70883c58a55SNipun Gupta <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 70983c58a55SNipun Gupta <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 71083c58a55SNipun Gupta <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 71183c58a55SNipun Gupta <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 71283c58a55SNipun Gupta <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 71383c58a55SNipun Gupta <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 71483c58a55SNipun Gupta <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 71583c58a55SNipun Gupta <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 71683c58a55SNipun Gupta <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 71783c58a55SNipun Gupta <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 71883c58a55SNipun Gupta <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 71983c58a55SNipun Gupta <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 72083c58a55SNipun Gupta <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 72183c58a55SNipun Gupta <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 72283c58a55SNipun Gupta <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 72383c58a55SNipun Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 72483c58a55SNipun Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 72583c58a55SNipun Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 72683c58a55SNipun Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 72783c58a55SNipun Gupta <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 72883c58a55SNipun Gupta <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 72983c58a55SNipun Gupta <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 73083c58a55SNipun Gupta <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 73183c58a55SNipun Gupta <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 73283c58a55SNipun Gupta <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 73383c58a55SNipun Gupta <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 73483c58a55SNipun Gupta <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 73583c58a55SNipun Gupta <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 73683c58a55SNipun Gupta <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 73783c58a55SNipun Gupta <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 73883c58a55SNipun Gupta <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 73983c58a55SNipun Gupta <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 74083c58a55SNipun Gupta <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 74183c58a55SNipun Gupta <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 74283c58a55SNipun Gupta <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 74383c58a55SNipun Gupta <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 74483c58a55SNipun Gupta <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 74583c58a55SNipun Gupta <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 74683c58a55SNipun Gupta <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 74783c58a55SNipun Gupta <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 74883c58a55SNipun Gupta <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 74983c58a55SNipun Gupta <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 75083c58a55SNipun Gupta <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 75183c58a55SNipun Gupta <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 75283c58a55SNipun Gupta <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 75383c58a55SNipun Gupta <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 75483c58a55SNipun Gupta <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 75583c58a55SNipun Gupta <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 75683c58a55SNipun Gupta <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 75783c58a55SNipun Gupta <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 75883c58a55SNipun Gupta <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 75983c58a55SNipun Gupta <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 76083c58a55SNipun Gupta <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 76183c58a55SNipun Gupta }; 76283c58a55SNipun Gupta 763546d92d3SIoana Ciornei console@8340020 { 764546d92d3SIoana Ciornei compatible = "fsl,dpaa2-console"; 765546d92d3SIoana Ciornei reg = <0x00000000 0x08340020 0 0x2>; 766546d92d3SIoana Ciornei }; 767546d92d3SIoana Ciornei 768fe844f19SYangbo Lu ptp-timer@8b95000 { 769fe844f19SYangbo Lu compatible = "fsl,dpaa2-ptp"; 770fe844f19SYangbo Lu reg = <0x0 0x8b95000 0x0 0x100>; 771f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 772f9799323SMichael Walle QORIQ_CLK_PLL_DIV(1)>; 773fe844f19SYangbo Lu little-endian; 774fe844f19SYangbo Lu fsl,extts-fifo; 775fe844f19SYangbo Lu }; 776fe844f19SYangbo Lu 777bbe75af7SIoana Ciornei emdio1: mdio@8b96000 { 778bbe75af7SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 779bbe75af7SIoana Ciornei reg = <0x0 0x8b96000 0x0 0x1000>; 780bbe75af7SIoana Ciornei little-endian; 781bbe75af7SIoana Ciornei #address-cells = <1>; 782bbe75af7SIoana Ciornei #size-cells = <0>; 783d78a5742SIoana Ciornei clock-frequency = <2500000>; 784d78a5742SIoana Ciornei clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 785d78a5742SIoana Ciornei QORIQ_CLK_PLL_DIV(1)>; 786bbe75af7SIoana Ciornei status = "disabled"; 787bbe75af7SIoana Ciornei }; 788bbe75af7SIoana Ciornei 789bbe75af7SIoana Ciornei emdio2: mdio@8b97000 { 790bbe75af7SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 791bbe75af7SIoana Ciornei reg = <0x0 0x8b97000 0x0 0x1000>; 792bbe75af7SIoana Ciornei little-endian; 793bbe75af7SIoana Ciornei #address-cells = <1>; 794bbe75af7SIoana Ciornei #size-cells = <0>; 795d78a5742SIoana Ciornei clock-frequency = <2500000>; 796d78a5742SIoana Ciornei clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 797d78a5742SIoana Ciornei QORIQ_CLK_PLL_DIV(1)>; 798bbe75af7SIoana Ciornei status = "disabled"; 799bbe75af7SIoana Ciornei }; 800bbe75af7SIoana Ciornei 801e3f9eb03SMathew McBride pcs_mdio1: mdio@8c07000 { 802e3f9eb03SMathew McBride compatible = "fsl,fman-memac-mdio"; 803e3f9eb03SMathew McBride reg = <0x0 0x8c07000 0x0 0x1000>; 804e3f9eb03SMathew McBride little-endian; 805e3f9eb03SMathew McBride #address-cells = <1>; 806e3f9eb03SMathew McBride #size-cells = <0>; 807e3f9eb03SMathew McBride status = "disabled"; 808e3f9eb03SMathew McBride 809e3f9eb03SMathew McBride pcs1: ethernet-phy@0 { 810e3f9eb03SMathew McBride reg = <0>; 811e3f9eb03SMathew McBride }; 812e3f9eb03SMathew McBride }; 813e3f9eb03SMathew McBride 814379b4f76SIoana Ciornei pcs_mdio2: mdio@8c0b000 { 815379b4f76SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 816379b4f76SIoana Ciornei reg = <0x0 0x8c0b000 0x0 0x1000>; 817379b4f76SIoana Ciornei little-endian; 818379b4f76SIoana Ciornei #address-cells = <1>; 819379b4f76SIoana Ciornei #size-cells = <0>; 820379b4f76SIoana Ciornei status = "disabled"; 821379b4f76SIoana Ciornei 822379b4f76SIoana Ciornei pcs2: ethernet-phy@0 { 823379b4f76SIoana Ciornei reg = <0>; 824379b4f76SIoana Ciornei }; 825379b4f76SIoana Ciornei }; 826379b4f76SIoana Ciornei 82773f034ccSIoana Ciornei pcs_mdio3: mdio@8c0f000 { 82873f034ccSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 82973f034ccSIoana Ciornei reg = <0x0 0x8c0f000 0x0 0x1000>; 83073f034ccSIoana Ciornei little-endian; 83173f034ccSIoana Ciornei #address-cells = <1>; 83273f034ccSIoana Ciornei #size-cells = <0>; 83373f034ccSIoana Ciornei status = "disabled"; 83473f034ccSIoana Ciornei 83573f034ccSIoana Ciornei pcs3_0: ethernet-phy@0 { 83673f034ccSIoana Ciornei reg = <0>; 83773f034ccSIoana Ciornei }; 83873f034ccSIoana Ciornei 83973f034ccSIoana Ciornei pcs3_1: ethernet-phy@1 { 84073f034ccSIoana Ciornei reg = <1>; 84173f034ccSIoana Ciornei }; 84273f034ccSIoana Ciornei 84373f034ccSIoana Ciornei pcs3_2: ethernet-phy@2 { 84473f034ccSIoana Ciornei reg = <2>; 84573f034ccSIoana Ciornei }; 84673f034ccSIoana Ciornei 84773f034ccSIoana Ciornei pcs3_3: ethernet-phy@3 { 84873f034ccSIoana Ciornei reg = <3>; 84973f034ccSIoana Ciornei }; 85073f034ccSIoana Ciornei }; 85173f034ccSIoana Ciornei 85273f034ccSIoana Ciornei pcs_mdio7: mdio@8c1f000 { 85373f034ccSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 85473f034ccSIoana Ciornei reg = <0x0 0x8c1f000 0x0 0x1000>; 85573f034ccSIoana Ciornei little-endian; 85673f034ccSIoana Ciornei #address-cells = <1>; 85773f034ccSIoana Ciornei #size-cells = <0>; 85873f034ccSIoana Ciornei status = "disabled"; 85973f034ccSIoana Ciornei 86073f034ccSIoana Ciornei pcs7_0: ethernet-phy@0 { 86173f034ccSIoana Ciornei reg = <0>; 86273f034ccSIoana Ciornei }; 86373f034ccSIoana Ciornei 86473f034ccSIoana Ciornei pcs7_1: ethernet-phy@1 { 86573f034ccSIoana Ciornei reg = <1>; 86673f034ccSIoana Ciornei }; 86773f034ccSIoana Ciornei 86873f034ccSIoana Ciornei pcs7_2: ethernet-phy@2 { 86973f034ccSIoana Ciornei reg = <2>; 87073f034ccSIoana Ciornei }; 87173f034ccSIoana Ciornei 87273f034ccSIoana Ciornei pcs7_3: ethernet-phy@3 { 87373f034ccSIoana Ciornei reg = <3>; 87473f034ccSIoana Ciornei }; 87573f034ccSIoana Ciornei }; 87673f034ccSIoana Ciornei 877cc223282SZhang Ying-22455 cluster1_core0_watchdog: wdt@c000000 { 87899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 879cc223282SZhang Ying-22455 reg = <0x0 0xc000000 0x0 0x1000>; 880f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 881f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 882f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 883f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 884f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 885cc223282SZhang Ying-22455 }; 886cc223282SZhang Ying-22455 887cc223282SZhang Ying-22455 cluster1_core1_watchdog: wdt@c010000 { 88899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 889cc223282SZhang Ying-22455 reg = <0x0 0xc010000 0x0 0x1000>; 890f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 891f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 892f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 893f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 894f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 895cc223282SZhang Ying-22455 }; 896cc223282SZhang Ying-22455 897cc223282SZhang Ying-22455 cluster1_core2_watchdog: wdt@c020000 { 89899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 899cc223282SZhang Ying-22455 reg = <0x0 0xc020000 0x0 0x1000>; 900f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 901f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 902f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 903f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 904f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 905cc223282SZhang Ying-22455 }; 906cc223282SZhang Ying-22455 907cc223282SZhang Ying-22455 cluster1_core3_watchdog: wdt@c030000 { 90899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 909cc223282SZhang Ying-22455 reg = <0x0 0xc030000 0x0 0x1000>; 910f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 911f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 912f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 913f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 914f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 915cc223282SZhang Ying-22455 }; 916cc223282SZhang Ying-22455 917cc223282SZhang Ying-22455 cluster2_core0_watchdog: wdt@c100000 { 91899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 919cc223282SZhang Ying-22455 reg = <0x0 0xc100000 0x0 0x1000>; 920f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 921f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 922f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 923f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 924f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 925cc223282SZhang Ying-22455 }; 926cc223282SZhang Ying-22455 927cc223282SZhang Ying-22455 cluster2_core1_watchdog: wdt@c110000 { 92899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 929cc223282SZhang Ying-22455 reg = <0x0 0xc110000 0x0 0x1000>; 930f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 931f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 932f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 933f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 934f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 935cc223282SZhang Ying-22455 }; 936cc223282SZhang Ying-22455 937cc223282SZhang Ying-22455 cluster2_core2_watchdog: wdt@c120000 { 93899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 939cc223282SZhang Ying-22455 reg = <0x0 0xc120000 0x0 0x1000>; 940f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 941f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 942f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 943f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 944f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 945cc223282SZhang Ying-22455 }; 946cc223282SZhang Ying-22455 947cc223282SZhang Ying-22455 cluster2_core3_watchdog: wdt@c130000 { 94899a7caccSMichael Walle compatible = "arm,sp805", "arm,primecell"; 949cc223282SZhang Ying-22455 reg = <0x0 0xc130000 0x0 0x1000>; 950f9799323SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 951f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 952f9799323SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 953f9799323SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 954f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 955cc223282SZhang Ying-22455 }; 956a2468676SIoana Ciocoi Radulescu 957a2468676SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 958a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 959a2468676SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 960a2468676SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 961a2468676SIoana Ciocoi Radulescu msi-parent = <&its>; 96283c58a55SNipun Gupta iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 963859873fbSNipun Gupta dma-coherent; 964a2468676SIoana Ciocoi Radulescu #address-cells = <3>; 965a2468676SIoana Ciocoi Radulescu #size-cells = <1>; 966a2468676SIoana Ciocoi Radulescu 967a2468676SIoana Ciocoi Radulescu /* 968a2468676SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 969a2468676SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 970a2468676SIoana Ciocoi Radulescu */ 971a2468676SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 972a2468676SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 973a2468676SIoana Ciocoi Radulescu 974a2468676SIoana Ciocoi Radulescu dpmacs { 975a2468676SIoana Ciocoi Radulescu #address-cells = <1>; 976a2468676SIoana Ciocoi Radulescu #size-cells = <0>; 977a2468676SIoana Ciocoi Radulescu 97873f034ccSIoana Ciornei dpmac1: ethernet@1 { 979a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 980a2468676SIoana Ciocoi Radulescu reg = <1>; 981a2468676SIoana Ciocoi Radulescu }; 982a2468676SIoana Ciocoi Radulescu 98373f034ccSIoana Ciornei dpmac2: ethernet@2 { 984a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 985a2468676SIoana Ciocoi Radulescu reg = <2>; 986a2468676SIoana Ciocoi Radulescu }; 987a2468676SIoana Ciocoi Radulescu 98873f034ccSIoana Ciornei dpmac3: ethernet@3 { 989a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 990a2468676SIoana Ciocoi Radulescu reg = <3>; 991a2468676SIoana Ciocoi Radulescu }; 992a2468676SIoana Ciocoi Radulescu 99373f034ccSIoana Ciornei dpmac4: ethernet@4 { 994a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 995a2468676SIoana Ciocoi Radulescu reg = <4>; 996a2468676SIoana Ciocoi Radulescu }; 997a2468676SIoana Ciocoi Radulescu 99873f034ccSIoana Ciornei dpmac5: ethernet@5 { 999a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1000a2468676SIoana Ciocoi Radulescu reg = <5>; 1001a2468676SIoana Ciocoi Radulescu }; 1002a2468676SIoana Ciocoi Radulescu 100373f034ccSIoana Ciornei dpmac6: ethernet@6 { 1004a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1005a2468676SIoana Ciocoi Radulescu reg = <6>; 1006a2468676SIoana Ciocoi Radulescu }; 1007a2468676SIoana Ciocoi Radulescu 100873f034ccSIoana Ciornei dpmac7: ethernet@7 { 1009a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1010a2468676SIoana Ciocoi Radulescu reg = <7>; 1011a2468676SIoana Ciocoi Radulescu }; 1012a2468676SIoana Ciocoi Radulescu 101373f034ccSIoana Ciornei dpmac8: ethernet@8 { 1014a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1015a2468676SIoana Ciocoi Radulescu reg = <8>; 1016a2468676SIoana Ciocoi Radulescu }; 1017a2468676SIoana Ciocoi Radulescu 101873f034ccSIoana Ciornei dpmac9: ethernet@9 { 1019a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1020a2468676SIoana Ciocoi Radulescu reg = <9>; 1021a2468676SIoana Ciocoi Radulescu }; 1022a2468676SIoana Ciocoi Radulescu 102373f034ccSIoana Ciornei dpmac10: ethernet@a { 1024a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1025a2468676SIoana Ciocoi Radulescu reg = <0xa>; 1026a2468676SIoana Ciocoi Radulescu }; 1027a2468676SIoana Ciocoi Radulescu }; 1028a2468676SIoana Ciocoi Radulescu }; 1029f4fe3a86SBiwen Li 1030f4fe3a86SBiwen Li rcpm: power-controller@1e34040 { 1031f4fe3a86SBiwen Li compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1032f4fe3a86SBiwen Li reg = <0x0 0x1e34040 0x0 0x18>; 1033f4fe3a86SBiwen Li #fsl,rcpm-wakeup-cells = <6>; 1034d9245428SBiwen Li little-endian; 1035f4fe3a86SBiwen Li }; 1036f4fe3a86SBiwen Li 1037f4fe3a86SBiwen Li ftm_alarm0: timer@2800000 { 1038f4fe3a86SBiwen Li compatible = "fsl,ls1088a-ftm-alarm"; 1039f4fe3a86SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 1040f4fe3a86SBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 1041f4fe3a86SBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1042f4fe3a86SBiwen Li }; 10437a5d7347SHarninder Rai }; 10447a5d7347SHarninder Rai 104551b29445SSumit Garg firmware { 104651b29445SSumit Garg optee { 104751b29445SSumit Garg compatible = "linaro,optee-tz"; 104851b29445SSumit Garg method = "smc"; 104951b29445SSumit Garg }; 105051b29445SSumit Garg }; 10517a5d7347SHarninder Rai}; 1052