1850db82fSStefan Roese/* 2850db82fSStefan Roese * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3850db82fSStefan Roese * 4850db82fSStefan Roese * Copyright (C) 2016 Marvell 5850db82fSStefan Roese * 6850db82fSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 7850db82fSStefan Roese * 8850db82fSStefan Roese * This file is dual-licensed: you can use it either under the terms 9850db82fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 10850db82fSStefan Roese * licensing only applies to this file, and not this project as a 11850db82fSStefan Roese * whole. 12850db82fSStefan Roese * 13850db82fSStefan Roese * a) This file is free software; you can redistribute it and/or 14850db82fSStefan Roese * modify it under the terms of the GNU General Public License as 15850db82fSStefan Roese * published by the Free Software Foundation; either version 2 of the 16850db82fSStefan Roese * License, or (at your option) any later version. 17850db82fSStefan Roese * 18850db82fSStefan Roese * This file is distributed in the hope that it will be useful 19850db82fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 20850db82fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21850db82fSStefan Roese * GNU General Public License for more details. 22850db82fSStefan Roese * 23850db82fSStefan Roese * Or, alternatively 24850db82fSStefan Roese * 25850db82fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 26850db82fSStefan Roese * obtaining a copy of this software and associated documentation 27850db82fSStefan Roese * files (the "Software"), to deal in the Software without 28850db82fSStefan Roese * restriction, including without limitation the rights to use 29850db82fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 30850db82fSStefan Roese * sell copies of the Software, and to permit persons to whom the 31850db82fSStefan Roese * Software is furnished to do so, subject to the following 32850db82fSStefan Roese * conditions: 33850db82fSStefan Roese * 34850db82fSStefan Roese * The above copyright notice and this permission notice shall be 35850db82fSStefan Roese * included in all copies or substantial portions of the Software. 36850db82fSStefan Roese * 37850db82fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38850db82fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39850db82fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40850db82fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41850db82fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42850db82fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43850db82fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44850db82fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 45850db82fSStefan Roese */ 46850db82fSStefan Roese 47850db82fSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 4856d53956SStefan Roese#include <dt-bindings/comphy/comphy_data.h> 49d13d8ba1SKen Ma#include <dt-bindings/gpio/gpio.h> 50850db82fSStefan Roese 51850db82fSStefan Roese/ { 52850db82fSStefan Roese model = "Marvell Armada 37xx SoC"; 53850db82fSStefan Roese compatible = "marvell,armada3700"; 54850db82fSStefan Roese interrupt-parent = <&gic>; 55850db82fSStefan Roese #address-cells = <2>; 56850db82fSStefan Roese #size-cells = <2>; 57850db82fSStefan Roese 58850db82fSStefan Roese aliases { 59850db82fSStefan Roese serial0 = &uart0; 60850db82fSStefan Roese }; 61850db82fSStefan Roese 62850db82fSStefan Roese cpus { 63850db82fSStefan Roese #address-cells = <1>; 64850db82fSStefan Roese #size-cells = <0>; 65850db82fSStefan Roese cpu@0 { 66850db82fSStefan Roese device_type = "cpu"; 67850db82fSStefan Roese compatible = "arm,cortex-a53", "arm,armv8"; 68850db82fSStefan Roese reg = <0>; 69850db82fSStefan Roese enable-method = "psci"; 70850db82fSStefan Roese }; 71850db82fSStefan Roese }; 72850db82fSStefan Roese 73850db82fSStefan Roese psci { 74850db82fSStefan Roese compatible = "arm,psci-0.2"; 75850db82fSStefan Roese method = "smc"; 76850db82fSStefan Roese }; 77850db82fSStefan Roese 78850db82fSStefan Roese timer { 79850db82fSStefan Roese compatible = "arm,armv8-timer"; 80850db82fSStefan Roese interrupts = <GIC_PPI 13 81850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82850db82fSStefan Roese <GIC_PPI 14 83850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84850db82fSStefan Roese <GIC_PPI 11 85850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 86850db82fSStefan Roese <GIC_PPI 10 87850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 88850db82fSStefan Roese }; 89850db82fSStefan Roese 90850db82fSStefan Roese soc { 91850db82fSStefan Roese compatible = "simple-bus"; 92850db82fSStefan Roese #address-cells = <2>; 93850db82fSStefan Roese #size-cells = <2>; 94850db82fSStefan Roese ranges; 95850db82fSStefan Roese 96850db82fSStefan Roese internal-regs { 97850db82fSStefan Roese #address-cells = <1>; 98850db82fSStefan Roese #size-cells = <1>; 99850db82fSStefan Roese compatible = "simple-bus"; 100850db82fSStefan Roese /* 32M internal register @ 0xd000_0000 */ 101850db82fSStefan Roese ranges = <0x0 0x0 0xd0000000 0x2000000>; 102850db82fSStefan Roese 103850db82fSStefan Roese uart0: serial@12000 { 104850db82fSStefan Roese compatible = "marvell,armada-3700-uart"; 105850db82fSStefan Roese reg = <0x12000 0x400>; 106850db82fSStefan Roese interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 107850db82fSStefan Roese status = "disabled"; 108850db82fSStefan Roese }; 109850db82fSStefan Roese 110*2b69a673SMarek Behún wdt: watchdog-timer@8300 { 111*2b69a673SMarek Behún compatible = "marvell,armada-3700-wdt"; 112*2b69a673SMarek Behún reg = <0xd064 0x4>, 113*2b69a673SMarek Behún <0x8300 0x40>; 114*2b69a673SMarek Behún }; 115*2b69a673SMarek Behún 11682a248dfSMarek Behún nb_periph_clk: nb-periph-clk@13000 { 11782a248dfSMarek Behún compatible = "marvell,armada-3700-periph-clock-nb"; 11882a248dfSMarek Behún reg = <0x13000 0x100>; 11982a248dfSMarek Behún clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>; 12082a248dfSMarek Behún #clock-cells = <1>; 12182a248dfSMarek Behún }; 12282a248dfSMarek Behún 12382a248dfSMarek Behún sb_periph_clk: sb-periph-clk@18000 { 12482a248dfSMarek Behún compatible = "marvell,armada-3700-periph-clock-sb"; 12582a248dfSMarek Behún reg = <0x18000 0x100>; 12682a248dfSMarek Behún clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>; 12782a248dfSMarek Behún #clock-cells = <1>; 12882a248dfSMarek Behún }; 12982a248dfSMarek Behún 13082a248dfSMarek Behún tbg: tbg@13200 { 13182a248dfSMarek Behún compatible = "marvell,armada-3700-tbg-clock"; 13282a248dfSMarek Behún reg = <0x13200 0x100>; 13382a248dfSMarek Behún #clock-cells = <1>; 13482a248dfSMarek Behún }; 13582a248dfSMarek Behún 1365cb7b795SGregory CLEMENT pinctrl_nb: pinctrl-nb@13800 { 1375cb7b795SGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 1385cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 1395cb7b795SGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 1405cb7b795SGregory CLEMENT gpionb: gpionb { 1415cb7b795SGregory CLEMENT #gpio-cells = <2>; 1425cb7b795SGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 1435cb7b795SGregory CLEMENT gpio-controller; 1445cb7b795SGregory CLEMENT interrupts = 1455cb7b795SGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1465cb7b795SGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1475cb7b795SGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1485cb7b795SGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1495cb7b795SGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1505cb7b795SGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1515cb7b795SGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1525cb7b795SGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1535cb7b795SGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1545cb7b795SGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1555cb7b795SGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1565cb7b795SGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1575cb7b795SGregory CLEMENT 1585cb7b795SGregory CLEMENT }; 159045504bbSGregory CLEMENT 160045504bbSGregory CLEMENT spi_quad_pins: spi-quad-pins { 161045504bbSGregory CLEMENT groups = "spi_quad"; 162045504bbSGregory CLEMENT function = "spi"; 163045504bbSGregory CLEMENT }; 164045504bbSGregory CLEMENT 165045504bbSGregory CLEMENT i2c1_pins: i2c1-pins { 166045504bbSGregory CLEMENT groups = "i2c1"; 167045504bbSGregory CLEMENT function = "i2c"; 168045504bbSGregory CLEMENT }; 169045504bbSGregory CLEMENT 170045504bbSGregory CLEMENT i2c2_pins: i2c2-pins { 171045504bbSGregory CLEMENT groups = "i2c2"; 172045504bbSGregory CLEMENT function = "i2c"; 173045504bbSGregory CLEMENT }; 174045504bbSGregory CLEMENT 175045504bbSGregory CLEMENT uart1_pins: uart1-pins { 176045504bbSGregory CLEMENT groups = "uart1"; 177045504bbSGregory CLEMENT function = "uart"; 178045504bbSGregory CLEMENT }; 179045504bbSGregory CLEMENT 180045504bbSGregory CLEMENT uart2_pins: uart2-pins { 181045504bbSGregory CLEMENT groups = "uart2"; 182045504bbSGregory CLEMENT function = "uart"; 183045504bbSGregory CLEMENT }; 1844382e53eSKen Ma 1854382e53eSKen Ma mmc_pins: mmc-pins { 1864382e53eSKen Ma groups = "emmc_nb"; 1874382e53eSKen Ma function = "emmc"; 1884382e53eSKen Ma }; 1895cb7b795SGregory CLEMENT }; 1905cb7b795SGregory CLEMENT 1915cb7b795SGregory CLEMENT pinctrl_sb: pinctrl-sb@18800 { 1925cb7b795SGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 1935cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 1945cb7b795SGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 1955cb7b795SGregory CLEMENT gpiosb: gpiosb { 1965cb7b795SGregory CLEMENT #gpio-cells = <2>; 1978aecbcd1SKen Ma gpio-ranges = <&pinctrl_sb 0 0 30>; 1985cb7b795SGregory CLEMENT gpio-controller; 1995cb7b795SGregory CLEMENT interrupts = 2005cb7b795SGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2015cb7b795SGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 2025cb7b795SGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 2035cb7b795SGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 2045cb7b795SGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 2055cb7b795SGregory CLEMENT }; 206045504bbSGregory CLEMENT 207045504bbSGregory CLEMENT rgmii_pins: mii-pins { 208045504bbSGregory CLEMENT groups = "rgmii"; 209045504bbSGregory CLEMENT function = "mii"; 210045504bbSGregory CLEMENT }; 211045504bbSGregory CLEMENT 21230aecc02SKen Ma smi_pins: smi-pins { 21330aecc02SKen Ma groups = "smi"; 21430aecc02SKen Ma function = "smi"; 21530aecc02SKen Ma }; 21630aecc02SKen Ma 2174382e53eSKen Ma sdio_pins: sdio-pins { 2184382e53eSKen Ma groups = "sdio_sb"; 2194382e53eSKen Ma function = "sdio"; 2204382e53eSKen Ma }; 2214382e53eSKen Ma 2224382e53eSKen Ma pcie_pins: pcie-pins { 2234382e53eSKen Ma groups = "pcie1"; 22430aecc02SKen Ma function = "gpio"; 2254382e53eSKen Ma }; 2265cb7b795SGregory CLEMENT }; 2275cb7b795SGregory CLEMENT 228850db82fSStefan Roese usb3: usb@58000 { 229850db82fSStefan Roese compatible = "marvell,armada3700-xhci", 230850db82fSStefan Roese "generic-xhci"; 231850db82fSStefan Roese reg = <0x58000 0x4000>; 232850db82fSStefan Roese interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 233850db82fSStefan Roese status = "disabled"; 234850db82fSStefan Roese }; 235850db82fSStefan Roese 236f733228aSStefan Roese usb2: usb@5e000 { 237f733228aSStefan Roese compatible = "marvell,armada3700-ehci"; 238f733228aSStefan Roese reg = <0x5e000 0x450>; 239f733228aSStefan Roese status = "disabled"; 240f733228aSStefan Roese }; 241f733228aSStefan Roese 242850db82fSStefan Roese xor@60900 { 243850db82fSStefan Roese compatible = "marvell,armada-3700-xor"; 244850db82fSStefan Roese reg = <0x60900 0x100 245850db82fSStefan Roese 0x60b00 0x100>; 246850db82fSStefan Roese 247850db82fSStefan Roese xor10 { 248850db82fSStefan Roese interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 249850db82fSStefan Roese }; 250850db82fSStefan Roese xor11 { 251850db82fSStefan Roese interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 252850db82fSStefan Roese }; 253850db82fSStefan Roese }; 254850db82fSStefan Roese 255cbe0ece8SStefan Roese sdhci0: sdhci@d0000 { 256cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 257cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 258cbe0ece8SStefan Roese reg = <0xd0000 0x300 259cbe0ece8SStefan Roese 0x1e808 0x4>; 260cbe0ece8SStefan Roese status = "disabled"; 261cbe0ece8SStefan Roese }; 262cbe0ece8SStefan Roese 263cbe0ece8SStefan Roese sdhci1: sdhci@d8000 { 264cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 265cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 266cbe0ece8SStefan Roese reg = <0xd8000 0x300 267cbe0ece8SStefan Roese 0x17808 0x4>; 268cbe0ece8SStefan Roese status = "disabled"; 269cbe0ece8SStefan Roese }; 270cbe0ece8SStefan Roese 271850db82fSStefan Roese sata: sata@e0000 { 272850db82fSStefan Roese compatible = "marvell,armada-3700-ahci"; 273850db82fSStefan Roese reg = <0xe0000 0x2000>; 274850db82fSStefan Roese interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 275850db82fSStefan Roese status = "disabled"; 276850db82fSStefan Roese }; 277850db82fSStefan Roese 278850db82fSStefan Roese gic: interrupt-controller@1d00000 { 279850db82fSStefan Roese compatible = "arm,gic-v3"; 280850db82fSStefan Roese #interrupt-cells = <3>; 281850db82fSStefan Roese interrupt-controller; 282850db82fSStefan Roese reg = <0x1d00000 0x10000>, /* GICD */ 283850db82fSStefan Roese <0x1d40000 0x40000>; /* GICR */ 284850db82fSStefan Roese }; 285cdccf9c1SStefan Roese 2863f84e2e8SStefan Roese eth0: neta@30000 { 2873f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2883f84e2e8SStefan Roese reg = <0x30000 0x20>; 2893f84e2e8SStefan Roese status = "disabled"; 2903f84e2e8SStefan Roese }; 2913f84e2e8SStefan Roese 2923f84e2e8SStefan Roese eth1: neta@40000 { 2933f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2943f84e2e8SStefan Roese reg = <0x40000 0x20>; 2953f84e2e8SStefan Roese status = "disabled"; 2963f84e2e8SStefan Roese }; 2973f84e2e8SStefan Roese 2989e9e63c0SStefan Roese i2c0: i2c@11000 { 2999e9e63c0SStefan Roese compatible = "marvell,armada-3700-i2c"; 3009e9e63c0SStefan Roese reg = <0x11000 0x100>; 3019e9e63c0SStefan Roese status = "disabled"; 3029e9e63c0SStefan Roese }; 3039e9e63c0SStefan Roese 304cdccf9c1SStefan Roese spi0: spi@10600 { 305cdccf9c1SStefan Roese compatible = "marvell,armada-3700-spi"; 306cdccf9c1SStefan Roese reg = <0x10600 0x50>; 307cdccf9c1SStefan Roese #address-cells = <1>; 308cdccf9c1SStefan Roese #size-cells = <0>; 309cdccf9c1SStefan Roese #clock-cells = <0>; 310dbbd5bddSMarek Behún spi-max-frequency = <50000000>; 311dbbd5bddSMarek Behún clocks = <&nb_periph_clk 7>; 312cdccf9c1SStefan Roese status = "disabled"; 313cdccf9c1SStefan Roese }; 31456d53956SStefan Roese 31556d53956SStefan Roese comphy: comphy@18300 { 31656d53956SStefan Roese compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 31756d53956SStefan Roese reg = <0x18300 0x28>, 31856d53956SStefan Roese <0x1f300 0x3d000>; 31922f41893SMarek Behún mux-bitcount = <4>; 32022f41893SMarek Behún mux-lane-order = <1 0 2>; 32122f41893SMarek Behún max-lanes = <3>; 32256d53956SStefan Roese }; 323850db82fSStefan Roese }; 3249734104fSWilson Ding 3259734104fSWilson Ding pcie0: pcie@d0070000 { 3269734104fSWilson Ding compatible = "marvell,armada-37xx-pcie"; 3279734104fSWilson Ding reg = <0 0xd0070000 0 0x20000>; 3289734104fSWilson Ding #address-cells = <3>; 3299734104fSWilson Ding #size-cells = <2>; 3309734104fSWilson Ding device_type = "pci"; 3319734104fSWilson Ding num-lanes = <1>; 3329734104fSWilson Ding status = "disabled"; 3339734104fSWilson Ding 3349734104fSWilson Ding bus-range = <0 0xff>; 3359734104fSWilson Ding ranges = <0x82000000 0 0xe8000000 3369734104fSWilson Ding 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 3379734104fSWilson Ding 0x81000000 0 0xe9000000 3389734104fSWilson Ding 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 3399734104fSWilson Ding }; 340850db82fSStefan Roese }; 341850db82fSStefan Roese}; 342