13d91ba65SAisheng Dong// SPDX-License-Identifier: GPL-2.0+ 23d91ba65SAisheng Dong/* 33d91ba65SAisheng Dong * Copyright (C) 2016 Freescale Semiconductor, Inc. 40dcd27bdSDong Aisheng * Copyright 2017-2020 NXP 53d91ba65SAisheng Dong * Dong Aisheng <aisheng.dong@nxp.com> 63d91ba65SAisheng Dong */ 73d91ba65SAisheng Dong 83d91ba65SAisheng Dong#include <dt-bindings/clock/imx8-clock.h> 916c4ea75SDong Aisheng#include <dt-bindings/clock/imx8-lpcg.h> 103d91ba65SAisheng Dong#include <dt-bindings/firmware/imx/rsrc.h> 113d91ba65SAisheng Dong#include <dt-bindings/gpio/gpio.h> 1249dad0c1SAnson Huang#include <dt-bindings/input/input.h> 133d91ba65SAisheng Dong#include <dt-bindings/interrupt-controller/arm-gic.h> 143d91ba65SAisheng Dong#include <dt-bindings/pinctrl/pads-imx8qxp.h> 15f0cac141SAnson Huang#include <dt-bindings/thermal/thermal.h> 163d91ba65SAisheng Dong 173d91ba65SAisheng Dong/ { 183d91ba65SAisheng Dong interrupt-parent = <&gic>; 193d91ba65SAisheng Dong #address-cells = <2>; 203d91ba65SAisheng Dong #size-cells = <2>; 213d91ba65SAisheng Dong 223d91ba65SAisheng Dong aliases { 233c8f8d8fSPeng Fan ethernet0 = &fec1; 243c8f8d8fSPeng Fan ethernet1 = &fec2; 25ddabee1eSAnson Huang gpio0 = &lsio_gpio0; 26ddabee1eSAnson Huang gpio1 = &lsio_gpio1; 27ddabee1eSAnson Huang gpio2 = &lsio_gpio2; 28ddabee1eSAnson Huang gpio3 = &lsio_gpio3; 29ddabee1eSAnson Huang gpio4 = &lsio_gpio4; 30ddabee1eSAnson Huang gpio5 = &lsio_gpio5; 31ddabee1eSAnson Huang gpio6 = &lsio_gpio6; 32ddabee1eSAnson Huang gpio7 = &lsio_gpio7; 3335f4e9d7SDong Aisheng i2c0 = &i2c0; 3435f4e9d7SDong Aisheng i2c1 = &i2c1; 3535f4e9d7SDong Aisheng i2c2 = &i2c2; 3635f4e9d7SDong Aisheng i2c3 = &i2c3; 373d91ba65SAisheng Dong mmc0 = &usdhc1; 383d91ba65SAisheng Dong mmc1 = &usdhc2; 393d91ba65SAisheng Dong mmc2 = &usdhc3; 4044f45d5cSPeng Fan mu0 = &lsio_mu0; 416b2bcbd8SAnson Huang mu1 = &lsio_mu1; 4244f45d5cSPeng Fan mu2 = &lsio_mu2; 4344f45d5cSPeng Fan mu3 = &lsio_mu3; 4444f45d5cSPeng Fan mu4 = &lsio_mu4; 4535f4e9d7SDong Aisheng serial0 = &lpuart0; 4635f4e9d7SDong Aisheng serial1 = &lpuart1; 4735f4e9d7SDong Aisheng serial2 = &lpuart2; 4835f4e9d7SDong Aisheng serial3 = &lpuart3; 49*fb8f715eSAlexander Stein vpu-core0 = &vpu_core0; 50*fb8f715eSAlexander Stein vpu-core1 = &vpu_core1; 51*fb8f715eSAlexander Stein vpu-core2 = &vpu_core2; 523d91ba65SAisheng Dong }; 533d91ba65SAisheng Dong 543d91ba65SAisheng Dong cpus { 553d91ba65SAisheng Dong #address-cells = <2>; 563d91ba65SAisheng Dong #size-cells = <0>; 573d91ba65SAisheng Dong 583d91ba65SAisheng Dong /* We have 1 clusters with 4 Cortex-A35 cores */ 593d91ba65SAisheng Dong A35_0: cpu@0 { 603d91ba65SAisheng Dong device_type = "cpu"; 613d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 623d91ba65SAisheng Dong reg = <0x0 0x0>; 633d91ba65SAisheng Dong enable-method = "psci"; 64ebd92296SPeng Fan i-cache-size = <0x8000>; 65ebd92296SPeng Fan i-cache-line-size = <64>; 66ebd92296SPeng Fan i-cache-sets = <256>; 67ebd92296SPeng Fan d-cache-size = <0x8000>; 68ebd92296SPeng Fan d-cache-line-size = <64>; 69ebd92296SPeng Fan d-cache-sets = <128>; 703d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 7126de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 727be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 737be494ddSAnson Huang #cooling-cells = <2>; 743d91ba65SAisheng Dong }; 753d91ba65SAisheng Dong 763d91ba65SAisheng Dong A35_1: cpu@1 { 773d91ba65SAisheng Dong device_type = "cpu"; 783d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 793d91ba65SAisheng Dong reg = <0x0 0x1>; 803d91ba65SAisheng Dong enable-method = "psci"; 81ebd92296SPeng Fan i-cache-size = <0x8000>; 82ebd92296SPeng Fan i-cache-line-size = <64>; 83ebd92296SPeng Fan i-cache-sets = <256>; 84ebd92296SPeng Fan d-cache-size = <0x8000>; 85ebd92296SPeng Fan d-cache-line-size = <64>; 86ebd92296SPeng Fan d-cache-sets = <128>; 873d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 8826de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 897be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 907be494ddSAnson Huang #cooling-cells = <2>; 913d91ba65SAisheng Dong }; 923d91ba65SAisheng Dong 933d91ba65SAisheng Dong A35_2: cpu@2 { 943d91ba65SAisheng Dong device_type = "cpu"; 953d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 963d91ba65SAisheng Dong reg = <0x0 0x2>; 973d91ba65SAisheng Dong enable-method = "psci"; 98ebd92296SPeng Fan i-cache-size = <0x8000>; 99ebd92296SPeng Fan i-cache-line-size = <64>; 100ebd92296SPeng Fan i-cache-sets = <256>; 101ebd92296SPeng Fan d-cache-size = <0x8000>; 102ebd92296SPeng Fan d-cache-line-size = <64>; 103ebd92296SPeng Fan d-cache-sets = <128>; 1043d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 10526de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 1067be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 1077be494ddSAnson Huang #cooling-cells = <2>; 1083d91ba65SAisheng Dong }; 1093d91ba65SAisheng Dong 1103d91ba65SAisheng Dong A35_3: cpu@3 { 1113d91ba65SAisheng Dong device_type = "cpu"; 1123d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 1133d91ba65SAisheng Dong reg = <0x0 0x3>; 1143d91ba65SAisheng Dong enable-method = "psci"; 115ebd92296SPeng Fan i-cache-size = <0x8000>; 116ebd92296SPeng Fan i-cache-line-size = <64>; 117ebd92296SPeng Fan i-cache-sets = <256>; 118ebd92296SPeng Fan d-cache-size = <0x8000>; 119ebd92296SPeng Fan d-cache-line-size = <64>; 120ebd92296SPeng Fan d-cache-sets = <128>; 1213d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 12226de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 1237be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 1247be494ddSAnson Huang #cooling-cells = <2>; 1253d91ba65SAisheng Dong }; 1263d91ba65SAisheng Dong 1273d91ba65SAisheng Dong A35_L2: l2-cache0 { 1283d91ba65SAisheng Dong compatible = "cache"; 129ebd92296SPeng Fan cache-level = <2>; 1303b450831SPierre Gondois cache-unified; 131ebd92296SPeng Fan cache-size = <0x80000>; 132ebd92296SPeng Fan cache-line-size = <64>; 133ebd92296SPeng Fan cache-sets = <1024>; 1343d91ba65SAisheng Dong }; 1353d91ba65SAisheng Dong }; 1363d91ba65SAisheng Dong 1377be494ddSAnson Huang a35_opp_table: opp-table { 1387be494ddSAnson Huang compatible = "operating-points-v2"; 1397be494ddSAnson Huang opp-shared; 1407be494ddSAnson Huang 1417be494ddSAnson Huang opp-900000000 { 1427be494ddSAnson Huang opp-hz = /bits/ 64 <900000000>; 1437be494ddSAnson Huang opp-microvolt = <1000000>; 1447be494ddSAnson Huang clock-latency-ns = <150000>; 1457be494ddSAnson Huang }; 1467be494ddSAnson Huang 1477be494ddSAnson Huang opp-1200000000 { 1487be494ddSAnson Huang opp-hz = /bits/ 64 <1200000000>; 1497be494ddSAnson Huang opp-microvolt = <1100000>; 1507be494ddSAnson Huang clock-latency-ns = <150000>; 1517be494ddSAnson Huang opp-suspend; 1527be494ddSAnson Huang }; 1537be494ddSAnson Huang }; 1547be494ddSAnson Huang 1553d91ba65SAisheng Dong gic: interrupt-controller@51a00000 { 1563d91ba65SAisheng Dong compatible = "arm,gic-v3"; 1573d91ba65SAisheng Dong reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 1583d91ba65SAisheng Dong <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 1593d91ba65SAisheng Dong #interrupt-cells = <3>; 1603d91ba65SAisheng Dong interrupt-controller; 1613d91ba65SAisheng Dong interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1623d91ba65SAisheng Dong }; 1633d91ba65SAisheng Dong 164cd42fa17SDaniel Baluta reserved-memory { 165cd42fa17SDaniel Baluta #address-cells = <2>; 166cd42fa17SDaniel Baluta #size-cells = <2>; 167cd42fa17SDaniel Baluta ranges; 168cd42fa17SDaniel Baluta 1690d9968d9SMing Qian decoder_boot: decoder-boot@84000000 { 1700d9968d9SMing Qian reg = <0 0x84000000 0 0x2000000>; 1710d9968d9SMing Qian no-map; 1720d9968d9SMing Qian }; 1730d9968d9SMing Qian 1740d9968d9SMing Qian encoder_boot: encoder-boot@86000000 { 1750d9968d9SMing Qian reg = <0 0x86000000 0 0x200000>; 1760d9968d9SMing Qian no-map; 1770d9968d9SMing Qian }; 1780d9968d9SMing Qian 1790d9968d9SMing Qian decoder_rpc: decoder-rpc@92000000 { 1800d9968d9SMing Qian reg = <0 0x92000000 0 0x100000>; 1810d9968d9SMing Qian no-map; 1820d9968d9SMing Qian }; 1830d9968d9SMing Qian 184cd42fa17SDaniel Baluta dsp_reserved: dsp@92400000 { 185cd42fa17SDaniel Baluta reg = <0 0x92400000 0 0x2000000>; 186cd42fa17SDaniel Baluta no-map; 187cd42fa17SDaniel Baluta }; 1880d9968d9SMing Qian 1890d9968d9SMing Qian encoder_rpc: encoder-rpc@94400000 { 1900d9968d9SMing Qian reg = <0 0x94400000 0 0x700000>; 1910d9968d9SMing Qian no-map; 1920d9968d9SMing Qian }; 193cd42fa17SDaniel Baluta }; 194cd42fa17SDaniel Baluta 1953d91ba65SAisheng Dong pmu { 19616ce4ce3SPeng Fan compatible = "arm,cortex-a35-pmu"; 1973d91ba65SAisheng Dong interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1983d91ba65SAisheng Dong }; 1993d91ba65SAisheng Dong 2003d91ba65SAisheng Dong psci { 2013d91ba65SAisheng Dong compatible = "arm,psci-1.0"; 2023d91ba65SAisheng Dong method = "smc"; 2033d91ba65SAisheng Dong }; 2043d91ba65SAisheng Dong 205c7b3c053SViorel Suman system-controller { 2063d91ba65SAisheng Dong compatible = "fsl,imx-scu"; 20768956811SPeng Fan mbox-names = "tx0", 20868956811SPeng Fan "rx0", 2096b2bcbd8SAnson Huang "gip3"; 2103d91ba65SAisheng Dong mboxes = <&lsio_mu1 0 0 2113d91ba65SAisheng Dong &lsio_mu1 1 0 2126b2bcbd8SAnson Huang &lsio_mu1 3 3>; 2133d91ba65SAisheng Dong 214b3993c7aSAbel Vesa pd: power-controller { 215b1484229SDong Aisheng compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 216b1484229SDong Aisheng #power-domain-cells = <1>; 217b1484229SDong Aisheng }; 218b1484229SDong Aisheng 2193d91ba65SAisheng Dong clk: clock-controller { 220b64aebbeSAbel Vesa compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 22126de33a1SDong Aisheng #clock-cells = <2>; 2223d91ba65SAisheng Dong }; 2233d91ba65SAisheng Dong 2243d91ba65SAisheng Dong iomuxc: pinctrl { 2253d91ba65SAisheng Dong compatible = "fsl,imx8qxp-iomuxc"; 2263d91ba65SAisheng Dong }; 2273d91ba65SAisheng Dong 2286003913aSViorel Suman ocotp: ocotp { 229ef9ed87eSPeng Fan compatible = "fsl,imx8qxp-scu-ocotp"; 230ef9ed87eSPeng Fan #address-cells = <1>; 231ef9ed87eSPeng Fan #size-cells = <1>; 232ef9ed87eSPeng Fan }; 233ef9ed87eSPeng Fan 2343876f482SAbel Vesa scu_key: keys { 23549dad0c1SAnson Huang compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 23649dad0c1SAnson Huang linux,keycodes = <KEY_POWER>; 23749dad0c1SAnson Huang status = "disabled"; 23849dad0c1SAnson Huang }; 23949dad0c1SAnson Huang 2406334f879SAnson Huang rtc: rtc { 2416334f879SAnson Huang compatible = "fsl,imx8qxp-sc-rtc"; 2426334f879SAnson Huang }; 243db9693aaSAnson Huang 244db9693aaSAnson Huang watchdog { 245db9693aaSAnson Huang compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 246db9693aaSAnson Huang timeout-sec = <60>; 247db9693aaSAnson Huang }; 248f0cac141SAnson Huang 249f0cac141SAnson Huang tsens: thermal-sensor { 250f0cac141SAnson Huang compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 251f0cac141SAnson Huang #thermal-sensor-cells = <1>; 252f0cac141SAnson Huang }; 2533d91ba65SAisheng Dong }; 2543d91ba65SAisheng Dong 2553d91ba65SAisheng Dong timer { 2563d91ba65SAisheng Dong compatible = "arm,armv8-timer"; 2573d91ba65SAisheng Dong interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 2583d91ba65SAisheng Dong <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 2593d91ba65SAisheng Dong <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 2603d91ba65SAisheng Dong <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 2613d91ba65SAisheng Dong }; 2623d91ba65SAisheng Dong 2633d91ba65SAisheng Dong xtal32k: clock-xtal32k { 2643d91ba65SAisheng Dong compatible = "fixed-clock"; 2653d91ba65SAisheng Dong #clock-cells = <0>; 2663d91ba65SAisheng Dong clock-frequency = <32768>; 2673d91ba65SAisheng Dong clock-output-names = "xtal_32KHz"; 2683d91ba65SAisheng Dong }; 2693d91ba65SAisheng Dong 2703d91ba65SAisheng Dong xtal24m: clock-xtal24m { 2713d91ba65SAisheng Dong compatible = "fixed-clock"; 2723d91ba65SAisheng Dong #clock-cells = <0>; 2733d91ba65SAisheng Dong clock-frequency = <24000000>; 2743d91ba65SAisheng Dong clock-output-names = "xtal_24MHz"; 2753d91ba65SAisheng Dong }; 2763d91ba65SAisheng Dong 277f0cac141SAnson Huang thermal_zones: thermal-zones { 278518d5f16SAbel Vesa cpu0-thermal { 279f0cac141SAnson Huang polling-delay-passive = <250>; 280f0cac141SAnson Huang polling-delay = <2000>; 281f0cac141SAnson Huang thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 282f0cac141SAnson Huang 283f0cac141SAnson Huang trips { 284f0cac141SAnson Huang cpu_alert0: trip0 { 285f0cac141SAnson Huang temperature = <107000>; 286f0cac141SAnson Huang hysteresis = <2000>; 287f0cac141SAnson Huang type = "passive"; 288f0cac141SAnson Huang }; 289f0cac141SAnson Huang 290f0cac141SAnson Huang cpu_crit0: trip1 { 291f0cac141SAnson Huang temperature = <127000>; 292f0cac141SAnson Huang hysteresis = <2000>; 293f0cac141SAnson Huang type = "critical"; 294f0cac141SAnson Huang }; 295f0cac141SAnson Huang }; 296f0cac141SAnson Huang 297f0cac141SAnson Huang cooling-maps { 298f0cac141SAnson Huang map0 { 299f0cac141SAnson Huang trip = <&cpu_alert0>; 300f0cac141SAnson Huang cooling-device = 301f0cac141SAnson Huang <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 302f0cac141SAnson Huang <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 303f0cac141SAnson Huang <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 304f0cac141SAnson Huang <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 305f0cac141SAnson Huang }; 306f0cac141SAnson Huang }; 307f0cac141SAnson Huang }; 308f0cac141SAnson Huang }; 3090dcd27bdSDong Aisheng 3100dcd27bdSDong Aisheng /* sorted in register address */ 3115bb27917SMirela Rabulea #include "imx8-ss-img.dtsi" 3120d9968d9SMing Qian #include "imx8-ss-vpu.dtsi" 3130dcd27bdSDong Aisheng #include "imx8-ss-adma.dtsi" 3140dcd27bdSDong Aisheng #include "imx8-ss-conn.dtsi" 3150dcd27bdSDong Aisheng #include "imx8-ss-ddr.dtsi" 3160dcd27bdSDong Aisheng #include "imx8-ss-lsio.dtsi" 3173d91ba65SAisheng Dong}; 3180dcd27bdSDong Aisheng 3195bb27917SMirela Rabulea#include "imx8qxp-ss-img.dtsi" 3200dcd27bdSDong Aisheng#include "imx8qxp-ss-adma.dtsi" 3210dcd27bdSDong Aisheng#include "imx8qxp-ss-conn.dtsi" 3220dcd27bdSDong Aisheng#include "imx8qxp-ss-lsio.dtsi" 323