1031106ceSJisheng Zhang// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2031106ceSJisheng Zhang/* 3031106ceSJisheng Zhang * Copyright (C) 2015 Marvell Technology Group Ltd. 4031106ceSJisheng Zhang * 5031106ceSJisheng Zhang * Author: Jisheng Zhang <jszhang@marvell.com> 6031106ceSJisheng Zhang */ 7031106ceSJisheng Zhang 8031106ceSJisheng Zhang#include <dt-bindings/interrupt-controller/arm-gic.h> 9031106ceSJisheng Zhang 10031106ceSJisheng Zhang/ { 11031106ceSJisheng Zhang compatible = "marvell,berlin4ct", "marvell,berlin"; 12031106ceSJisheng Zhang interrupt-parent = <&gic>; 13031106ceSJisheng Zhang #address-cells = <2>; 14031106ceSJisheng Zhang #size-cells = <2>; 15031106ceSJisheng Zhang 16031106ceSJisheng Zhang aliases { 17031106ceSJisheng Zhang serial0 = &uart0; 18031106ceSJisheng Zhang }; 19031106ceSJisheng Zhang 20031106ceSJisheng Zhang psci { 21031106ceSJisheng Zhang compatible = "arm,psci-1.0", "arm,psci-0.2"; 22031106ceSJisheng Zhang method = "smc"; 23031106ceSJisheng Zhang }; 24031106ceSJisheng Zhang 25031106ceSJisheng Zhang cpus { 26031106ceSJisheng Zhang #address-cells = <1>; 27031106ceSJisheng Zhang #size-cells = <0>; 28031106ceSJisheng Zhang 29031106ceSJisheng Zhang cpu0: cpu@0 { 3031af04cdSRob Herring compatible = "arm,cortex-a53"; 31031106ceSJisheng Zhang device_type = "cpu"; 32031106ceSJisheng Zhang reg = <0x0>; 33031106ceSJisheng Zhang enable-method = "psci"; 34031106ceSJisheng Zhang next-level-cache = <&l2>; 35031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 36031106ceSJisheng Zhang }; 37031106ceSJisheng Zhang 38031106ceSJisheng Zhang cpu1: cpu@1 { 3931af04cdSRob Herring compatible = "arm,cortex-a53"; 40031106ceSJisheng Zhang device_type = "cpu"; 41031106ceSJisheng Zhang reg = <0x1>; 42031106ceSJisheng Zhang enable-method = "psci"; 43031106ceSJisheng Zhang next-level-cache = <&l2>; 44031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 45031106ceSJisheng Zhang }; 46031106ceSJisheng Zhang 47031106ceSJisheng Zhang cpu2: cpu@2 { 4831af04cdSRob Herring compatible = "arm,cortex-a53"; 49031106ceSJisheng Zhang device_type = "cpu"; 50031106ceSJisheng Zhang reg = <0x2>; 51031106ceSJisheng Zhang enable-method = "psci"; 52031106ceSJisheng Zhang next-level-cache = <&l2>; 53031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 54031106ceSJisheng Zhang }; 55031106ceSJisheng Zhang 56031106ceSJisheng Zhang cpu3: cpu@3 { 5731af04cdSRob Herring compatible = "arm,cortex-a53"; 58031106ceSJisheng Zhang device_type = "cpu"; 59031106ceSJisheng Zhang reg = <0x3>; 60031106ceSJisheng Zhang enable-method = "psci"; 61031106ceSJisheng Zhang next-level-cache = <&l2>; 62031106ceSJisheng Zhang cpu-idle-states = <&CPU_SLEEP_0>; 63031106ceSJisheng Zhang }; 64031106ceSJisheng Zhang 65031106ceSJisheng Zhang l2: cache { 66031106ceSJisheng Zhang compatible = "cache"; 67*3740a577SKrzysztof Kozlowski cache-level = <2>; 68*3740a577SKrzysztof Kozlowski cache-unified; 69031106ceSJisheng Zhang }; 70031106ceSJisheng Zhang 71031106ceSJisheng Zhang idle-states { 72031106ceSJisheng Zhang entry-method = "psci"; 73031106ceSJisheng Zhang CPU_SLEEP_0: cpu-sleep-0 { 74031106ceSJisheng Zhang compatible = "arm,idle-state"; 75031106ceSJisheng Zhang local-timer-stop; 76031106ceSJisheng Zhang arm,psci-suspend-param = <0x0010000>; 77031106ceSJisheng Zhang entry-latency-us = <75>; 78031106ceSJisheng Zhang exit-latency-us = <155>; 79031106ceSJisheng Zhang min-residency-us = <1000>; 80031106ceSJisheng Zhang }; 81031106ceSJisheng Zhang }; 82031106ceSJisheng Zhang }; 83031106ceSJisheng Zhang 84031106ceSJisheng Zhang osc: osc { 85031106ceSJisheng Zhang compatible = "fixed-clock"; 86031106ceSJisheng Zhang #clock-cells = <0>; 87031106ceSJisheng Zhang clock-frequency = <25000000>; 88031106ceSJisheng Zhang }; 89031106ceSJisheng Zhang 90031106ceSJisheng Zhang pmu { 91031106ceSJisheng Zhang compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 92031106ceSJisheng Zhang interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 93031106ceSJisheng Zhang <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 94031106ceSJisheng Zhang <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 95031106ceSJisheng Zhang <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 96031106ceSJisheng Zhang interrupt-affinity = <&cpu0>, 97031106ceSJisheng Zhang <&cpu1>, 98031106ceSJisheng Zhang <&cpu2>, 99031106ceSJisheng Zhang <&cpu3>; 100031106ceSJisheng Zhang }; 101031106ceSJisheng Zhang 102031106ceSJisheng Zhang timer { 103031106ceSJisheng Zhang compatible = "arm,armv8-timer"; 104031106ceSJisheng Zhang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 105031106ceSJisheng Zhang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 106031106ceSJisheng Zhang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 107031106ceSJisheng Zhang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 108031106ceSJisheng Zhang }; 109031106ceSJisheng Zhang 110031106ceSJisheng Zhang soc@f7000000 { 111031106ceSJisheng Zhang compatible = "simple-bus"; 112031106ceSJisheng Zhang #address-cells = <1>; 113031106ceSJisheng Zhang #size-cells = <1>; 114031106ceSJisheng Zhang ranges = <0 0 0xf7000000 0x1000000>; 115031106ceSJisheng Zhang 116031106ceSJisheng Zhang gic: interrupt-controller@901000 { 117031106ceSJisheng Zhang compatible = "arm,gic-400"; 118031106ceSJisheng Zhang #interrupt-cells = <3>; 119031106ceSJisheng Zhang interrupt-controller; 120031106ceSJisheng Zhang reg = <0x901000 0x1000>, 121031106ceSJisheng Zhang <0x902000 0x2000>, 122031106ceSJisheng Zhang <0x904000 0x2000>, 123031106ceSJisheng Zhang <0x906000 0x2000>; 124031106ceSJisheng Zhang interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 125031106ceSJisheng Zhang }; 126031106ceSJisheng Zhang 127031106ceSJisheng Zhang apb@e80000 { 128031106ceSJisheng Zhang compatible = "simple-bus"; 129031106ceSJisheng Zhang #address-cells = <1>; 130031106ceSJisheng Zhang #size-cells = <1>; 131031106ceSJisheng Zhang 132031106ceSJisheng Zhang ranges = <0 0xe80000 0x10000>; 133031106ceSJisheng Zhang interrupt-parent = <&aic>; 134031106ceSJisheng Zhang 135031106ceSJisheng Zhang gpio0: gpio@400 { 136031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 137031106ceSJisheng Zhang reg = <0x0400 0x400>; 138031106ceSJisheng Zhang #address-cells = <1>; 139031106ceSJisheng Zhang #size-cells = <0>; 140031106ceSJisheng Zhang 141031106ceSJisheng Zhang porta: gpio-port@0 { 142031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 143031106ceSJisheng Zhang gpio-controller; 144031106ceSJisheng Zhang #gpio-cells = <2>; 145ec13e502SJisheng Zhang ngpios = <32>; 146031106ceSJisheng Zhang reg = <0>; 147031106ceSJisheng Zhang interrupt-controller; 148031106ceSJisheng Zhang #interrupt-cells = <2>; 149031106ceSJisheng Zhang interrupts = <0>; 150031106ceSJisheng Zhang }; 151031106ceSJisheng Zhang }; 152031106ceSJisheng Zhang 153031106ceSJisheng Zhang gpio1: gpio@800 { 154031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 155031106ceSJisheng Zhang reg = <0x0800 0x400>; 156031106ceSJisheng Zhang #address-cells = <1>; 157031106ceSJisheng Zhang #size-cells = <0>; 158031106ceSJisheng Zhang 159031106ceSJisheng Zhang portb: gpio-port@1 { 160031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 161031106ceSJisheng Zhang gpio-controller; 162031106ceSJisheng Zhang #gpio-cells = <2>; 163ec13e502SJisheng Zhang ngpios = <32>; 164031106ceSJisheng Zhang reg = <0>; 165031106ceSJisheng Zhang interrupt-controller; 166031106ceSJisheng Zhang #interrupt-cells = <2>; 167031106ceSJisheng Zhang interrupts = <1>; 168031106ceSJisheng Zhang }; 169031106ceSJisheng Zhang }; 170031106ceSJisheng Zhang 171031106ceSJisheng Zhang gpio2: gpio@c00 { 172031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 173031106ceSJisheng Zhang reg = <0x0c00 0x400>; 174031106ceSJisheng Zhang #address-cells = <1>; 175031106ceSJisheng Zhang #size-cells = <0>; 176031106ceSJisheng Zhang 177031106ceSJisheng Zhang portc: gpio-port@2 { 178031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 179031106ceSJisheng Zhang gpio-controller; 180031106ceSJisheng Zhang #gpio-cells = <2>; 181ec13e502SJisheng Zhang ngpios = <32>; 182031106ceSJisheng Zhang reg = <0>; 183031106ceSJisheng Zhang interrupt-controller; 184031106ceSJisheng Zhang #interrupt-cells = <2>; 185031106ceSJisheng Zhang interrupts = <2>; 186031106ceSJisheng Zhang }; 187031106ceSJisheng Zhang }; 188031106ceSJisheng Zhang 189031106ceSJisheng Zhang gpio3: gpio@1000 { 190031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 191031106ceSJisheng Zhang reg = <0x1000 0x400>; 192031106ceSJisheng Zhang #address-cells = <1>; 193031106ceSJisheng Zhang #size-cells = <0>; 194031106ceSJisheng Zhang 195031106ceSJisheng Zhang portd: gpio-port@3 { 196031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 197031106ceSJisheng Zhang gpio-controller; 198031106ceSJisheng Zhang #gpio-cells = <2>; 199ec13e502SJisheng Zhang ngpios = <32>; 200031106ceSJisheng Zhang reg = <0>; 201031106ceSJisheng Zhang interrupt-controller; 202031106ceSJisheng Zhang #interrupt-cells = <2>; 203031106ceSJisheng Zhang interrupts = <3>; 204031106ceSJisheng Zhang }; 205031106ceSJisheng Zhang }; 206031106ceSJisheng Zhang 207031106ceSJisheng Zhang aic: interrupt-controller@3800 { 208031106ceSJisheng Zhang compatible = "snps,dw-apb-ictl"; 209031106ceSJisheng Zhang reg = <0x3800 0x30>; 210031106ceSJisheng Zhang interrupt-controller; 211031106ceSJisheng Zhang #interrupt-cells = <1>; 212031106ceSJisheng Zhang interrupt-parent = <&gic>; 213031106ceSJisheng Zhang interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 214031106ceSJisheng Zhang }; 215031106ceSJisheng Zhang }; 216031106ceSJisheng Zhang 217031106ceSJisheng Zhang soc_pinctrl: pin-controller@ea8000 { 218031106ceSJisheng Zhang compatible = "marvell,berlin4ct-soc-pinctrl"; 219031106ceSJisheng Zhang reg = <0xea8000 0x14>; 220031106ceSJisheng Zhang }; 221031106ceSJisheng Zhang 222031106ceSJisheng Zhang avio_pinctrl: pin-controller@ea8400 { 223031106ceSJisheng Zhang compatible = "marvell,berlin4ct-avio-pinctrl"; 224031106ceSJisheng Zhang reg = <0xea8400 0x8>; 225031106ceSJisheng Zhang }; 226031106ceSJisheng Zhang 227031106ceSJisheng Zhang apb@fc0000 { 228031106ceSJisheng Zhang compatible = "simple-bus"; 229031106ceSJisheng Zhang #address-cells = <1>; 230031106ceSJisheng Zhang #size-cells = <1>; 231031106ceSJisheng Zhang ranges = <0 0xfc0000 0x10000>; 232031106ceSJisheng Zhang interrupt-parent = <&sic>; 233031106ceSJisheng Zhang 234031106ceSJisheng Zhang sic: interrupt-controller@1000 { 235031106ceSJisheng Zhang compatible = "snps,dw-apb-ictl"; 236031106ceSJisheng Zhang reg = <0x1000 0x30>; 237031106ceSJisheng Zhang interrupt-controller; 238031106ceSJisheng Zhang #interrupt-cells = <1>; 239031106ceSJisheng Zhang interrupt-parent = <&gic>; 240031106ceSJisheng Zhang interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 241031106ceSJisheng Zhang }; 242031106ceSJisheng Zhang 243031106ceSJisheng Zhang wdt0: watchdog@3000 { 244031106ceSJisheng Zhang compatible = "snps,dw-wdt"; 245031106ceSJisheng Zhang reg = <0x3000 0x100>; 246031106ceSJisheng Zhang clocks = <&osc>; 247031106ceSJisheng Zhang interrupts = <0>; 248031106ceSJisheng Zhang }; 249031106ceSJisheng Zhang 250031106ceSJisheng Zhang wdt1: watchdog@4000 { 251031106ceSJisheng Zhang compatible = "snps,dw-wdt"; 252031106ceSJisheng Zhang reg = <0x4000 0x100>; 253031106ceSJisheng Zhang clocks = <&osc>; 254031106ceSJisheng Zhang interrupts = <1>; 255031106ceSJisheng Zhang }; 256031106ceSJisheng Zhang 257031106ceSJisheng Zhang wdt2: watchdog@5000 { 258031106ceSJisheng Zhang compatible = "snps,dw-wdt"; 259031106ceSJisheng Zhang reg = <0x5000 0x100>; 260031106ceSJisheng Zhang clocks = <&osc>; 261031106ceSJisheng Zhang interrupts = <2>; 262031106ceSJisheng Zhang }; 263031106ceSJisheng Zhang 264031106ceSJisheng Zhang sm_gpio0: gpio@8000 { 265031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 266031106ceSJisheng Zhang reg = <0x8000 0x400>; 267031106ceSJisheng Zhang #address-cells = <1>; 268031106ceSJisheng Zhang #size-cells = <0>; 269031106ceSJisheng Zhang 270031106ceSJisheng Zhang porte: gpio-port@4 { 271031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 272031106ceSJisheng Zhang gpio-controller; 273031106ceSJisheng Zhang #gpio-cells = <2>; 274ec13e502SJisheng Zhang ngpios = <32>; 275031106ceSJisheng Zhang reg = <0>; 276031106ceSJisheng Zhang }; 277031106ceSJisheng Zhang }; 278031106ceSJisheng Zhang 279031106ceSJisheng Zhang sm_gpio1: gpio@9000 { 280031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio"; 281031106ceSJisheng Zhang reg = <0x9000 0x400>; 282031106ceSJisheng Zhang #address-cells = <1>; 283031106ceSJisheng Zhang #size-cells = <0>; 284031106ceSJisheng Zhang 285031106ceSJisheng Zhang portf: gpio-port@5 { 286031106ceSJisheng Zhang compatible = "snps,dw-apb-gpio-port"; 287031106ceSJisheng Zhang gpio-controller; 288031106ceSJisheng Zhang #gpio-cells = <2>; 289ec13e502SJisheng Zhang ngpios = <32>; 290031106ceSJisheng Zhang reg = <0>; 291031106ceSJisheng Zhang }; 292031106ceSJisheng Zhang }; 293031106ceSJisheng Zhang 2940a9b7beeSKrzysztof Kozlowski uart0: serial@d000 { 295031106ceSJisheng Zhang compatible = "snps,dw-apb-uart"; 296031106ceSJisheng Zhang reg = <0xd000 0x100>; 297031106ceSJisheng Zhang interrupts = <8>; 298031106ceSJisheng Zhang clocks = <&osc>; 299031106ceSJisheng Zhang reg-shift = <2>; 300031106ceSJisheng Zhang status = "disabled"; 301031106ceSJisheng Zhang pinctrl-0 = <&uart0_pmux>; 302031106ceSJisheng Zhang pinctrl-names = "default"; 303031106ceSJisheng Zhang }; 304031106ceSJisheng Zhang }; 305031106ceSJisheng Zhang 306031106ceSJisheng Zhang system_pinctrl: pin-controller@fe2200 { 307031106ceSJisheng Zhang compatible = "marvell,berlin4ct-system-pinctrl"; 308031106ceSJisheng Zhang reg = <0xfe2200 0xc>; 309031106ceSJisheng Zhang 310031106ceSJisheng Zhang uart0_pmux: uart0-pmux { 311031106ceSJisheng Zhang groups = "SM_URT0_TXD", "SM_URT0_RXD"; 312031106ceSJisheng Zhang function = "uart0"; 313031106ceSJisheng Zhang }; 314031106ceSJisheng Zhang }; 315031106ceSJisheng Zhang }; 316031106ceSJisheng Zhang}; 317