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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
23 - const: sifive,spi0
26 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
32 - const: sifive,pwm0
34 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 - sifive,fu540-c000-pdma
33 - const: sifive,pdma0
35 Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
24 - const: sifive,uart0
27 Should be something similar to "sifive,<chip>-uart"
29 and "sifive,uart<version>" for the general UART IP
[all …]
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
181 compatible = "sifive,fu540-c000-prci";
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H A Dfu740-c000.dtsi2 /* Copyright (c) 2020 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
11 compatible = "sifive,fu740-c000", "sifive,fu740";
26 compatible = "sifive,bullet0", "riscv";
42 compatible = "sifive,bullet0", "riscv";
66 compatible = "sifive,bullet0", "riscv";
90 compatible = "sifive,bullet0", "riscv";
114 compatible = "sifive,bullet0", "riscv";
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
182 compatible = "sifive,fu740-c000-prci";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dsifive,ccache0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
36 - sifive,ccache0
37 - sifive,fu540-c000-ccache
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
7 title: SiFive Core Local Interruptor
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
25 compatible with SiFive ones.
33 - sifive,fu540-c000-clint # SiFive FU540
36 - const: sifive,clint0 # SiFive CLINT v0 IP block
43 - const: sifive,clint0
49 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
50 when compatible with a SiFive CLINT. Please refer to
51 sifive-blocks-ip-versioning.txt for details regarding the latter.
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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dsifive.yaml4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
23 - sifive,hifive-unleashed-a00
24 - const: sifive,fu540-c000
25 - const: sifive,fu540
29 - sifive,hifive-unmatched-a00
30 - const: sifive,fu740-c000
[all …]
H A Dcpus.yaml10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
37 - sifive,bullet0
38 - sifive,e5
39 - sifive,e7
40 - sifive,e71
41 - sifive,rocket0
42 - sifive,s7
43 - sifive,u5
44 - sifive,u54
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
19 - const: sifive,gpio0
44 It is 16 for the SiFive SoCs and 32 for the Canaan K210.
69 - sifive,fu540-c000-gpio
70 - sifive,fu740-c000-gpio
79 #include <dt-bindings/clock/sifive-fu540-prci.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
48 - Paul Walmsley <paul.walmsley@sifive.com>
61 - sifive,fu540-c000-plic
64 - const: sifive,plic-1.0.0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu740-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#
8 title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)
11 - Zong Li <zong.li@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.
27 const: sifive,fu740-c000-prci
59 compatible = "sifive,fu740-c000-prci";
H A Dfu540-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <paul.walmsley@sifive.com>
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
26 const: sifive,fu540-c000-prci
55 compatible = "sifive,fu540-c000-prci";
/openbmc/linux/arch/riscv/
H A DKconfig.errata25 bool "SiFive errata"
28 All SiFive errata Kconfig depend on this Kconfig. Disabling
29 this Kconfig will disable all SiFive errata. Please say "Y"
30 here if your platform uses SiFive CPU cores.
35 bool "Apply SiFive errata CIP-453"
39 This will apply the SiFive CIP-453 errata to add sign extension
46 bool "Apply SiFive errata CIP-1200"
50 This will apply the SiFive CIP-1200 errata to repalce all
/openbmc/u-boot/board/sifive/fu540/
H A DMAINTAINERS1 SiFive FU540 BOARD
2 M: Paul Walmsley <paul.walmsley@sifive.com>
3 M: Palmer Dabbelt <palmer@sifive.com>
7 F: board/sifive/fu540/
8 F: include/configs/sifive-fu540.h
/openbmc/qemu/hw/riscv/
H A Dsifive_e.c2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
4 * Copyright (c) 2017 SiFive, Inc.
6 * Provides a board compatible with the SiFive Freedom E SDK:
148 mc->desc = "RISC-V Board compatible with SiFive E SDK"; in sifive_e_machine_class_init()
152 mc->default_ram_id = "riscv.sifive.e.ram"; in sifive_e_machine_class_init()
186 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, in type_init()
188 object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, in type_init()
204 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", in sifive_e_soc_realize()
263 create_unimplemented_device("riscv.sifive.e.qspi0", in sifive_e_soc_realize()
265 create_unimplemented_device("riscv.sifive.e.pwm0", in sifive_e_soc_realize()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsifive,fu740-pcie.yaml4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
7 title: SiFive FU740 PCIe host controller
10 SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
24 const: sifive,fu740-pcie
87 #include <dt-bindings/clock/sifive-fu740-prci.h>
90 compatible = "sifive,fu740-pcie";
/openbmc/linux/drivers/tty/serial/
H A Dsifive.c3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
12 * - drivers/pwm/pwm-sifive.c
16 * SiFive FE310-G000 v2p3
18 * https://github.com/sifive/sifive-blocks/
20 * The SiFive UART design is not 8250-compatible. The following common
117 #define SIFIVE_SERIAL_NAME "sifive-serial"
119 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
145 * Configuration data specific to this SiFive UART.
178 * __ssp_early_writel() - write to a SiFive serial port register (early)
[all …]
/openbmc/linux/drivers/edac/
H A Dsifive_edac.c3 * SiFive Platform EDAC Driver
5 * Copyright (C) 2018-2022 SiFive, Inc.
13 #include <soc/sifive/sifive_ccache.h>
61 p->dci->mod_name = "Sifive ECC Manager"; in ecc_register()
117 MODULE_AUTHOR("SiFive Inc.");
118 MODULE_DESCRIPTION("SiFive platform EDAC driver");
/openbmc/u-boot/drivers/clk/sifive/
H A DKconfig7 bool "SiFive SoC driver support"
10 SoC drivers for SiFive Linux-capable SoCs.
13 bool "PRCI driver for SiFive FU540 SoCs"
18 FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
/openbmc/linux/drivers/clk/sifive/
H A DKconfig4 bool "SiFive SoC driver support"
8 SoC drivers for SiFive Linux-capable SoCs.
13 bool "PRCI driver for SiFive SoCs"
20 FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
/openbmc/qemu/target/riscv/
H A Dcpu-qom.h45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
200 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";

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