16b49329aSSagar Kadam# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 26b49329aSSagar Kadam# Copyright (C) 2020 SiFive, Inc. 36b49329aSSagar Kadam%YAML 1.2 46b49329aSSagar Kadam--- 56b49329aSSagar Kadam$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml# 66b49329aSSagar Kadam$schema: http://devicetree.org/meta-schemas/core.yaml# 76b49329aSSagar Kadam 86b49329aSSagar Kadamtitle: SiFive PWM controller 96b49329aSSagar Kadam 106b49329aSSagar Kadammaintainers: 116b49329aSSagar Kadam - Paul Walmsley <paul.walmsley@sifive.com> 126b49329aSSagar Kadam 136b49329aSSagar Kadamdescription: 146b49329aSSagar Kadam Unlike most other PWM controllers, the SiFive PWM controller currently 156b49329aSSagar Kadam only supports one period for all channels in the PWM. All PWMs need to 166b49329aSSagar Kadam run at the same period. The period also has significant restrictions on 176b49329aSSagar Kadam the values it can achieve, which the driver rounds to the nearest 186b49329aSSagar Kadam achievable period. PWM RTL that corresponds to the IP block version 196b49329aSSagar Kadam numbers can be found here - 206b49329aSSagar Kadam 216b49329aSSagar Kadam https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm 226b49329aSSagar Kadam 23*e040921cSKrzysztof KozlowskiallOf: 24*e040921cSKrzysztof Kozlowski - $ref: pwm.yaml# 25*e040921cSKrzysztof Kozlowski 266b49329aSSagar Kadamproperties: 276b49329aSSagar Kadam compatible: 286b49329aSSagar Kadam items: 29b1f592d5SYash Shah - enum: 30b1f592d5SYash Shah - sifive,fu540-c000-pwm 31b1f592d5SYash Shah - sifive,fu740-c000-pwm 326b49329aSSagar Kadam - const: sifive,pwm0 336b49329aSSagar Kadam description: 346b49329aSSagar Kadam Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported 35b1f592d5SYash Shah compatible strings are "sifive,fu540-c000-pwm" and 36b1f592d5SYash Shah "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the 37b1f592d5SYash Shah SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the 386b49329aSSagar Kadam SiFive PWM v0 IP block with no chip integration tweaks. 396b49329aSSagar Kadam Please refer to sifive-blocks-ip-versioning.txt for details. 406b49329aSSagar Kadam 416b49329aSSagar Kadam reg: 426b49329aSSagar Kadam maxItems: 1 436b49329aSSagar Kadam 446b49329aSSagar Kadam clocks: 456b49329aSSagar Kadam maxItems: 1 466b49329aSSagar Kadam 476b49329aSSagar Kadam "#pwm-cells": 486b49329aSSagar Kadam const: 3 496b49329aSSagar Kadam 506b49329aSSagar Kadam interrupts: 516b49329aSSagar Kadam maxItems: 4 526b49329aSSagar Kadam description: 536b49329aSSagar Kadam Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator. 546b49329aSSagar Kadam 556b49329aSSagar Kadamrequired: 566b49329aSSagar Kadam - compatible 576b49329aSSagar Kadam - reg 586b49329aSSagar Kadam - clocks 596b49329aSSagar Kadam - interrupts 606b49329aSSagar Kadam 616b49329aSSagar KadamadditionalProperties: false 626b49329aSSagar Kadam 636b49329aSSagar Kadamexamples: 646b49329aSSagar Kadam - | 656b49329aSSagar Kadam pwm: pwm@10020000 { 666b49329aSSagar Kadam compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; 676b49329aSSagar Kadam reg = <0x10020000 0x1000>; 686b49329aSSagar Kadam clocks = <&tlclk>; 696b49329aSSagar Kadam interrupt-parent = <&plic>; 706b49329aSSagar Kadam interrupts = <42>, <43>, <44>, <45>; 716b49329aSSagar Kadam #pwm-cells = <3>; 726b49329aSSagar Kadam }; 73