1a3d095acSAndrew Jonesmenu "CPU errata selection" 2a3d095acSAndrew Jones 3e021ae7fSLad Prabhakarconfig ERRATA_ANDES 4e021ae7fSLad Prabhakar bool "Andes AX45MP errata" 52f73b35dSLad Prabhakar depends on RISCV_ALTERNATIVE && RISCV_SBI 6e021ae7fSLad Prabhakar help 7e021ae7fSLad Prabhakar All Andes errata Kconfig depend on this Kconfig. Disabling 8e021ae7fSLad Prabhakar this Kconfig will disable all Andes errata. Please say "Y" 9e021ae7fSLad Prabhakar here if your platform uses Andes CPU cores. 10e021ae7fSLad Prabhakar 11e021ae7fSLad Prabhakar Otherwise, please say "N" here to avoid unnecessary overhead. 12e021ae7fSLad Prabhakar 13e021ae7fSLad Prabhakarconfig ERRATA_ANDES_CMO 14e021ae7fSLad Prabhakar bool "Apply Andes cache management errata" 1554adc24cSLad Prabhakar depends on ERRATA_ANDES && ARCH_R9A07G043 16e021ae7fSLad Prabhakar select RISCV_DMA_NONCOHERENT 17e021ae7fSLad Prabhakar default y 18e021ae7fSLad Prabhakar help 19e021ae7fSLad Prabhakar This will apply the cache management errata to handle the 20e021ae7fSLad Prabhakar non-standard handling on non-coherent operations on Andes cores. 21e021ae7fSLad Prabhakar 22e021ae7fSLad Prabhakar If you don't know what to do here, say "Y". 23e021ae7fSLad Prabhakar 24a3d095acSAndrew Jonesconfig ERRATA_SIFIVE 25a3d095acSAndrew Jones bool "SiFive errata" 26be693ef2SPalmer Dabbelt depends on RISCV_ALTERNATIVE 27a3d095acSAndrew Jones help 28a3d095acSAndrew Jones All SiFive errata Kconfig depend on this Kconfig. Disabling 29a3d095acSAndrew Jones this Kconfig will disable all SiFive errata. Please say "Y" 30a3d095acSAndrew Jones here if your platform uses SiFive CPU cores. 31a3d095acSAndrew Jones 32a3d095acSAndrew Jones Otherwise, please say "N" here to avoid unnecessary overhead. 33a3d095acSAndrew Jones 34a3d095acSAndrew Jonesconfig ERRATA_SIFIVE_CIP_453 35a3d095acSAndrew Jones bool "Apply SiFive errata CIP-453" 36a3d095acSAndrew Jones depends on ERRATA_SIFIVE && 64BIT 37a3d095acSAndrew Jones default y 38a3d095acSAndrew Jones help 39a3d095acSAndrew Jones This will apply the SiFive CIP-453 errata to add sign extension 40a3d095acSAndrew Jones to the $badaddr when exception type is instruction page fault 41a3d095acSAndrew Jones and instruction access fault. 42a3d095acSAndrew Jones 43a3d095acSAndrew Jones If you don't know what to do here, say "Y". 44a3d095acSAndrew Jones 45a3d095acSAndrew Jonesconfig ERRATA_SIFIVE_CIP_1200 46a3d095acSAndrew Jones bool "Apply SiFive errata CIP-1200" 47a3d095acSAndrew Jones depends on ERRATA_SIFIVE && 64BIT 48a3d095acSAndrew Jones default y 49a3d095acSAndrew Jones help 50a3d095acSAndrew Jones This will apply the SiFive CIP-1200 errata to repalce all 51a3d095acSAndrew Jones "sfence.vma addr" with "sfence.vma" to ensure that the addr 52a3d095acSAndrew Jones has been flushed from TLB. 53a3d095acSAndrew Jones 54a3d095acSAndrew Jones If you don't know what to do here, say "Y". 55a3d095acSAndrew Jones 56a3d095acSAndrew Jonesconfig ERRATA_THEAD 57a3d095acSAndrew Jones bool "T-HEAD errata" 58be693ef2SPalmer Dabbelt depends on RISCV_ALTERNATIVE 59a3d095acSAndrew Jones help 60a3d095acSAndrew Jones All T-HEAD errata Kconfig depend on this Kconfig. Disabling 61a3d095acSAndrew Jones this Kconfig will disable all T-HEAD errata. Please say "Y" 62a3d095acSAndrew Jones here if your platform uses T-HEAD CPU cores. 63a3d095acSAndrew Jones 64a3d095acSAndrew Jones Otherwise, please say "N" here to avoid unnecessary overhead. 65a3d095acSAndrew Jones 66a3d095acSAndrew Jonesconfig ERRATA_THEAD_PBMT 67a3d095acSAndrew Jones bool "Apply T-Head memory type errata" 68a3d095acSAndrew Jones depends on ERRATA_THEAD && 64BIT && MMU 69a3d095acSAndrew Jones select RISCV_ALTERNATIVE_EARLY 70a3d095acSAndrew Jones default y 71a3d095acSAndrew Jones help 72a3d095acSAndrew Jones This will apply the memory type errata to handle the non-standard 73a3d095acSAndrew Jones memory type bits in page-table-entries on T-Head SoCs. 74a3d095acSAndrew Jones 75a3d095acSAndrew Jones If you don't know what to do here, say "Y". 76a3d095acSAndrew Jones 77a3d095acSAndrew Jonesconfig ERRATA_THEAD_CMO 78a3d095acSAndrew Jones bool "Apply T-Head cache management errata" 79a3d095acSAndrew Jones depends on ERRATA_THEAD && MMU 80*381cae16SChristoph Hellwig select DMA_DIRECT_REMAP 81a3d095acSAndrew Jones select RISCV_DMA_NONCOHERENT 82a3d095acSAndrew Jones default y 83a3d095acSAndrew Jones help 84a3d095acSAndrew Jones This will apply the cache management errata to handle the 85a3d095acSAndrew Jones non-standard handling on non-coherent operations on T-Head SoCs. 86a3d095acSAndrew Jones 87a3d095acSAndrew Jones If you don't know what to do here, say "Y". 88a3d095acSAndrew Jones 89a3d095acSAndrew Jonesconfig ERRATA_THEAD_PMU 90a3d095acSAndrew Jones bool "Apply T-Head PMU errata" 91a3d095acSAndrew Jones depends on ERRATA_THEAD && RISCV_PMU_SBI 92a3d095acSAndrew Jones default y 93a3d095acSAndrew Jones help 94a3d095acSAndrew Jones The T-Head C9xx cores implement a PMU overflow extension very 95a3d095acSAndrew Jones similar to the core SSCOFPMF extension. 96a3d095acSAndrew Jones 97a3d095acSAndrew Jones This will apply the overflow errata to handle the non-standard 98a3d095acSAndrew Jones behaviour via the regular SBI PMU driver and interface. 99a3d095acSAndrew Jones 100a3d095acSAndrew Jones If you don't know what to do here, say "Y". 101a3d095acSAndrew Jones 102a3d095acSAndrew Jonesendmenu # "CPU errata selection" 103