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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dvirt-v7.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Routines to transition ARMv7 processors from secure into non-secure state
7 * and from non-secure SVC into HYP mode
15 #include <asm/secure.h>
19 unsigned int reg; in read_id_pfr1() local
21 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); in read_id_pfr1()
22 return reg; in read_id_pfr1()
36 * encode this). Bail out here since we cannot access this without in get_gicd_base_address()
40 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); in get_gicd_base_address()
41 return -1; in get_gicd_base_address()
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
22 - enum:
23 - qcom,msm8916-iommu
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H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
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H A Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
23 By default, the access issuing initiator is informed about the error
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
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/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
24 - st,stm32f4-otp
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H A Dqcom,sec-qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc, Secure QFPROM Efuse
10 - Komal Bajaj <quic_kbajaj@quicinc.com>
14 protected from non-secure access. In such situations, the OS have to use
15 secure calls to read the region.
18 - $ref: nvmem.yaml#
23 - enum:
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/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Chen-Yu Tsai <wens@csie.org>
7 * which was based on code by Carl van Schaik <carl@ok-labs.com>.
19 #include <asm/secure.h>
32 * The power clamps are located in the unused space after the per-core
63 u32 reg = ONE_MS * ms; in __mdelay() local
65 cp15_write_cntp_tval(reg); in __mdelay()
71 reg = cp15_read_cntp_ctl(); in __mdelay()
72 } while (!(reg & BIT(2))); in __mdelay()
133 writel((u32)entry, &cpucfg->priv0); in sunxi_set_entry_address()
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/openbmc/linux/drivers/nvmem/
H A Dsec-qfprom.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/nvmem-provider.h>
13 * struct sec_qfprom - structure holding secure qfprom attributes
15 * @base: starting physical address for secure qfprom corrected address space.
23 static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) in sec_qfprom_reg_read() argument
31 for (i = 0; i < bytes; i++, reg++) { in sec_qfprom_reg_read()
32 if (i == 0 || reg % 4 == 0) { in sec_qfprom_reg_read()
33 if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) { in sec_qfprom_reg_read()
34 dev_err(priv->dev, "Couldn't access fuse register\n"); in sec_qfprom_reg_read()
35 return -EINVAL; in sec_qfprom_reg_read()
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/openbmc/qemu/target/arm/
H A Dcpregs.h2 * QEMU ARM CP Register access and descriptions
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
25 #include "target/arm/kvm-consts.h"
51 /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
78 * Flag: Register has no underlying state and does not support raw access
91 * Flag: Writes to the sysreg might change the exception level - typically
92 * on older ARM chips. For those cases we need to re-read the new el when
97 * Flag: Access check for this sysreg is identical to accessing FPU state
102 * Flag: Access check for this sysreg is identical to accessing SVE state
110 * - UNDEF: discard the cpreg,
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/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "cpu-features.h"
14 #include "exec/helper-proto.h"
15 #include "qemu/main-loop.h"
18 #include "exec/exec-all.h"
19 #include "exec/page-protection.h"
22 #include "semihosting/common-semi.h"
29 uint32_t reg, uint32_t val) in v7m_msr_xpsr() argument
32 if (!(reg & 4)) { in v7m_msr_xpsr()
45 static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) in v7m_mrs_xpsr() argument
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/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c19 /* Return a 32-bit mask which should be applied for this set of 32 in mask_group()
20 * interrupts; each bit is 1 if access is permitted by the in mask_group()
21 * combination of attrs.secure and GICR_GROUPR. (GICR_NSACR does in mask_group()
24 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in mask_group()
25 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in mask_group()
26 return cs->gicr_igroupr0; in mask_group()
35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
39 uint32_t *reg, uint32_t val) in gicr_write_bitmap_reg() argument
43 *reg = val; in gicr_write_bitmap_reg()
48 uint32_t *reg, uint32_t val) in gicr_write_set_bitmap_reg() argument
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dscu.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 uint scu_reserved0[12]; /* reserved, offset 10-3C */
17 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
18 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
19 uint scu_reserved1[2]; /* reserved, offset 48-4C */
20 uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
21 uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
/openbmc/u-boot/drivers/crypto/fsl/
H A Djobdesc.c1 // SPDX-License-Identifier: GPL-2.0+
18 * Secure memory run command
20 * @param sec_mem_cmd Secure memory command register
21 * @return cmd_status Secure memory command status register
28 uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); in secmem_set_cmd()
42 * Allocates a partition from secure memory, with the id
43 * equal to partition_num. This will de-allocate the page
45 * full access permissions. The permissions are set before,
46 * running a job descriptor. A memory page of secure RAM
58 uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); in caam_page_alloc()
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/openbmc/u-boot/include/
H A Dfsl_sec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
34 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
114 u32 smpart; /* Secure Memory Partition Parameters */
115 u32 smvid; /* Secure Memory Version ID */
116 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
204 * Scatter Gather Entry - Specifies the the Scatter Gather Format
210 uint32_t addr_lo; /* Memory Address - lo */
211 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
213 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
214 uint32_t addr_lo; /* Memory Address - lo */
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/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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/openbmc/linux/drivers/mfd/
H A Dintel-m10-bmc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel MAX 10 Board Management Controller chip - common code
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
12 #include <linux/mfd/intel-m10-bmc.h>
18 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_fw_state_set()
21 down_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
22 m10bmc->bmcfw_state = new_state; in m10bmc_fw_state_set()
23 up_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
29 * handshake registers during a secure update.
33 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_reg_always_available()
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmarvell,icu.txt2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
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/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 …* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.c…
19 u8 pad0[0x08 - 0x00];
24 u8 pad1[0x030 - 0x014 - 4];
26 u8 pad2[0x200 - 0x030 - 4];
28 u8 pad3[0x1000 - 0x200 - 4];
31 u8 pad4[0x1020 - 0x1004 - 4];
49 u8 pad3[0x04C - 0x018 - 4];
59 u8 pad5[0x07C - 0x06C - 4];
61 u8 pad6[0x090 - 0x07C - 4];
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/openbmc/qemu/hw/arm/
H A Darmv7m.c4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/qdev-properties.h"
17 #include "hw/qdev-clock.h"
20 #include "qemu/error-report.h"
25 #include "target/arm/cpu-features.h"
26 #include "target/arm/cpu-qom.h"
31 /* Get the byte address of the real memory for a bitband access. */
34 return s->base | (offset & 0x1ffffff) >> 5; in bitband_addr()
49 addr = bitband_addr(s, offset) & (-size); in bitband_read()
50 res = address_space_read(&s->source_as, addr, attrs, buf, size); in bitband_read()
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/openbmc/u-boot/drivers/mailbox/
H A Dk3-sec-proxy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Texas Instruments' K3 Secure proxy Driver
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
13 #include <linux/soc/ti/k3-sec-proxy.h>
15 #include <mailbox-uclass.h>
37 * struct k3_sec_proxy_desc - Description of secure proxy integration.
42 * @valid_threads: List of Valid threads that the processor can access
55 * struct k3_sec_proxy_thread - Description of a secure proxy Thread
58 * @scfg: Secure Config Region for Thread
71 * struct k3_sec_proxy_mbox - Description of a Secure Proxy Instance
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/openbmc/linux/drivers/perf/
H A Darm_pmu_platform.c1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return !!of_find_property(node, "interrupt-affinity", NULL); in pmu_has_irq_affinity()
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/openbmc/linux/drivers/rtc/
H A Drtc-mxc_v2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
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