Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 /* SPDX-License-Identifier: GPL-2.0+ */
5 …* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.c…
19 u8 pad0[0x08 - 0x00];
24 u8 pad1[0x030 - 0x014 - 4];
26 u8 pad2[0x200 - 0x030 - 4];
28 u8 pad3[0x1000 - 0x200 - 4];
31 u8 pad4[0x1020 - 0x1004 - 4];
49 u8 pad3[0x04C - 0x018 - 4];
59 u8 pad5[0x07C - 0x06C - 4];
61 u8 pad6[0x090 - 0x07C - 4];
67 u8 pad7[0x0B0 - 0x0A0 - 4];
70 u8 pad8[0x0C0 - 0x0B4 - 4];
75 u8 pad9[0x0D4 - 0x0CC - 4];
81 u8 pad11[0x0F0 - 0x0E4 - 4];
102 u8 pad0[0x028 - 0x018 - 4];
107 u8 pad1[0x03c - 0x034 - 4];
112 u8 pad2[0x050 - 0x048 - 4];
113 u32 asfar; /*0x050 AIB Secure First Access Reg*/
114 u32 assar; /*0x054 AIB Secure Second Access Reg*/
115 u8 pad3[0x06c - 0x054 - 4];
118 u8 pad4[0x07c - 0x070 - 4];
120 u8 pad5[0x084 - 0x07c - 4];
129 u32 pad1[0x01C - 0x000];
132 u32 pad2[0x04C - 0x020 - 4];
134 u32 pad3[0x058 - 0x04C - 4];
144 u32 chip_id; /* Chip Id Reg */
146 u32 cpu_conf; /* CPU Conf Reg */
148 u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
151 u32 mcb_conf; /* MCB Conf Reg */