cpu/armv7/virt-v7.c

1 // SPDX-License-Identifier: GPL-2.0+
6  * Routines to transition ARMv7 processors from secure into non-secure state
7  * and from non-secure SVC into HYP mode
15 #include <asm/secure.h>
19 	unsigned int reg;  in read_id_pfr1()  local
21 	asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));  in read_id_pfr1()
22 	return reg;  in read_id_pfr1()
36 	 * encode this). Bail out here since we cannot access this without  in get_gicd_base_address()
40 		printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");  in get_gicd_base_address()
41 		return -1;  in get_gicd_base_address()
55 	size_t sz = __secure_end - __secure_start;  in relocate_secure_section()
78 	if (gic_dist_addr == -1)  in smp_kick_all_cpus()
90 	unsigned int reg;  in armv7_init_nonsec()  local
95 	reg = read_id_pfr1();  in armv7_init_nonsec()
96 	if ((reg & 0xF0) == 0) {  in armv7_init_nonsec()
98 		return -1;  in armv7_init_nonsec()
102 	 * according to the spec one should not tinker with it in secure state  in armv7_init_nonsec()
103 	 * in SVC mode. Do not try to read it once in non-secure state,  in armv7_init_nonsec()
104 	 * any access to it will trap.  in armv7_init_nonsec()
108 	if (gic_dist_addr == -1)  in armv7_init_nonsec()
109 		return -1;  in armv7_init_nonsec()
118 	/* set all bits in the GIC group registers to one to allow access  in armv7_init_nonsec()
119 	 * from non-secure state. The first 32 interrupts are private per  in armv7_init_nonsec()
123 		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);  in armv7_init_nonsec()
128 	 * Relocate secure section before any cpu runs in secure ram.  in armv7_init_nonsec()
129 	 * smp_kick_all_cpus may enable other cores and runs into secure  in armv7_init_nonsec()
130 	 * ram, so need to relocate secure section before enabling other  in armv7_init_nonsec()
136 	smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);  in armv7_init_nonsec()
140 	/* call the non-sec switching code on this CPU also */  in armv7_init_nonsec()