Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
37 - enum:
38 - qcom,qcm2290-smmu-500
39 - qcom,qdu1000-smmu-500
40 - qcom,sa8775p-smmu-500
41 - qcom,sc7180-smmu-500
42 - qcom,sc7280-smmu-500
43 - qcom,sc8180x-smmu-500
44 - qcom,sc8280xp-smmu-500
45 - qcom,sdm670-smmu-500
46 - qcom,sdm845-smmu-500
47 - qcom,sdx55-smmu-500
48 - qcom,sdx65-smmu-500
49 - qcom,sdx75-smmu-500
50 - qcom,sm6115-smmu-500
51 - qcom,sm6125-smmu-500
52 - qcom,sm6350-smmu-500
53 - qcom,sm6375-smmu-500
54 - qcom,sm8150-smmu-500
55 - qcom,sm8250-smmu-500
56 - qcom,sm8350-smmu-500
57 - qcom,sm8450-smmu-500
58 - qcom,sm8550-smmu-500
59 - const: qcom,smmu-500
60 - const: arm,mmu-500
62 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
66 - enum:
67 - qcom,qcm2290-smmu-500
68 - qcom,sc7180-smmu-500
69 - qcom,sc7280-smmu-500
70 - qcom,sc8180x-smmu-500
71 - qcom,sc8280xp-smmu-500
72 - qcom,sdm845-smmu-500
73 - qcom,sm6115-smmu-500
74 - qcom,sm6350-smmu-500
75 - qcom,sm6375-smmu-500
76 - qcom,sm8150-smmu-500
77 - qcom,sm8250-smmu-500
78 - qcom,sm8350-smmu-500
79 - qcom,sm8450-smmu-500
80 - const: arm,mmu-500
81 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
83 - enum:
84 - qcom,sa8775p-smmu-500
85 - qcom,sc7280-smmu-500
86 - qcom,sc8280xp-smmu-500
87 - qcom,sm6115-smmu-500
88 - qcom,sm6125-smmu-500
89 - qcom,sm8150-smmu-500
90 - qcom,sm8250-smmu-500
91 - qcom,sm8350-smmu-500
92 - const: qcom,adreno-smmu
93 - const: qcom,smmu-500
94 - const: arm,mmu-500
95 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
99 - enum:
100 - qcom,sc7280-smmu-500
101 - qcom,sm8150-smmu-500
102 - qcom,sm8250-smmu-500
103 - const: qcom,adreno-smmu
104 - const: arm,mmu-500
105 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
107 - enum:
108 - qcom,msm8996-smmu-v2
109 - qcom,sc7180-smmu-v2
110 - qcom,sdm630-smmu-v2
111 - qcom,sdm845-smmu-v2
112 - qcom,sm6350-smmu-v2
113 - const: qcom,adreno-smmu
114 - const: qcom,smmu-v2
115 - description: Qcom Adreno GPUs on Google Cheza platform
117 - const: qcom,sdm845-smmu-v2
118 - const: qcom,smmu-v2
119 - description: Marvell SoCs implementing "arm,mmu-500"
121 - const: marvell,ap806-smmu-500
122 - const: arm,mmu-500
123 - description: NVIDIA SoCs that require memory controller interaction
124 and may program multiple ARM MMU-500s identically with the memory
128 - enum:
129 - nvidia,tegra186-smmu
130 - nvidia,tegra194-smmu
131 - nvidia,tegra234-smmu
132 - const: nvidia,smmu-500
133 - items:
134 - const: arm,mmu-500
135 - const: arm,smmu-v2
136 - items:
137 - enum:
138 - arm,mmu-400
139 - arm,mmu-401
140 - const: arm,smmu-v1
141 - enum:
142 - arm,smmu-v1
143 - arm,smmu-v2
144 - arm,mmu-400
145 - arm,mmu-401
146 - arm,mmu-500
147 - cavium,smmu-v2
149 reg:
153 '#global-interrupts':
157 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
159 '#iommu-cells':
175 Interrupt list, with the first #global-interrupts entries corresponding to
183 dma-coherent:
191 calxeda,smmu-secure-config-access:
194 Enable proper handling of buggy implementations that always use secure
195 access to SMMU configuration registers. In this case non-secure aliases of
196 secure registers have to be used during SMMU configuration.
198 stream-match-mask:
201 For SMMUs supporting stream matching and using #iommu-cells = <1>,
205 Stream ID (e.g. for certain MMU-500 configurations given globally unique
207 using stream matching with #iommu-cells = <2>, and may be ignored if
210 clock-names:
218 power-domains:
222 nvidia,memory-controller:
234 - compatible
235 - reg
236 - '#global-interrupts'
237 - '#iommu-cells'
238 - interrupts
243 - if:
248 - nvidia,tegra186-smmu
249 - nvidia,tegra194-smmu
250 - nvidia,tegra234-smmu
253 reg:
261 - nvidia,memory-controller
264 reg:
267 - if:
272 - qcom,msm8998-smmu-v2
273 - qcom,sdm630-smmu-v2
276 - properties:
277 clock-names:
279 - const: bus
282 - description: bus clock required for downstream bus access and for
284 - properties:
285 clock-names:
287 - const: iface
288 - const: mem
289 - const: mem_iface
292 - description: interface clock required to access smmu's registers
294 - description: bus clock required for memory access
295 - description: bus clock required for GPU memory access
296 - properties:
297 clock-names:
299 - const: iface-mm
300 - const: iface-smmu
301 - const: bus-smmu
304 - description: interface clock required to access mnoc's registers
306 - description: interface clock required to access smmu's registers
308 - description: bus clock required for the smmu ptw
310 - if:
315 - qcom,sm6375-smmu-v2
318 - properties:
319 clock-names:
321 - const: bus
324 - description: bus clock required for downstream bus access and for
326 - properties:
327 clock-names:
329 - const: iface
330 - const: mem
331 - const: mem_iface
334 - description: interface clock required to access smmu's registers
336 - description: bus clock required for memory access
337 - description: bus clock required for GPU memory access
338 - properties:
339 clock-names:
341 - const: iface-mm
342 - const: iface-smmu
343 - const: bus-mm
344 - const: bus-smmu
347 - description: interface clock required to access mnoc's registers
349 - description: interface clock required to access smmu's registers
351 - description: bus clock required for downstream bus access
352 - description: bus clock required for the smmu ptw
354 - if:
359 - qcom,msm8996-smmu-v2
360 - qcom,sc7180-smmu-v2
361 - qcom,sdm845-smmu-v2
364 clock-names:
366 - const: bus
367 - const: iface
371 - description: bus clock required for downstream bus access and for
373 - description: interface clock required to access smmu's registers
376 - if:
381 - qcom,sa8775p-smmu-500
382 - qcom,sc7280-smmu-500
383 - qcom,sc8280xp-smmu-500
386 clock-names:
388 - const: gcc_gpu_memnoc_gfx_clk
389 - const: gcc_gpu_snoc_dvm_gfx_clk
390 - const: gpu_cc_ahb_clk
391 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
392 - const: gpu_cc_cx_gmu_clk
393 - const: gpu_cc_hub_cx_int_clk
394 - const: gpu_cc_hub_aon_clk
398 - description: GPU memnoc_gfx clock
399 - description: GPU snoc_dvm_gfx clock
400 - description: GPU ahb clock
401 - description: GPU hlos1_vote_GPU smmu clock
402 - description: GPU cx_gmu clock
403 - description: GPU hub_cx_int clock
404 - description: GPU hub_aon clock
406 - if:
411 - qcom,sm6350-smmu-v2
412 - qcom,sm8150-smmu-500
413 - qcom,sm8250-smmu-500
416 clock-names:
418 - const: ahb
419 - const: bus
420 - const: iface
424 - description: bus clock required for AHB bus access
425 - description: bus clock required for downstream bus access and for
427 - description: interface clock required to access smmu's registers
430 - if:
434 - enum:
435 - qcom,sm6115-smmu-500
436 - qcom,sm6125-smmu-500
437 - const: qcom,adreno-smmu
438 - const: qcom,smmu-500
439 - const: arm,mmu-500
442 clock-names:
444 - const: mem
445 - const: hlos
446 - const: iface
450 - description: GPU memory bus clock
451 - description: Voter clock required for HLOS SMMU access
452 - description: Interface clock required for register access
455 - if:
460 - cavium,smmu-v2
461 - marvell,ap806-smmu-500
462 - nvidia,smmu-500
463 - qcom,qcm2290-smmu-500
464 - qcom,qdu1000-smmu-500
465 - qcom,sc7180-smmu-500
466 - qcom,sc8180x-smmu-500
467 - qcom,sdm670-smmu-500
468 - qcom,sdm845-smmu-500
469 - qcom,sdx55-smmu-500
470 - qcom,sdx65-smmu-500
471 - qcom,sm6350-smmu-500
472 - qcom,sm6375-smmu-500
473 - qcom,sm8350-smmu-500
474 - qcom,sm8450-smmu-500
475 - qcom,sm8550-smmu-500
478 clock-names: false
481 - if:
485 const: qcom,sm6375-smmu-500
488 power-domains:
490 - description: SNoC MMU TBU RT GDSC
491 - description: SNoC MMU TBU NRT GDSC
492 - description: SNoC TURING MMU TBU0 GDSC
495 - power-domains
498 power-domains:
502 - |+
505 compatible = "arm,smmu-v1";
506 reg = <0xba5e0000 0x10000>;
507 #global-interrupts = <2>;
514 #iommu-cells = <1>;
526 compatible = "arm,smmu-v1";
527 reg = <0xba5f0000 0x10000>;
528 #global-interrupts = <2>;
535 #iommu-cells = <2>;
550 /* ARM MMU-500 with 10-bit stream ID input configuration */
552 compatible = "arm,mmu-500", "arm,smmu-v2";
553 reg = <0xba600000 0x10000>;
554 #global-interrupts = <2>;
561 #iommu-cells = <1>;
562 /* always ignore appended 5-bit TBU number */
563 stream-match-mask = <0x7c00>;
567 /* bus whose child devices emit one unique 10-bit stream
569 iommu-map = <0 &smmu3 0 0x400>;
574 - |+
575 /* Qcom's arm,smmu-v2 implementation */
576 #include <dt-bindings/interrupt-controller/arm-gic.h>
577 #include <dt-bindings/interrupt-controller/irq.h>
579 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
580 reg = <0xd00000 0x10000>;
582 #global-interrupts = <1>;
586 #iommu-cells = <1>;
587 power-domains = <&mmcc 0>;
591 clock-names = "bus", "iface";