1 // SPDX-License-Identifier: GPL-2.0
4  * Author: Chen-Yu Tsai <wens@csie.org>
7  * which was based on code by Carl van Schaik <carl@ok-labs.com>.
19 #include <asm/secure.h>
32  * The power clamps are located in the unused space after the per-core
63 	u32 reg = ONE_MS * ms;  in __mdelay()  local
65 	cp15_write_cntp_tval(reg);  in __mdelay()
71 		reg = cp15_read_cntp_ctl();  in __mdelay()
72 	} while (!(reg & BIT(2)));  in __mdelay()
133 	writel((u32)entry, &cpucfg->priv0);  in sunxi_set_entry_address()
144 	sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,  in sunxi_cpu_set_power()
163 	sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,  in sunxi_cpu_set_power()
176 		if (readl(&cpucfg->cpu[cpu].status) & BIT(2))  in sunxi_cpu_power_off()
182 	writel(0, &cpucfg->cpu[cpu].rst);  in sunxi_cpu_power_off()
184 	/* Lock CPU (Disable external debug access) */  in sunxi_cpu_power_off()
185 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in sunxi_cpu_power_off()
190 	/* Unlock CPU (Disable external debug access) */  in sunxi_cpu_power_off()
191 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in sunxi_cpu_power_off()
217 	u32 scr, reg, cpu;  in psci_fiq_enter()  local
219 	/* Switch to secure mode */  in psci_fiq_enter()
224 	reg = readl(GICC_BASE + GICC_IAR);  in psci_fiq_enter()
227 	if (reg == 1023 || reg == 1022)  in psci_fiq_enter()
231 	writel(reg, GICC_BASE + GICC_EOIR);  in psci_fiq_enter()
235 	cpu = (reg >> 10) & 0x7;  in psci_fiq_enter()
259 	writel(0, &cpucfg->cpu[cpu].rst);  in psci_cpu_on()
262 	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));  in psci_cpu_on()
264 	/* Lock CPU (Disable external debug access) */  in psci_cpu_on()
265 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in psci_cpu_on()
270 	/* De-assert reset on target CPU */  in psci_cpu_on()
271 	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);  in psci_cpu_on()
273 	/* Unlock CPU (Disable external debug access) */  in psci_cpu_on()
274 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in psci_cpu_on()
294 	u32 reg;  in psci_arch_init()  local
296 	/* SGI15 as Group-0 */  in psci_arch_init()
302 	/* Be cool with non-secure */  in psci_arch_init()
308 	reg = cp15_read_scr();  in psci_arch_init()
309 	reg |= BIT(2);  /* Enable FIQ in monitor mode */  in psci_arch_init()
310 	reg &= ~BIT(0); /* Secure mode */  in psci_arch_init()
311 	cp15_write_scr(reg);  in psci_arch_init()