Lines Matching +full:secure +full:- +full:reg +full:- +full:access

1 // SPDX-License-Identifier: GPL-2.0
3 * Intel MAX 10 Board Management Controller chip - common code
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
12 #include <linux/mfd/intel-m10-bmc.h>
18 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_fw_state_set()
21 down_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
22 m10bmc->bmcfw_state = new_state; in m10bmc_fw_state_set()
23 up_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
29 * handshake registers during a secure update.
33 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_reg_always_available()
36 return !regmap_reg_in_ranges(offset, m10bmc->info->handshake_sys_reg_ranges, in m10bmc_reg_always_available()
37 m10bmc->info->handshake_sys_reg_nranges); in m10bmc_reg_always_available()
41 * m10bmc_handshake_reg_unavailable - Checks if reg access collides with secure update state
45 * handshake registers during a secure update erase and write phases.
47 * Context: @m10bmc->bmcfw_lock must be held.
51 return m10bmc->bmcfw_state == M10BMC_FW_STATE_SEC_UPDATE_PREPARE || in m10bmc_handshake_reg_unavailable()
52 m10bmc->bmcfw_state == M10BMC_FW_STATE_SEC_UPDATE_WRITE; in m10bmc_handshake_reg_unavailable()
63 const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map; in m10bmc_sys_read()
67 return m10bmc_raw_read(m10bmc, csr_map->base + offset, val); in m10bmc_sys_read()
69 down_read(&m10bmc->bmcfw_lock); in m10bmc_sys_read()
71 ret = -EBUSY; /* Reg not available during secure update */ in m10bmc_sys_read()
73 ret = m10bmc_raw_read(m10bmc, csr_map->base + offset, val); in m10bmc_sys_read()
74 up_read(&m10bmc->bmcfw_lock); in m10bmc_sys_read()
83 const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map; in m10bmc_sys_update_bits()
87 return regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val); in m10bmc_sys_update_bits()
89 down_read(&m10bmc->bmcfw_lock); in m10bmc_sys_update_bits()
91 ret = -EBUSY; /* Reg not available during secure update */ in m10bmc_sys_update_bits()
93 ret = regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val); in m10bmc_sys_update_bits()
94 up_read(&m10bmc->bmcfw_lock); in m10bmc_sys_update_bits()
107 ret = m10bmc_sys_read(ddata, ddata->info->csr_map->build_version, &val); in bmc_version_show()
122 ret = m10bmc_sys_read(ddata, ddata->info->csr_map->fw_version, &val); in bmcfw_version_show()
137 ret = m10bmc_sys_read(ddata, ddata->info->csr_map->mac_low, &macaddr_low); in mac_address_show()
141 ret = m10bmc_sys_read(ddata, ddata->info->csr_map->mac_high, &macaddr_high); in mac_address_show()
162 ret = m10bmc_sys_read(ddata, ddata->info->csr_map->mac_high, &macaddr_high); in mac_count_show()
192 m10bmc->info = info; in m10bmc_dev_init()
193 dev_set_drvdata(m10bmc->dev, m10bmc); in m10bmc_dev_init()
194 init_rwsem(&m10bmc->bmcfw_lock); in m10bmc_dev_init()
196 ret = devm_mfd_add_devices(m10bmc->dev, PLATFORM_DEVID_AUTO, in m10bmc_dev_init()
197 info->cells, info->n_cells, in m10bmc_dev_init()
200 dev_err(m10bmc->dev, "Failed to register sub-devices: %d\n", ret); in m10bmc_dev_init()