Lines Matching +full:secure +full:- +full:reg +full:- +full:access
19 /* Return a 32-bit mask which should be applied for this set of 32 in mask_group()
20 * interrupts; each bit is 1 if access is permitted by the in mask_group()
21 * combination of attrs.secure and GICR_GROUPR. (GICR_NSACR does in mask_group()
24 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in mask_group()
25 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in mask_group()
26 return cs->gicr_igroupr0; in mask_group()
35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
39 uint32_t *reg, uint32_t val) in gicr_write_bitmap_reg() argument
43 *reg = val; in gicr_write_bitmap_reg()
48 uint32_t *reg, uint32_t val) in gicr_write_set_bitmap_reg() argument
50 /* Helper routine to implement writing to a "set-bitmap" register */ in gicr_write_set_bitmap_reg()
52 *reg |= val; in gicr_write_set_bitmap_reg()
57 uint32_t *reg, uint32_t val) in gicr_write_clear_bitmap_reg() argument
59 /* Helper routine to implement writing to a "clear-bitmap" register */ in gicr_write_clear_bitmap_reg()
61 *reg &= ~val; in gicr_write_clear_bitmap_reg()
66 uint32_t reg) in gicr_read_bitmap_reg() argument
68 reg &= mask_group(cs, attrs); in gicr_read_bitmap_reg()
69 return reg; in gicr_read_bitmap_reg()
79 if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) { in vcpu_resident()
82 return vptaddr == (cs->gicr_vpendbaser & R_GICR_VPENDBASER_PHYADDR_MASK); in vcpu_resident()
105 address_space_read(&cs->gic->dma_as, in update_for_one_lpi()
106 ctbase + ((irq - GICV3_LPI_INTID_START) * sizeof(lpite)), in update_for_one_lpi()
119 if ((prio < hpp->prio) || in update_for_one_lpi()
120 ((prio == hpp->prio) && (irq <= hpp->irq))) { in update_for_one_lpi()
121 hpp->irq = irq; in update_for_one_lpi()
122 hpp->prio = prio; in update_for_one_lpi()
123 hpp->nmi = false; in update_for_one_lpi()
124 /* LPIs and vLPIs are always non-secure Grp1 interrupts */ in update_for_one_lpi()
125 hpp->grp = GICV3_G1NS; in update_for_one_lpi()
146 * We take @ptsizebits in the form idbits-1 because this is the way that
154 AddressSpace *as = &cs->gic->dma_as; in update_for_all_lpis()
159 hpp->prio = 0xff; in update_for_all_lpis()
160 hpp->nmi = false; in update_for_all_lpis()
186 AddressSpace *as = &cs->gic->dma_as; in set_pending_table_bit()
204 * honouring security state (these are RAZ/WI for Group 0 or Secure in gicr_read_ipriorityr()
209 prio = cs->gicr_ipriorityr[irq]; in gicr_read_ipriorityr()
211 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicr_read_ipriorityr()
212 if (!(cs->gicr_igroupr0 & (1U << irq))) { in gicr_read_ipriorityr()
213 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in gicr_read_ipriorityr()
226 * honouring security state (these are RAZ/WI for Group 0 or Secure in gicr_write_ipriorityr()
229 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicr_write_ipriorityr()
230 if (!(cs->gicr_igroupr0 & (1U << irq))) { in gicr_write_ipriorityr()
231 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in gicr_write_ipriorityr()
237 cs->gicr_ipriorityr[irq] = value; in gicr_write_ipriorityr()
244 if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) { in gicv3_redist_update_vlpi_only()
245 cs->hppvlpi.prio = 0xff; in gicv3_redist_update_vlpi_only()
246 cs->hppvlpi.nmi = false; in gicv3_redist_update_vlpi_only()
250 ptbase = cs->gicr_vpendbaser & R_GICR_VPENDBASER_PHYADDR_MASK; in gicv3_redist_update_vlpi_only()
251 ctbase = cs->gicr_vpropbaser & R_GICR_VPROPBASER_PHYADDR_MASK; in gicv3_redist_update_vlpi_only()
252 idbits = FIELD_EX64(cs->gicr_vpropbaser, GICR_VPROPBASER, IDBITS); in gicv3_redist_update_vlpi_only()
254 update_for_all_lpis(cs, ptbase, ctbase, idbits, true, &cs->hppvlpi); in gicv3_redist_update_vlpi_only()
266 bool oldvalid = FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID); in gicr_write_vpendbaser()
271 * The DIRTY bit is read-only and for us is always zero; in gicr_write_vpendbaser()
287 if (cs->gicr_vpendbaser ^ newval) { in gicr_write_vpendbaser()
295 cs->gicr_vpendbaser = newval; in gicr_write_vpendbaser()
314 pendinglast = cs->hppvlpi.prio != 0xff; in gicr_write_vpendbaser()
318 cs->gicr_vpendbaser = newval; in gicr_write_vpendbaser()
327 *data = gicr_read_ipriorityr(cs, attrs, offset - GICR_IPRIORITYR); in gicr_readb()
339 gicr_write_ipriorityr(cs, attrs, offset - GICR_IPRIORITYR, value); in gicr_writeb()
352 *data = cs->gicr_ctlr; in gicr_readl()
358 *data = extract64(cs->gicr_typer, 0, 32); in gicr_readl()
361 *data = extract64(cs->gicr_typer, 32, 32); in gicr_readl()
370 *data = cs->gicr_waker; in gicr_readl()
373 *data = extract64(cs->gicr_propbaser, 0, 32); in gicr_readl()
376 *data = extract64(cs->gicr_propbaser, 32, 32); in gicr_readl()
379 *data = extract64(cs->gicr_pendbaser, 0, 32); in gicr_readl()
382 *data = extract64(cs->gicr_pendbaser, 32, 32); in gicr_readl()
385 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicr_readl()
389 *data = cs->gicr_igroupr0; in gicr_readl()
393 *data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_ienabler0); in gicr_readl()
399 * latch and the input line level for level-triggered interrupts. in gicr_readl()
401 uint32_t val = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level); in gicr_readl()
407 *data = gicr_read_bitmap_reg(cs, attrs, cs->gicr_iactiver0); in gicr_readl()
411 int i, irq = offset - GICR_IPRIORITYR; in gicr_readl()
414 for (i = irq + 3; i >= irq; i--) { in gicr_readl()
422 *data = cs->gic->nmi_support ? in gicr_readl()
423 gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0; in gicr_readl()
433 value = cs->edge_trigger & mask_group(cs, attrs); in gicr_readl()
440 if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicr_readl()
442 * security enabled and this is an NS access in gicr_readl()
447 *data = cs->gicr_igrpmodr0; in gicr_readl()
450 if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicr_readl()
452 * security enabled and this is an NS access in gicr_readl()
457 *data = cs->gicr_nsacr; in gicr_readl()
460 *data = gicv3_idreg(cs->gic, offset - GICR_IDREGS, GICV3_PIDR0_REDIST); in gicr_readl()
465 * prevent pre-v4 GIC from passing us offsets this high. in gicr_readl()
468 *data = extract64(cs->gicr_vpropbaser, 0, 32); in gicr_readl()
471 *data = extract64(cs->gicr_vpropbaser, 32, 32); in gicr_readl()
474 *data = extract64(cs->gicr_vpendbaser, 0, 32); in gicr_readl()
477 *data = extract64(cs->gicr_vpendbaser, 32, 32); in gicr_readl()
494 if (cs->gicr_typer & GICR_TYPER_PLPIS) { in gicr_writel()
496 cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS; in gicr_writel()
500 cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS; in gicr_writel()
501 /* cs->hppi might have been an LPI; recalculate */ in gicr_writel()
525 cs->gicr_waker = value; in gicr_writel()
528 cs->gicr_propbaser = deposit64(cs->gicr_propbaser, 0, 32, value); in gicr_writel()
531 cs->gicr_propbaser = deposit64(cs->gicr_propbaser, 32, 32, value); in gicr_writel()
534 cs->gicr_pendbaser = deposit64(cs->gicr_pendbaser, 0, 32, value); in gicr_writel()
537 cs->gicr_pendbaser = deposit64(cs->gicr_pendbaser, 32, 32, value); in gicr_writel()
540 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicr_writel()
543 cs->gicr_igroupr0 = value; in gicr_writel()
547 gicr_write_set_bitmap_reg(cs, attrs, &cs->gicr_ienabler0, value); in gicr_writel()
550 gicr_write_clear_bitmap_reg(cs, attrs, &cs->gicr_ienabler0, value); in gicr_writel()
553 gicr_write_set_bitmap_reg(cs, attrs, &cs->gicr_ipendr0, value); in gicr_writel()
556 gicr_write_clear_bitmap_reg(cs, attrs, &cs->gicr_ipendr0, value); in gicr_writel()
559 gicr_write_set_bitmap_reg(cs, attrs, &cs->gicr_iactiver0, value); in gicr_writel()
562 gicr_write_clear_bitmap_reg(cs, attrs, &cs->gicr_iactiver0, value); in gicr_writel()
566 int i, irq = offset - GICR_IPRIORITYR; in gicr_writel()
575 if (cs->gic->nmi_support) { in gicr_writel()
576 gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value); in gicr_writel()
588 * 32-bits will compress down into 16 bits which we need in gicr_writel()
594 cs->edge_trigger &= ~mask; in gicr_writel()
595 cs->edge_trigger |= (value & mask); in gicr_writel()
601 if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicr_writel()
603 * security enabled and this is an NS access in gicr_writel()
607 cs->gicr_igrpmodr0 = value; in gicr_writel()
611 if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicr_writel()
613 * security enabled and this is an NS access in gicr_writel()
617 cs->gicr_nsacr = value; in gicr_writel()
618 /* no update required as this only affects access permission checks */ in gicr_writel()
631 * prevent pre-v4 GIC from passing us offsets this high. in gicr_writel()
634 cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 0, 32, value); in gicr_writel()
637 cs->gicr_vpropbaser = deposit64(cs->gicr_vpropbaser, 32, 32, value); in gicr_writel()
640 gicr_write_vpendbaser(cs, deposit64(cs->gicr_vpendbaser, 0, 32, value)); in gicr_writel()
643 gicr_write_vpendbaser(cs, deposit64(cs->gicr_vpendbaser, 32, 32, value)); in gicr_writel()
655 *data = cs->gicr_typer; in gicr_readll()
658 *data = cs->gicr_propbaser; in gicr_readll()
661 *data = cs->gicr_pendbaser; in gicr_readll()
666 * prevent pre-v4 GIC from passing us offsets this high. in gicr_readll()
669 *data = cs->gicr_vpropbaser; in gicr_readll()
672 *data = cs->gicr_vpendbaser; in gicr_readll()
684 cs->gicr_propbaser = value; in gicr_writell()
687 cs->gicr_pendbaser = value; in gicr_writell()
698 * prevent pre-v4 GIC from passing us offsets this high. in gicr_writell()
701 cs->gicr_vpropbaser = value; in gicr_writell()
715 GICv3State *s = region->gic; in gicv3_redist_read()
720 assert((offset & (size - 1)) == 0); in gicv3_redist_read()
730 cpuidx = region->cpuidx + offset / gicv3_redist_size(s); in gicv3_redist_read()
733 cs = &s->cpu[cpuidx]; in gicv3_redist_read()
755 size, attrs.secure); in gicv3_redist_read()
758 * trigger the guest-error logging but don't return it to in gicv3_redist_read()
765 size, attrs.secure); in gicv3_redist_read()
774 GICv3State *s = region->gic; in gicv3_redist_write()
779 assert((offset & (size - 1)) == 0); in gicv3_redist_write()
789 cpuidx = region->cpuidx + offset / gicv3_redist_size(s); in gicv3_redist_write()
792 cs = &s->cpu[cpuidx]; in gicv3_redist_write()
814 size, attrs.secure); in gicv3_redist_write()
817 * trigger the guest-error logging but don't return it to in gicv3_redist_write()
823 size, attrs.secure); in gicv3_redist_write()
830 uint64_t lpict_baddr = cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK; in gicv3_redist_check_lpi_priority()
833 cs->gic->gicd_ctlr & GICD_CTLR_DS, in gicv3_redist_check_lpi_priority()
834 &cs->hpplpi); in gicv3_redist_check_lpi_priority()
849 idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS), in gicv3_redist_update_lpi_only()
852 if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { in gicv3_redist_update_lpi_only()
856 lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; in gicv3_redist_update_lpi_only()
857 lpict_baddr = cs->gicr_propbaser & R_GICR_PROPBASER_PHYADDR_MASK; in gicv3_redist_update_lpi_only()
860 cs->gic->gicd_ctlr & GICD_CTLR_DS, &cs->hpplpi); in gicv3_redist_update_lpi_only()
877 lpipt_baddr = cs->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; in gicv3_redist_lpi_pending()
891 if (irq == cs->hpplpi.irq) { in gicv3_redist_lpi_pending()
901 idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS), in gicv3_redist_process_lpi()
904 if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || in gicv3_redist_process_lpi()
905 (irq > (1ULL << (idbits + 1)) - 1) || irq < GICV3_LPI_INTID_START) { in gicv3_redist_process_lpi()
938 if (!(src->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || in gicv3_redist_mov_lpi()
939 !(dest->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { in gicv3_redist_mov_lpi()
943 idbits = MIN(FIELD_EX64(src->gicr_propbaser, GICR_PROPBASER, IDBITS), in gicv3_redist_mov_lpi()
945 idbits = MIN(FIELD_EX64(dest->gicr_propbaser, GICR_PROPBASER, IDBITS), in gicv3_redist_mov_lpi()
953 src_baddr = src->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; in gicv3_redist_mov_lpi()
959 if (irq == src->hpplpi.irq) { in gicv3_redist_mov_lpi()
961 * We just made this LPI not-pending so only need to update in gicv3_redist_mov_lpi()
975 * src, we must set it not-pending on src and pending on dest. in gicv3_redist_movall_lpis()
982 AddressSpace *as = &src->gic->dma_as; in gicv3_redist_movall_lpis()
988 if (!(src->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || in gicv3_redist_movall_lpis()
989 !(dest->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { in gicv3_redist_movall_lpis()
993 idbits = MIN(FIELD_EX64(src->gicr_propbaser, GICR_PROPBASER, IDBITS), in gicv3_redist_movall_lpis()
995 idbits = MIN(FIELD_EX64(dest->gicr_propbaser, GICR_PROPBASER, IDBITS), in gicv3_redist_movall_lpis()
999 src_baddr = src->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; in gicv3_redist_movall_lpis()
1000 dest_baddr = dest->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; in gicv3_redist_movall_lpis()
1034 vptbase = FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, PHYADDR) << 16; in gicv3_redist_vlpi_pending()
1039 ctbase = cs->gicr_vpropbaser & R_GICR_VPROPBASER_PHYADDR_MASK; in gicv3_redist_vlpi_pending()
1040 update_for_one_lpi(cs, irq, ctbase, true, &cs->hppvlpi); in gicv3_redist_vlpi_pending()
1044 if (irq == cs->hppvlpi.irq) { in gicv3_redist_vlpi_pending()
1059 uint32_t idbits = FIELD_EX64(cs->gicr_vpropbaser, GICR_VPROPBASER, IDBITS); in gicv3_redist_process_vlpi()
1069 ctbase = cs->gicr_vpropbaser & R_GICR_VPROPBASER_PHYADDR_MASK; in gicv3_redist_process_vlpi()
1070 update_for_one_lpi(cs, irq, ctbase, true, &cs->hppvlpi); in gicv3_redist_process_vlpi()
1074 if (irq == cs->hppvlpi.irq) { in gicv3_redist_process_vlpi()
1081 (cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { in gicv3_redist_process_vlpi()
1099 if (vcpu_resident(src, src_vptaddr) && irq == src->hppvlpi.irq) { in gicv3_redist_mov_vlpi()
1101 * Update src's cached highest-priority pending vLPI if we just made in gicv3_redist_mov_vlpi()
1102 * it not-pending in gicv3_redist_mov_vlpi()
1138 if (level == extract32(cs->level, irq, 1)) { in gicv3_redist_set_irq()
1144 cs->level = deposit32(cs->level, irq, 1, level); in gicv3_redist_set_irq()
1147 /* 0->1 edges latch the pending bit for edge-triggered interrupts */ in gicv3_redist_set_irq()
1148 if (extract32(cs->edge_trigger, irq, 1)) { in gicv3_redist_set_irq()
1149 cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 1); in gicv3_redist_set_irq()
1159 int irqgrp = gicv3_irq_group(cs->gic, cs, irq); in gicv3_redist_send_sgi()
1161 /* If we are asked for a Secure Group 1 SGI and it's actually in gicv3_redist_send_sgi()
1162 * configured as Secure Group 0 this is OK (subject to the usual in gicv3_redist_send_sgi()
1173 if (ns && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicv3_redist_send_sgi()
1185 cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 1); in gicv3_redist_send_sgi()