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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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H A Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek STAR Ethernet MAC Controller
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
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H A Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
22 - nxp,imx93-dwmac-eqos
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H A Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
21 MAC can generate it.
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
24 possible values from "txclk", "clk_125" or "clkgen".
26 - sti-ethclk: this is the phy clock.
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
79 struct clk *rmii_internal_clk;
103 /* list of clocks required for mac */
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
[all …]
H A Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
9 #include <linux/clk.h>
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
46 * RMII | 1 | 0 | 0 | n/a |
47 *------------------------------------------
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H A Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
18 #include <linux/clk.h>
43 * ------------------------------------------------
46 * ------------------------------------------------
48 *| | clk-125/txclk | txclk |
49 * ------------------------------------------------
51 *| | clk-125/txclk | clkgen |
53 * ------------------------------------------------
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H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
50 /* Bypass (= 0, the signal from the GPIO input directly connects to the
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
94 struct clk *rgmii_tx_clk;
97 struct clk *timing_adj_clk;
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
119 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, in meson8b_dwmac_register_clk()
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H A Ddwmac-rk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
12 #include <linux/clk.h>
74 struct clk *clk_mac;
75 struct clk *clk_phy;
106 struct device *dev = &bsp_priv->pdev->dev; in px30_set_to_rmii()
108 if (IS_ERR(bsp_priv->grf)) { in px30_set_to_rmii()
113 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_to_rmii()
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H A Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
39 * @soc_has_internal_phy: Does the MAC embed an internal PHY
40 * @support_mii: Does the MAC handle MII
41 * @support_rmii: Does the MAC handle RMII
42 * @support_rgmii: Does the MAC handle RGMII
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/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2600.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2600-clock.h>
16 #include <dt-bindings/reset/ast2600-reset.h>
19 * SCU 80 & 90 clock stop control for MAC controllers
27 * MAC Clock Delay settings
123 * TGMII Clock Duty constants, taken from Aspeed SDK
134 * For H-PLL and M-PLL the formula is
136 * M - Numerator
137 * N - Denumerator
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H A Dclk_ast2500.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2500-clock.h>
16 #include <dt-bindings/reset/ast2500-reset.h>
19 * MAC Clock Delay settings, taken from Aspeed SDK
25 * TGMII Clock Duty constants, taken from Aspeed SDK
36 * For H-PLL and M-PLL the formula is
38 * M - Numerator
39 * N - Denumerator
40 * P - Post Divider
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/openbmc/u-boot/drivers/net/
H A Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0+
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
4 * Copyright 2016-2018 Socionext inc.
7 #include <clk.h>
34 /* MAC Register Group */
37 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
38 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
61 /* RMII Bridge Register Group */
69 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
72 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
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H A Dfec_mxc.c1 // SPDX-License-Identifier: GPL-2.0+
25 #include <asm/arch/imx-regs.h>
26 #include <asm/mach-imx/sys_proto.h>
27 #include <asm-generic/gpio.h>
40 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
41 * 64-byte alignment in the DMA RX FEC buffer.
43 * satisfies the alignment on other SoCs (32-bytes)
87 /* MII-interface related functions */
97 * reading from any PHY's register is done by properly in fec_mdio_read()
100 writel(FEC_IEVENT_MII, &eth->ievent); in fec_mdio_read()
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/openbmc/u-boot/arch/arm/dts/
H A Dam335x-draco.dts4 * Copyright (C) 2014 - Lukas Stockmann <lukas.stockmann@siemens.com>
11 /dts-v1/;
14 #include "am335x-draco.dtsi"
15 #include <dt-bindings/input/input.h>
21 /* ethernet alias is needed for the MAC address passing from U-Boot */
24 mdio-gpio0 = &mdio0;
27 gpio-keys {
28 compatible = "gpio-keys";
52 pinctrl-names = "default";
53 pinctrl-0 = <&gpio_mux_pins>;
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/openbmc/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
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/openbmc/linux/drivers/net/phy/
H A Ddp83td510.c1 // SPDX-License-Identifier: GPL-2.0
15 /* Bit 7 - mii_interrupt, active high. Clears on read.
17 * This differs from the DP83TD510E datasheet (2020) which states this bit
40 * "Application Report - DP83TD510E Cable Diagnostics Toolkit":
41 * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
42 * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
43 * features for 100BASE-T1 automotive Ethernet PHYs"
60 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83td510_config_intr()
112 phydev->speed = SPEED_UNKNOWN; in dp83td510_read_status()
113 phydev->duplex = DUPLEX_UNKNOWN; in dp83td510_read_status()
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/openbmc/linux/drivers/net/ethernet/socionext/
H A Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
38 /* MAC Register Group */
41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
84 /* RMII Bridge Register Group */
93 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
98 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
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/openbmc/linux/drivers/net/ethernet/actions/
H A Dowl-emac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Actions Semi Owl SoCs Ethernet MAC driver
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
19 #include "owl-emac.h"
27 return readl(priv->base + reg); in owl_emac_reg_read()
32 writel(data, priv->base + reg); in owl_emac_reg_write()
63 return priv->netdev->dev.parent; in owl_emac_get_dev()
84 * unexpected side effect (MAC hardware bug?!) where some bits in the in owl_emac_irq_disable()
129 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); in owl_emac_dma_map_tx()
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/openbmc/linux/drivers/net/ethernet/faraday/
H A Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
90 struct clk *clk; member
92 /* AST2500/AST2600 RMII ref clock gate */
93 struct clk *rclk;
116 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
120 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); in ftgmac100_reset_mac()
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/openbmc/linux/drivers/net/ethernet/nxp/
H A Dlpc_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/clk.h>
23 #include <linux/soc/nxp/lpc32xx-misc.h>
25 #define MODNAME "lpc-eth"
35 * Ethernet MAC controller Register offsets
317 if (dev && dev->of_node) { in lpc_phy_interface_mode()
318 const char *mode = of_get_property(dev->of_node, in lpc_phy_interface_mode()
319 "phy-mode", NULL); in lpc_phy_interface_mode()
328 if (dev && dev->of_node) in use_iram_for_net()
329 return of_property_read_bool(dev->of_node, "use-iram"); in use_iram_for_net()
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/openbmc/u-boot/board/ti/am335x/
H A Dboard.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
44 /* GPIO that controls power to DDR on EVM-SK */
67 * Read header information from EEPROM into global structure.
247 /* break into full u-boot on 'c' */ in spl_start_uboot()
442 sil_rev = readl(&cdev->deviceid) >> 28; in scale_vcores_generic()
610 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
664 /* check for phy_id as well as phy-handle properties */ in ft_board_setup()
679 "phy-handle"); in ft_board_setup()
683 ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT); in ft_board_setup()
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/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc3250-phy3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PHYTEC phyCORE-LPC3250 board
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 /dts-v1/;
13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
22 compatible = "gpio-leds";
26 default-state = "off";
31 linux,default-trigger = "heartbeat";
37 power-supply = <&reg_lcd>;
41 remote-endpoint = <&cldc_output>;
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H A Dlpc3250-ea3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
20 gpio-keys {
21 compatible = "gpio-keys";
86 compatible = "gpio-leds";
92 linux,default-trigger = "timer";
93 default-state = "off";
98 default-state = "off";
103 default-state = "off";
108 default-state = "off";
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/openbmc/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
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