191f3fd11SBartosz Golaszewski# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 291f3fd11SBartosz Golaszewski%YAML 1.2 391f3fd11SBartosz Golaszewski--- 491f3fd11SBartosz Golaszewski$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml# 591f3fd11SBartosz Golaszewski$schema: http://devicetree.org/meta-schemas/core.yaml# 691f3fd11SBartosz Golaszewski 791f3fd11SBartosz Golaszewskititle: MediaTek STAR Ethernet MAC Controller 891f3fd11SBartosz Golaszewski 991f3fd11SBartosz Golaszewskimaintainers: 1091f3fd11SBartosz Golaszewski - Bartosz Golaszewski <bgolaszewski@baylibre.com> 1191f3fd11SBartosz Golaszewski 1291f3fd11SBartosz Golaszewskidescription: 1391f3fd11SBartosz Golaszewski This Ethernet MAC is used on the MT8* family of SoCs from MediaTek. 1491f3fd11SBartosz Golaszewski It's compliant with 802.3 standards and supports half- and full-duplex 1591f3fd11SBartosz Golaszewski modes with flow-control as well as CRC offloading and VLAN tags. 1691f3fd11SBartosz Golaszewski 1791f3fd11SBartosz GolaszewskiallOf: 18*3079bfdbSRob Herring - $ref: ethernet-controller.yaml# 1991f3fd11SBartosz Golaszewski 2091f3fd11SBartosz Golaszewskiproperties: 2191f3fd11SBartosz Golaszewski compatible: 2291f3fd11SBartosz Golaszewski enum: 2391f3fd11SBartosz Golaszewski - mediatek,mt8516-eth 2491f3fd11SBartosz Golaszewski - mediatek,mt8518-eth 2591f3fd11SBartosz Golaszewski - mediatek,mt8175-eth 2643360697SBiao Huang - mediatek,mt8365-eth 2791f3fd11SBartosz Golaszewski 2891f3fd11SBartosz Golaszewski reg: 2991f3fd11SBartosz Golaszewski maxItems: 1 3091f3fd11SBartosz Golaszewski 3191f3fd11SBartosz Golaszewski interrupts: 3291f3fd11SBartosz Golaszewski maxItems: 1 3391f3fd11SBartosz Golaszewski 3491f3fd11SBartosz Golaszewski clocks: 3591f3fd11SBartosz Golaszewski minItems: 3 3691f3fd11SBartosz Golaszewski maxItems: 3 3791f3fd11SBartosz Golaszewski 3891f3fd11SBartosz Golaszewski clock-names: 3991f3fd11SBartosz Golaszewski additionalItems: false 4091f3fd11SBartosz Golaszewski items: 4191f3fd11SBartosz Golaszewski - const: core 4291f3fd11SBartosz Golaszewski - const: reg 4391f3fd11SBartosz Golaszewski - const: trans 4491f3fd11SBartosz Golaszewski 4591f3fd11SBartosz Golaszewski mediatek,pericfg: 46d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/phandle 4791f3fd11SBartosz Golaszewski description: 4891f3fd11SBartosz Golaszewski Phandle to the device containing the PERICFG register range. This is used 4991f3fd11SBartosz Golaszewski to control the MII mode. 5091f3fd11SBartosz Golaszewski 51320c49feSBiao Huang mediatek,rmii-rxc: 52320c49feSBiao Huang type: boolean 53320c49feSBiao Huang description: 54320c49feSBiao Huang If present, indicates that the RMII reference clock, which is from external 55320c49feSBiao Huang PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. 56320c49feSBiao Huang 57320c49feSBiao Huang mediatek,rxc-inverse: 58320c49feSBiao Huang type: boolean 59320c49feSBiao Huang description: 60320c49feSBiao Huang If present, indicates that clock on RXC pad will be inversed. 61320c49feSBiao Huang 62320c49feSBiao Huang mediatek,txc-inverse: 63320c49feSBiao Huang type: boolean 64320c49feSBiao Huang description: 65320c49feSBiao Huang If present, indicates that clock on TXC pad will be inversed. 66320c49feSBiao Huang 6791f3fd11SBartosz Golaszewski mdio: 68b2d28642SRob Herring $ref: mdio.yaml# 69b2d28642SRob Herring unevaluatedProperties: false 7091f3fd11SBartosz Golaszewski 7191f3fd11SBartosz Golaszewskirequired: 7291f3fd11SBartosz Golaszewski - compatible 7391f3fd11SBartosz Golaszewski - reg 7491f3fd11SBartosz Golaszewski - interrupts 7591f3fd11SBartosz Golaszewski - clocks 7691f3fd11SBartosz Golaszewski - clock-names 7791f3fd11SBartosz Golaszewski - mediatek,pericfg 7891f3fd11SBartosz Golaszewski - phy-handle 7991f3fd11SBartosz Golaszewski 806fdc6e23SRob HerringunevaluatedProperties: false 816fdc6e23SRob Herring 8291f3fd11SBartosz Golaszewskiexamples: 8391f3fd11SBartosz Golaszewski - | 8491f3fd11SBartosz Golaszewski #include <dt-bindings/interrupt-controller/arm-gic.h> 8591f3fd11SBartosz Golaszewski #include <dt-bindings/clock/mt8516-clk.h> 8691f3fd11SBartosz Golaszewski 8791f3fd11SBartosz Golaszewski ethernet: ethernet@11180000 { 8891f3fd11SBartosz Golaszewski compatible = "mediatek,mt8516-eth"; 8991f3fd11SBartosz Golaszewski reg = <0x11180000 0x1000>; 9091f3fd11SBartosz Golaszewski mediatek,pericfg = <&pericfg>; 9191f3fd11SBartosz Golaszewski interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; 9291f3fd11SBartosz Golaszewski clocks = <&topckgen CLK_TOP_RG_ETH>, 9391f3fd11SBartosz Golaszewski <&topckgen CLK_TOP_66M_ETH>, 9491f3fd11SBartosz Golaszewski <&topckgen CLK_TOP_133M_ETH>; 9591f3fd11SBartosz Golaszewski clock-names = "core", "reg", "trans"; 9691f3fd11SBartosz Golaszewski phy-handle = <ð_phy>; 9791f3fd11SBartosz Golaszewski phy-mode = "rmii"; 9891f3fd11SBartosz Golaszewski 9991f3fd11SBartosz Golaszewski mdio { 10091f3fd11SBartosz Golaszewski #address-cells = <1>; 10191f3fd11SBartosz Golaszewski #size-cells = <0>; 10291f3fd11SBartosz Golaszewski 10391f3fd11SBartosz Golaszewski eth_phy: ethernet-phy@0 { 10491f3fd11SBartosz Golaszewski reg = <0>; 10591f3fd11SBartosz Golaszewski }; 10691f3fd11SBartosz Golaszewski }; 10791f3fd11SBartosz Golaszewski }; 108